Hello,
I have a custom board with a iMX8QM, and need to use a dual link MIPI-DSI for a 1920x1080p@60 LCD screen. How should the device tree be structured to use two DSI ports for a single LCD panel? The DS90UB941 Serializer accepts even data on channel 1 and odd data on channel 2. I've tried structuring my device tree as shown below, but I get DRM errors and the video device is never created. If I put the panel inside the MIPI node the errors go away, but that seems to only work for single-channel DSI. How should the device tree be structured to support dual-channel DSI for a LCD?
panel1: panel1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
compatible = "raydium,rm67191";
reg = <0>;
dsi-lanes = <4>;
video-mode = <2>;
width-mm = <292>;
height-mm = <109>;
port@0 {
reg = <0>;
panel1_input: endpoint {
remote-endpoint = <&mipi0_out>;
};
};
port@1 {
reg = <1>;
panel1_input2: endpoint {
remote-endpoint = <&mipi1_out>;
};
};
};
&mipi0_dphy {
status = "okay";
};
&mipi1_dphy {
status = "okay";
};
&mipi0_dsi_host {
status = "okay";
fsl,clock-drop-level = <2>;
ports {
port@1 {
reg = <1>;
mipi0_out: endpoint {
remote-endpoint = <&panel1_input>;
};
};
};
};
&mipi1_dsi_host {
status = "okay";
fsl,clock-drop-level = <2>;
ports {
port@1 {
reg = <1>;
mipi1_out: endpoint {
remote-endpoint = <&panel1_input2>;
};
};
};
};Hi @joanxie,
I'm connecting to the DS90UB941 via I2C and setting the necessary registers in the device tree. I was under the impression that I would need to output even data on one DSI channel and odd data on the second DSI channel, but after talking with TI it turns out that I can supply a single channel DSI as you suggested and the serializer will automatically adjust based on the PCLK frequency. Therefore, I think this topic can be closed. Thank you!
how do you connect DS90UB941? I don't find you set this in the dts file, and one mipi dsi can support 148Mhz, why do you need to use dual mipi dsi? and you couldn't combine dual mipi dsi into one to support display
Hi @joanxie, yes that is true, but the max pixel clock the TI DS90UB941 serializer can support is 105MHz, so it requires using two DSI channels to support up to 210MHz pixel clock. For 1920x1080p@60 the pixel clock required is 147.5MHz, so that is why I must split it into two DSI channels.
How should the device tree be structured to support this?
why do you need to set as this? one mipi dsi can support 1080p@60 already, why do you need to connect with 2 mipi dsi interface?