MIMXRT1170 EVK flexspi issues I'm using the MIMXRT1170 EVK with the IAR tool set.  I am running the flexspi_nor_polling_transfer project from the driver_examples provided with the SDK.  I am building the debug project target which should NOT use the flexspi flash as I understand it.  The program fails on a memory compare between the program buffer and the read buffer.  I have not modified any of the code, the project is as provided in SDK 2.15.  Any help/suggestions about why the provided example fails would be appreciated.  I'm intending to use this code as a basis to program flash in the field via boot code that resides in on-chip flash. if (memcmp(s_nor_program_buffer, s_nor_read_buffer, sizeof(s_nor_program_buffer))) { PRINTF("Erase data - read out data value incorrect !\r\n "); return -1; } Re: MIMXRT1170 EVK flexspi issues I resolved my issue.  I had created my own pin_mux.c and had an error in it.  The example application and my test code now work erasing/writing/reading flash.  Thanks for your attention to my issue. Re: MIMXRT1170 EVK flexspi issues Hi @GLantzTCore ,    Thanks for your updated information, please also check the boot mode, it should be in the serial download mode, SW1:1-OFF,2-OFF,3-ON,4-OFF.     Now, follow me to do more testing, in fact, my side works OK:   1. Try the flexspi_nor_debug Whether this method works OK on your side? At least, this works on my side, no need to modify the reset type 2. if point 1 is working, you also can in the debug project, prepreocessor add: XIP_EXTERNAL_FLASH=1 try it again, this 2 method works on my MIMXRT1170-EVK rev C4 board. Wish it helps you! Best Regards, Kerry Re: MIMXRT1170 EVK flexspi issues Reset of System (default) is what my settings are.  It does not run successfully. Re: MIMXRT1170 EVK flexspi issues Hi @GLantzTCore ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.   Please follow me to resolve it. 1.select the project option 2. Choose the CMSIS DAP, setup, reset type to system(default) 3. this is the test result: You can see, the test result passed. Please try it on your side. If you still have question about it, please kindly let me know. If your question is solved, please help me to mark the correct answer, just to close this case. Any new issues, welcome to create the new question post. Best Regards, kerry

Why the CPU supported list is not a full list on the MCU Xpresso IDE Hello Team, We are planning to use LPC55S6x series microcontroller for one of our application. What I noticed was, this microcontroller is not listed on MCU Xpresso IDE (Latest version: MCUXpressoIDE_11.9.1_2170). Under an existing project properties, under Preinstalled CPU section, I am not seeing LPC55S6x microcontroller support. Can someone please let me know, if I am missing anything?  Regards, San Re: Why the CPU supported list is not a full list on the MCU Xpresso IDE Hello @Alice_Yang, Thanks for the support. Regards, San Re: Why the CPU supported list is not a full list on the MCU Xpresso IDE Hello @sushmasan  Develop LPC55xx series product, please install SDK into MCUXpresso IDE first. About detail please refer to 4.2 SDK part support of . BR Alice

Accessing internet from device connected to AP Note: This post is the continuation of the previous post.  I have been trying to intergrate NXP'S IW612 based wifi module with iMX8MPEVK.  I have followed this document for the setup. The problem is that I don't get Internet access in the client devices connected to the Access Point. The client devices seem to request for services from the Internet but the device responds unreachable. I have attached a snippet of output from tcpdump below: 01:53:41.901331 IP 172.24.100.5.41720 > nrt12s47-in-f10.1e100.net.https: Flags [S], seq 332091786, win 65535, options [mss 1460,sackOK,TS val 2069380644 ecr 0,nop,wscale 9], length 0 01:53:41.934260 IP 172.24.100.5.43714 > server-18-172-31-104.nrt20.r.cloudfront.net.https: Flags [S], seq 3938392598, win 65535, options [mss 1460,sackOK,TS val 1154171877 ecr 0,nop,wscale 9], length 0 01:53:41.963676 IP 172.24.100.1 > 172.24.100.5: ICMP host server-18-172-31-104.nrt20.r.cloudfront.net unreachable, length 68 Also, I noticed the document is based on 88w8987 WiFi modules. But I have an iw612 based WiFi module. Could this be the reason for difference in the results? After doing some digging in the web, I found following article, from Toradex  where it is said:  Toradex's provided Kernel configurations are insufficient for configuring NAT, thus it is important to add and enable the required kernel configs. For this, you can use the menuconfig Is it necessary to do same with the wifi module I have? Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Thanks for your reply. I suspect there are two reasons: 1. It is not necessary to set default gateway. I checked my ASUS router, there is also no gateway in the configurations which working as an AP. Please see below: 2. The configurations in  /etc/udhcpd.conf  opt router 192.168.2.1 # uap0 gw IP It has influence on Internet access. Best regards, Christine. Re: Accessing internet from device connected to AP I checked by adding default gw entries and the internet access is gone. After removing the entry, internet connection is back again. Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Thanks for your reply. I tried without default Gateway, it works, I didn't try with default Gate way. After you tried with internet available DNS and default Gateway, doesn't it work? Best regards, Christine. Re: Accessing internet from device connected to AP I now understand the issue of DNS. But why have we not set the default gateway now? I think we need default gateway because the packets destined for external network need to have somewhere to go (which was default gateway). But removing the default gateway seems to be correct method. Why is it so? Re: Accessing internet from device connected to AP Hi， @bgaurav1718  Thanks for your reply. The problem is the DNS configurations. The previous DNS configurations is internet unavailable. When we config the DNS to 8.8.8.8(Google's default DNS), we can visit internet. Best regards, Christine. Re: Accessing internet from device connected to AP This solution works in my side as well. Thank you very much @Christine_Li Can you please explain what the issue was previously and why the changes we make work? This way, I can have a better understanding of the issue and solve it on my own in case it arises again. Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Have you tried on your side? Does my suggestion work on your side? Please let me know whether have any other concerns on this thread I can help you. Best regards, Christine. Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Thanks for your feedback. Please try to change this line in  /etc/udhcpd.conf opt dns 192.168.0.1 #router IP  to below one: opt dns 8.8.8.8 #external dns server And also, do not set default gateway when you configure uap0 IP address: I mean, if you use: root@imx8mnevk:~# ifconfig uap0 192.168.2.2 netmask 255.255.255.0 up root@imx8mnevk:~# route add default gw 192.168.2.1 Please change it to: root@imx8mnevk:~# ifconfig uap0 192.168.2.2 netmask 255.255.255.0 up I have tried on my local side, and now I can visit Internet on my PC which connect to NXP-uap0. Best regards, Christine. Re: Accessing internet from device connected to AP I am actually using the Evaluation Kit provided by UBlox. It is called EVK-MAYA-W2 based on MAYA-W276 which is again based on IW612 chipset. Re: Accessing internet from device connected to AP I am sure I executed the settings for NAT. I might have forgotten to add the details in the shared document, but I am sure I did. Re: Accessing internet from device connected to AP Hi, @bgaurav1718  I think I have reproduced your issue on my local side with Linux kernel 6.1.22 and Wi-Fi driver is the default one in this kernel. Please see below: Right now I suspect it might be related to Linux kernel version. I will try to debug and resolve it, once have any updates, I will let you know. Best regards, Christine. Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Did you execute: Step 2 Configurations For NAT between uap0 & eth0 # iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE # iptables -A FORWARD -m conntrack --ctstate RELATED,ESTABLISHED -j ACCEPT # iptables -A FORWARD -i uap0 -o eth0 -j ACCEPT # iptables-save > /etc/iptables/iptables.rules Step 3 Enabling iptables and Restart board # systemctl --system daemon-reload # systemctl enable iptables # reboot If no, can you please execute to have a try? Best regards, Christine. Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Please let me know your IW612 Wi-Fi driver and FW version, so that I can do a same test with you. I have I.MX8MP-EVK and IW612 module(Murata 2EL M.2 module). Best regards, Christine. Re: Accessing internet from device connected to AP @Christine_Li  I made sure that the eth interface has access to the internet. It is able to ping a remote IP (8.8.8.8) without any issues.  I have attached a document to show the settings I have used to configure the AP mode.  Re: Accessing internet from device connected to AP Hi, @bgaurav1718  Thanks for creating case to us. For 88W8987 it is similar with IW612 when Wi-Fi  works. Has your I.MX8MP board connected to Ethernet (can visit internet)and assigned correct IP address? Firstly please make sure your I.MX8MP's ethernet can visit internet, then refer to the given guide to route the internet from Ethernet to IW612's Wi-Fi(as an AP). You can also provide me your detailed setup steps and results in a doc or take video/screenshot for better understanding. Best regards, Christine.

无法为S32K388生成UART配置 硬件：S32K388 问题描述：我在生成 UART 配置时遇到问题。它抱怨说 LPUART4 和 LPUART12 使用相同的 DMA 方法源通道，并要求我只配置 LPUART4 或 LPUART12 中的一个。但对于我的应用程序，我需要配置两个通道。 我确保在配置 Rm 和 Mcl 时使用不同的 DMA 通道。 这是 Tresos 生成器的错误吗？如果没有，请帮我找出这里的问题。谢谢。

从连接到 AP 的设备访问互联网 注：这篇文章是上一篇文章的续篇。 我一直在尝试将基于 NXP IW612 的 wifi 模块与 iMX8MPEVK 集成。 我已按照此文档进行设置。 问题是我无法在连接到接入点的客户端设备中访问互联网。客户端设备似乎正在向互联网请求服务，但设备却返回“无法访问”。我附上了一段 tcpdump 的输出： 01：53：41.901331 IP 172.24.100.5.41720 > nrt12s47-in-f10.1e100.net.https：标志[S]，序列号332091786，win 65535，选项[mss 1460，sackOK，TS val 2069380644 ecr 0，nop，wscale 9]，长度0 01：53：41.934260 IP 172.24.100.5.43714 > 服务器-18-172-31-104.nrt20.r.cloudfront.net.https：标志 [S]，序列号 3938392598，win 65535，选项 [mss 1460,sackOK,TS val 1154171877 ecr 0,nop,wscale 9]，长度 0 01：53：41.963676 IP 172.24.100.1 > 172.24.100.5：ICMP 主机 server-18-172-31-104.nrt20.r.cloudfront.net 无法访问，长度 68 另外，我注意到该文档基于 88w8987 WiFi 模块。但我有一个基于iw612的WiFi模块。这可能是结果不同的原因吗？ 在网上搜索一番后，我发现了Toradex 的以下文章，其中提到： Toradex 提供的内核配置不足以配置 NAT，因此添加并启用所需的内核配置非常重要。为此，您可以使用 menuconfig 我现有的 wifi 模块也需要做同样的操作吗？ 回复：从连接到 AP 的设备访问互联网 我通过添加默认 gw 条目进行了检查，发现互联网访问已经中断。删除该条目后，互联网连接又恢复了。 回复：从连接到 AP 的设备访问互联网 我现在了解了 DNS 的问题。但为什么我们现在还没有设置默认网关呢？我认为我们需要默认网关，因为发往外部网络的数据包需要有地方去（即默认网关）。但删除默认网关似乎是正确的方法。为什么会这样？ 回复：从连接到 AP 的设备访问互联网 这个解决方案在我这边也有效。非常感谢@Christine_Li 您能否解释一下之前的问题是什么以及我们所做的更改为什么有效？这样，我可以更好地了解问题，并在问题再次出现时自行解决。 回复：从连接到 AP 的设备访问互联网 我确定我已经执行了 NAT 的设置。我可能忘记在共享文档中添加详细信息，但我确信我已经添加了。

MIMXRT1170 EVK flexspiの問題 IARツールセットでMIMXRT1170 EVKを使用しています。SDKに付属のdriver_examplesからflexspi_nor_polling_transferプロジェクトを実行しています。私はデバッグプロジェクトターゲットを構築していますが、これは私が理解しているようにflexspiフラッシュを使用すべきではありません。プログラムは、プログラム バッファーと読み取りバッファー間のメモリ比較で失敗します。私はコードを一切変更しておらず、プロジェクトはSDK 2.15で提供されているものです。提供された例が失敗する理由についての助け/提案は高く評価されます。このコードを基礎として使用して、オンチップフラッシュに存在するブートコードを介してフィールドでフラッシュをプログラムするつもりです。 if (memcmp(s_nor_program_buffer, s_nor_read_buffer, sizeof(s_nor_program_buffer))) { PRINTF("データの消去 - データ値の読み出しが正しくありません!\r\n "); -1 を返します。 } Re:MIMXRT1170 EVKフレックススピの問題 問題を解決しました。私は自分でpin_mux.cを作りましたそして、それに誤りがありました。サンプルアプリケーションと私のテストコードは、フラッシュの消去/書き込み/読み取りで動作するようになりました。私の問題にご清聴いただきありがとうございます。 Re:MIMXRT1170 EVKフレックススピの問題 システムのリセット(デフォルト)は私の設定です。正常に実行されません。

关于S32R系列雷达处理芯片的问题 请问S32R294或者S32R41芯片除了毫米波雷达外，还可以用于其他频段的线性调频连续波雷达应用吗？

Regarding the issue of S32R series radar processing chips May I ask if the S32R294 or S32R41 chips can be used for linear frequency modulation continuous wave radar applications in other bands besides millimeter wave radar？ Re: Regarding the issue of S32R series radar processing chips Hello,   The processors are not constrained like this As long as the radar front-end device has compatible MIPI-CSI2/DPHY interface then it can be connected to S32R Best regards, Peter

Could not generate UART configuration for S32K388 Hardware: S32K388 Issue Description: I am facing issue during generation of UART config. It's complaining saying LPUART4 and LPUART12 are using same source channel of DMA Method and asking me to configure only one of LPUART4 or LPUART12. But for my application, I need both of the channels to be configured. I made sure that I am using different DMA channels when I configured Rm and Mcl. Is this error with Tresos generator? If not, please help me with identifying the problem here. Thanks. Re: Could not generate UART configuration for S32K388 Hello @Gnanesh, This is a HW limitation. There are many peripherals but not many DMAMUX slots, therefore, some of the DMAMUX sources are routed to more peripharals. Like source 43: That means that if either of the LPUARTs received data, it would trigger both DMA channels and both LPUART DATA registers would be read by the DMA at the same time. Regards, Daniel

ブートローダーが存在する場合、DeepSleepからウェイクアップLPC1768 私はLPC1768を備えたCusotmボードを持っていますが、ディープスリープモードを使用する必要があります。デフォルトではすべて問題なく動作しますが、ブートローダーをインストールし、ディープスリープを使用する必要があるメインプログラムにオフセットがある場合、MCUをウェイクアップするとIRQがクリアされ、電流が増加するとウェイクアップするとどこかで動かなくなったままになります...possible が間違ったアドレスに入力されます。デバッグツールは深い眠りでは機能しないため、デバッグ方法がわかりません。 何かアイデアはありますか?

S32K311 EMIOS GPT Hi, I am trying to configure timer for 500ms usin EMIOS GPT. How to calculate the compareValue ? Is there any documents available? Re: S32K311 EMIOS GPT Hi @_Leo_ , Thank you for your support. Small doubt, how to derive this 1s -> 120MHz (120,000,000 ticks)? Re: S32K311 EMIOS GPT Hi, Thank you so much for your interest in our products and for using our community. There is the S32K3 RTD Training eMIOS presentation (attached). On the other hand, for GPT frequency of 2Hz (500ms) with eMIOS clock frequency of 120MHz you need 60,000,000 ticks: 1s -> 120MHz (120,000,000 ticks) 2Hz = (1/2)s ->120,000,000 *(1/2) = 60,000,000 ticks But max ticks are 65,534 (16 bits). Using Global Prescaler = 256 (in Emios_Mcl_Ip driver) and Gpt Emios Prescaler = 15 (in Emios_Gpt driver): 1s -> 120MHz/256/15 (31,250 ticks) 2Hz = (1/2)s ->31,250 *(1/2) = 15,625 ticks Please find attached project. This example implement a General Purpose Timer (GPT) with eMIOS (CH_0), such timer generates an interrupt when it reaches to its defined compare value and its respective notification function toggles the on-board blue LED (PTB8). S32DS 3.6 + RTD 5.0.0 (S32K31XEVB-Q100) Hope it helps you. Have a nice day!    

LPC1768 wake up from DeepSleep when bootloader is present I have a cusotm board with LPC1768 and I need to use deep sleep mode. Everything works OK as default but when I install a bootloader and the main program where I need to use deep sleep has an offset, when I wake up the MCU it clear ctach teh IRQ and wake up as current increased it remains stucked somewhere... possible goes on a wrong address. I do nto know how to debug as debuger does not work in deep sleep. Any idea? Re: LPC1768 wake up from DeepSleep when bootloader is present Yes... aplicatiopn was aorking independently. Anyway I found the problem and solution. Only need it to add Offset address when reainitialize the clock  SCB->VTOR = ADRE_OFFSET & 0x3FFFFF80; Thank you Re: LPC1768 wake up from DeepSleep when bootloader is present Hello @laurianussss, Could you execute the Bootloader application and the low power mode independently? this with the propose of corroborate that both work as expected. Also, I highly recommend see the 4.8.2 called " Deep Sleep mode" in order to obtain more information about low power mode. BR Habib 

S32G399A STM issue Hi everyone, I'm facing an issue with the STM1 timer. I've configured two counters: Counter_1 running at 1ms for STM0 (CH0) and Counter_2 running at 1us for STM1 (CH0). The STM0 counter works fine, but STM1 is not updating as expected. Instead of updating every 1us, it updates every 15-25s.  Configuration Details: Clock for both STM0 and STM1: 133.33333 MHz Prescaler (PSC) for both: 1 Compare values: 0x208D5 for 1ms (STM0) and 0x85 for 1us (STM1) Interrupt priority: 4 for STM0, 5 for STM1 Re: S32G399A STM issue hi,asj Thank you for your reply. According to the timer's PSC and clock frequency, it is theoretically possible to achieve 1us, if you doubt the reason for performance, you can try to set STM1 larger time, such as 100us or 2ms. BR Joey Re: S32G399A STM issue Hi Joey, Sorry for the late reply. Yes, I'm doing that. My doubt now, is whether a time period of 1us is feasible. This means 1000000 interrupts per second. So, it might lead to a runtime problem. Could you shed some light on this? BR asj Re: S32G399A STM issue hi,asj Sorry for replying so late. Did you try setting Freeze mode to FALSE? Additionally, after the channel interrupt has been handled, clear the channel interrupt flag (CIF). BR Joey Re: S32G399A STM issue Hi Joey, Yes, I am. The CNT value for STM0 (1ms) continuously updates every 1ms, upon reaching CMP value (IRQ assertion is happening properly). But for STM1 (1us), the CMP value only updates after CNT value falls over from FFFFFFFF to 00000000 and then matches the CMP value (IRQ assertion is improper). So, it takes 10-15s for my counter to update its value. Thanks, asj Re: S32G399A STM issue hi,asj Are you using STM0 and STM1 in debug mode, and if so, check to see if the value of CNT reaches the comparison value to enter the interrupt. Also, try setting Freeze mode to FALSE. BR Joey Re: S32G399A STM issue Okay, I can do that, but the thing is if I'm using them both for 1ms, they work. So that's why I had the doubt. Anyways, I'll do it and let you know Do let me know if you find anything from the code Re: S32G399A STM issue hi,asj Thank you for your information. I will try to look at the code for you and find the problem. In addition, The second problem is that I suggest that you do not apply STM0 and only use STM1 to check whether STM1 itself is configured incorrectly. If STM1 works well alone, you should focus on finding configuration problems between the two STMS when they are used. BR Joey Re: S32G399A STM issue This is my STM configuration: static const Stm_Prv_InstanceConfig_tst Stm_Cfg_PbInstanceConfInirba_Stm_Config_acst[STM_CFG_PB_NUMBER_OF_STM_INSTANCES] = { /* STM peripheral instance*/ /* Freeze mode */ /* Prescaler value(range 1 to 256) */ /* Instance configuration for instance STM0*/ { STM_CFG_STM0_INSTANCE, // STM peripheral instance TRUE, // Freeze mode 1, // Prescale value(range 1 to 256) }, /* Instance configuration for instance STM1*/ { STM_CFG_STM1_INSTANCE, // STM peripheral instance TRUE, // Freeze mode 1, // Prescale value(range 1 to 256) }, }; static const Stm_GptChannelConfig_tst Stm_Cfg_GptPbChannelConfigInirba_Stm_Config_acst[STM_CFG_GPT_NUMBER_OF_LOGIC_STM_CHANNELS] = { /* Instance of the STM STM hardware channel */ /* peripheral, STM_REG_STMN_CHm */ /* m = 0, 1, 2, 3 { STM_CFG_STM0_INSTANCE, STM_CFG_STMN_CH0, }, { STM_CFG_STM1_INSTANCE, STM_CFG_STMN_CH0, }, }; This is how I'm setting the compare value: Stm_StartTimer((uint8)  RBA_STM_CFG_STM0_INSTANCE,                           (uint8)  RBA_STM_CFG_STMN_CH0,                           (uint32) 0x208D5);                   // 1ms     //Rework OS timer clock value         // Init OS system timer - STM1 and CH0 Stm_StartTimer((uint8)  RBA_STM_CFG_STM1_INSTANCE,                          (uint8)  RBA_STM_CFG_STMN_CH0,                           (uint32) 0x85);                   // 1us Stm_StartTimer function does the following: /* Read the current counter value */      Stm_Prv_CounterStartValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]= STM_PRV_REG_CNT((HwTimerInstance_u8));      /* Load the compare value,which is the sum of current counter value and timeout value */      STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8)) = (uint32)(TimeOutValue_u32+Stm_Prv_CounterStartValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]);      /* Store the timeout value */      Stm_Prv_TimeoutValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]=TimeOutValue_u32;      /* Enable the channel */      STM_PRV_REG_STMCCR_CEN_TIMER_CH_ENABLED((HwTimerInstance_u8), (HwTimerChannel_u8)); The logic for updation of CMP value: /* store current compare value */     Stm_cmp_value_u32=STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8));     /* Set the compare value */     STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8))=(uint32)(Stm_cmp_value_u32 + Stm_Prv_TimeoutValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]); } And as for the second question, I'm trying to use both STM0 and STM1 for different time intervals, to implement counters for my usecase. Re: S32G399A STM issue Hi，asj Thank you for contacting us. Could you share more information about your code? For example, how do you configure your STM? In addition, is it normal only to use the STM1? BR Joey Re: S32G399A STM issue These are my ISRs where I set the CMP value by adding a "timeout value" (0x85 for 1us), and clear the interrupt flag, these are done inside "Handler": ISR(IsrSTM0) {     Handler((uint8) STM_CFG_STM0_INSTANCE, (uint8) STM_CFG_STMN_CH0);     Os_IncrementCounter_Counter_1();        } ISR(IsrSTM1) {     Handler((uint8) STM_CFG_STM1_INSTANCE, (uint8) STM_CFG_STMN_CH0);     Os_IncrementCounter_Counter_2(); }

S32K344) Update Hall period Regarding the sample project "MCSPTE1AK344_BLDC_6Step_hall_ll," an interrupt occurs every seven rising edges of the Hall sensor, triggering the function "eMIOS1IcuNotify()". Could you please let me know how to change it to trigger an interrupt for every single edge? Where is it set to every 7 times? Re: S32K344) Update Hall period Hi Tomato1,  within eMios driver configuration there is function where the last argument is interval for calling notification:  /*********************************************************************************************** * eMios Driver ***********************************************************************************************/ ... Emios_Icu_Ip_StartTimestamp(1U, 1U, &IcuTimeStampBuffer[0], 7U, 7U); ... More details about S32K344 motor control application can be found in knowledge base article   https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Motor-control-SW-examples/ta-p/1804577 Best regards,  Tomas Fedor. Re: S32K344) Update Hall period Hello, I have asked motor control expert responsible for S32K3 to comment here. Best regards, Peter

S32K344)更新ホール期間 サンプルプロジェクト「MCSPTE1AK344_BLDC_6Step_hall_ll」については、 ホールセンサーの7つの立ち上がりエッジごとに割り込みが発生し、eMIOS1IcuNotify()関数がトリガーされます。 すべてのエッジで割り込みをトリガーするように変更する方法を教えてください。 7回ごとにどこに設定されていますか?

S32G399A STMの問題 こんにちは、皆さん STM1 タイマーで問題が発生しています。STM0 (CH0) の 1ms で動作する Counter_1 と STM1 (CH0) の 1us で動作する Counter_2 の 2 つのカウンターを構成しました。STM0 カウンタは正常に動作しますが、STM1 が期待どおりに更新されません。1usごとに更新するのではなく、15〜25秒ごとに更新されます。 構成の詳細: STM0 と STM1 の両方のクロック: 133.33333 MHz 両方のプリスケーラー(PSC):1 値の比較:1msの0x208D5(STM0)と1usの0x85(STM1) 割り込み優先度:STM0の場合は4、STM1の場合は5 Re:S32G399A STMの問題 さて、私はそれを行うことができますが、問題は、両方を1ms使用している場合、それらは機能するということです。だから、私は疑問を持っていました。とにかく、やってみて、お知らせします コードから何か見つけた場合はお知らせください

S32K344)更新霍尔周期 关于示例项目“MCSPTE1AK344_BLDC_6Step_hall_ll”， 霍尔传感器每七个上升沿就会发生一次中断，触发函数“eMIOS1IcuNotify()”。 您能否告诉我如何改变它以触发每个边缘的中断？ 在哪里设置每7次？

i.mx95 lvds HI NXP Teams I am evaluating the I.MX95 for multi-camera and multi-display applications. Since two sets of MIPI-CSI are required simultaneously, DSI cannot be used for the display. I would like to know if the two 1x4 LVDS ports can output different display information separately? What is the supported bitrate and resolution? poyuan Graphics & Display Re: i.mx95 lvds Hello, Yes, the i.MX95 2x 4-lane LVDS display interface capable of 1080p60 resolution. Best regards/Saludos, Aldo. Re: i.mx95 lvds I understand the current status of the I.MX95. Can the two BOE WXGA LVDS panels on the EVK output different information? If I create my own adapter, can it output 1080P, 30FPS information? Re: i.mx95 lvds Hello, Please note that i.MX95 is still in pre-production stage so all information and specifications herein are subject to change without notice. I.MX95 is capable of a 2x 4-lane or 1x 8-lane LVDS display interface capable of 1080p60 resolution. On the EVK there is 2 combinations available either two single-channel LVDS-to-HDMI converter or two BOE WXGA LVDS panel. Best regards/Saludos, Aldo.

LS1046A custom board: BL2: Failed to load image I'm trying to bring up custom LS1046A board, but it fails due to memory initialization failure. TFA version: 1.5 NXP LLDP L6.1.55_2.2.0 Board stuck at BL2. Here is the verbose output: ``` INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: total size 8 GB INFO: Need to wait up to 2680 ms INFO: Reading debug[9] as 0x10101010 INFO: Reading debug[10] as 0x10101010 INFO: Reading debug[11] as 0x10101010 INFO: Reading debug[12] as 0x10101010 INFO: cpo_min 0x10 INFO: cpo_max 0x10 INFO: debug[28] 0x70006f WARNING: Warning: A009942 requires setting cpo_sample to 0x37 INFO: *0x1080000 = 0x1ff INFO: *0x1080008 = 0x200023f INFO: *0x1080010 = 0x240027f INFO: *0x1080018 = 0x28002bf INFO: *0x1080080 = 0x80010512 INFO: *0x1080084 = 0x202 INFO: *0x1080088 = 0x202 INFO: *0x108008c = 0x202 INFO: *0x1080100 = 0x21d1100 INFO: *0x1080104 = 0xff770010 INFO: *0x1080108 = 0xf8fc1265 INFO: *0x108010c = 0x5951a0 INFO: *0x1080110 = 0xc5208000 INFO: *0x1080114 = 0x401060 INFO: *0x1080118 = 0x1010631 INFO: *0x108011c = 0x100000 INFO: *0x1080120 = 0x600081f INFO: *0x1080124 = 0x1ffe07ff INFO: *0x1080130 = 0x2800000 INFO: *0x1080160 = 0x22d502 INFO: *0x1080164 = 0x6401400 INFO: *0x108016c = 0x25540000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc6750605 INFO: *0x1080190 = 0x5060607 INFO: *0x1080194 = 0x7080804 INFO: *0x1080220 = 0x701 INFO: *0x1080224 = 0x8800000 INFO: *0x1080250 = 0x5447a00 INFO: *0x1080270 = 0xffff INFO: *0x1080280 = 0xffffffff INFO: *0x1080284 = 0xffffff7d INFO: *0x1080288 = 0xffffffff INFO: *0x108028c = 0xffffff7d INFO: *0x1080290 = 0x1 INFO: *0x10802a0 = 0x1 INFO: *0x1080400 = 0x1692672c INFO: *0x1080404 = 0x8c99d5a0 INFO: *0x1080408 = 0xe50eb14 INFO: *0x108040c = 0xc8000000 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80040000 INFO: *0x1080b2c = 0x80 INFO: *0x1080bf8 = 0x20502 INFO: *0x1080bfc = 0x100 INFO: *0x1080e40 = 0x80 INFO: *0x1080f04 = 0x3002 INFO: *0x1080f08 = 0xd INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x10101010 INFO: *0x1080f28 = 0x10101010 INFO: *0x1080f2c = 0x10101010 INFO: *0x1080f30 = 0x10101010 INFO: *0x1080f34 = 0x10103000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x94000000 INFO: *0x1080f50 = 0x10001000 INFO: *0x1080f54 = 0xf000f00 INFO: *0x1080f58 = 0xd000d00 INFO: *0x1080f5c = 0xc000c00 INFO: *0x1080f60 = 0x8000000 INFO: *0x1080f64 = 0x9000 INFO: *0x1080f68 = 0x20 INFO: *0x1080f70 = 0INFO: RCW BOOT SRC is IFC NOR VERBOSE: Generic delay timer configured with mult=1 and div=25 INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: total size 8 GB INFO: Need to wait up to 2680 ms INFO: Reading debug[9] as 0x10101010 INFO: Reading debug[10] as 0x10101010 INFO: Reading debug[11] as 0x10101010 INFO: Reading debug[12] as 0x10101010 INFO: cpo_min 0x10 INFO: cpo_max 0x10 INFO: debug[28] 0x70006f WARNING: Warning: A009942 requires setting cpo_sample to 0x37 INFO: *0x1080000 = 0x1ff INFO: *0x1080008 = 0x200023f INFO: *0x1080010 = 0x240027f INFO: *0x1080018 = 0x28002bf INFO: *0x1080080 = 0x80010512 INFO: *0x1080084 = 0x202 INFO: *0x1080088 = 0x202 INFO: *0x108008c = 0x202 INFO: *0x1080100 = 0x21d1100 INFO: *0x1080104 = 0xff770010 INFO: *0x1080108 = 0xf8fc1265 INFO: *0x108010c = 0x5951a0 INFO: *0x1080110 = 0xc5208000 INFO: *0x1080114 = 0x401060 INFO: *0x1080118 = 0x1010631 INFO: *0x108011c = 0x100000 INFO: *0x1080120 = 0x600081f INFO: *0x1080124 = 0x1ffe07ff INFO: *0x1080130 = 0x2800000 INFO: *0x1080160 = 0x22d502 INFO: *0x1080164 = 0x6401400 INFO: *0x108016c = 0x25540000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc6750605 INFO: *0x1080190 = 0x5060607 INFO: *0x1080194 = 0x7080804 INFO: *0x1080220 = 0x701 INFO: *0x1080224 = 0x8800000 INFO: *0x1080250 = 0x5447a00 INFO: *0x1080270 = 0xffff INFO: *0x1080280 = 0xffffffff INFO: *0x1080284 = 0xffffff7d INFO: *0x1080288 = 0xffffffff INFO: *0x108028c = 0xffffff7d INFO: *0x1080290 = 0x1 INFO: *0x10802a0 = 0x1 INFO: *0x1080400 = 0x1692672c INFO: *0x1080404 = 0x8c99d5a0 INFO: *0x1080408 = 0xe50eb14 INFO: *0x108040c = 0xc8000000 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80040000 INFO: *0x1080b2c = 0x80 INFO: *0x1080bf8 = 0x20502 INFO: *0x1080bfc = 0x100 INFO: *0x1080e40 = 0x80 INFO: *0x1080f04 = 0x3002 INFO: *0x1080f08 = 0xd INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x10101010 INFO: *0x1080f28 = 0x10101010 INFO: *0x1080f2c = 0x10101010 INFO: *0x1080f30 = 0x10101010 INFO: *0x1080f34 = 0x10103000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x94000000 INFO: *0x1080f50 = 0x10001000 INFO: *0x1080f54 = 0xf000f00 INFO: *0x1080f58 = 0xd000d00 INFO: *0x1080f5c = 0xc000c00 INFO: *0x1080f60 = 0x8000000 INFO: *0x1080f64 = 0x9000 INFO: *0x1080f68 = 0x20 INFO: *0x1080f70 = 0x70006f INFO: *0x1080f94 = 0x80000000 INFO: *0x1080fb0 = 0x3 INFO: *0x1080fb4 = 0x1f1f1f1f INFO: *0x1080fb8 = 0x1f1f1f1f INFO: *0x1080fbc = 0x1f1f1f1f INFO: *0x1080fc0 = 0x1f1f1f1f INFO: *0x1080fc4 = 0x1f1f1f1f INFO: *0x1080fc8 = 0x1f1f1f1f INFO: *0x1080fcc = 0x1f1f1f1f INFO: *0x1080fd0 = 0x1f1f1f1f INFO: *0x1080fd4 = 0x1f1f1f1f INFO: *0x1080fd8 = 0x1f1f1f1f INFO: *0x1080fdc = 0x1f1f1f1f INFO: *0x1080fe0 = 0x1f1f1f1f INFO: *0x1080fe4 = 0x1f1f1f1f INFO: *0x1080fe8 = 0x1f1f1f1f INFO: *0x1080fec = 0x1f1f1f1f INFO: *0x1080ff0 = 0x1f1f1f1f INFO: *0x1080ff4 = 0x1f1f1f1f INFO: *0x1080ff8 = 0x1f1f1f1f INFO: *0x1080ffc = 0x1f003f38 NOTICE: 8 GB DDR4, 64-bit, CL=15, ECC off INFO: Time used by DDR driver 1371 ms VERBOSE: Memory seen by this BL image: 0x10000000 - 0x10013000 VERBOSE: Code region: 0x10000000 - 0x10008000 VERBOSE: Read-only data region: 0x10008000 - 0x1000b000 VERBOSE: DRAM Region 0: 0x80000000 - 0xfbdfffff VERBOSE: Secure DRAM Region 0: 0xfbe00000 - 0xffffffff mmap: VA:0x1000000 PA:0x1000000 size:0xf000000 attr:0x8 granularity:0x40000000 VA:0x10000000 PA:0x10000000 size:0x8000 attr:0x2 granularity:0x40000000 VA:0x10008000 PA:0x10008000 size:0x3000 attr:0x22 granularity:0x40000000 VA:0x10000000 PA:0x10000000 size:0x13000 attr:0xa granularity:0x40000000 VA:0x60000000 PA:0x60000000 size:0x8000000 attr:0xa granularity:0x40000000 VA:0x80000000 PA:0x80000000 size:0x7be00000 attr:0x1a granularity:0x40000000 VA:0xfbe00000 PA:0xfbe00000 size:0x4200000 attr:0xa granularity:0x40000000 VERBOSE: Translation tables state: VERBOSE: Xlat regime: EL3 VERBOSE: Max allowed PA: 0xffffffffff VERBOSE: Max allowed VA: 0xffffffffff VERBOSE: Max mapped PA: 0xffffffff VERBOSE: Max mapped VA: 0xffffffff VERBOSE: Initial lookup level: 0 VERBOSE: Entries @initial lookup level: 2 ... NOTICE: BL2: v1.5(debug): NOTICE: BL2: Built : 07:13:31, Jun 6 2024 INFO: Configuring TrustZone Controller VERBOSE: TrustZone : Configuring region 0 (TZC Interface Base=0x1500000 sec_attr=0x0, ns_devs=0x0) INFO: Value of region base = ffe00000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 1)... VERBOSE: TrustZone : ... base = fbe00000, top = ffdfffff, VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0x0) INFO: Value of region base = 1ffe00000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 2)... VERBOSE: TrustZone : ... base = ffe00000, top = ffffffff, VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff) INFO: Value of region base = fbe00000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 3)... VERBOSE: TrustZone : ... base = 80000000, top = fbdfffff, VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff) INFO: Value of region base = a80000000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 4)... VERBOSE: TrustZone : ... base = 880000000, top = 9ffffffff, VERBOSE: TrustZone : ... sec_attr = 0x0, ns_devs = 0xffffffff) INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 WARNING: Firmware Image Package header check failed. VERBOSE: Trying FUSE IO WARNING: Failed to obtain reference to image id=3 (-2) ERROR: BL2: Failed to load image (-2) Authentication failure ``` On the QCVS tool 'Centering the clock'  test failed. I got the following log. ``` #################### Result for: wrlvl_searcher ###### Run 1 ###################################### Test result: [ ============================================================ Updated: WRLVL_CNTL = 0x86750605, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750607, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750609, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675060B, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675060D, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675060F, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750611, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750613, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750615, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750617, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750619, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675061B, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Validation cannot proceed due to other DDR hardware or software issues! Common hardware issues include: - DRAM reset is not implemented correctly - Voltages are not present - Signals not connected correctly - Differential signals connected in wrong polarity Common software issues include: - wrong DDR frequency selected - wrong DDR configuration selected - incorrect SPD data - DDR4 DQn_MAP configured values are incorrect < > {{Validation cannot proceed due to other DDR hardware or software issues!}} Err. capture registers: 0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080 0xE44, 0x00000100 0xE48, 0x00000000 0xE4C, 0x00000000 0xE50, 0x00000000 0xE54, 0x00000000 0xE58, 0x00010000 Dump: 0xF00, 0x00000000 0xF04, 0x00003002 0xF08, 0x0000000D 0xF0C, 0x14000C20 0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000 0xF20, 0x00000000 0xF24, 0x10101010 0xF28, 0x10101010 0xF2C, 0x10101010 0xF30, 0x10101010 0xF34, 0x10103000 0xF38, 0x00000000 0xF3C, 0x00000000 0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0x94000000 0xF50, 0x30003000 0xF54, 0x2F002F00 0xF58, 0x3D003D00 0xF5C, 0x3C003C00 0xF60, 0x36000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000 0xF70, 0x0070006F 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000 0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000 0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x00000000 0xFA0, 0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000 0xFB0, 0x00000003 0xFB4, 0x1F1F1F1F 0xFB8, 0x1F1F1F1F 0xFBC, 0x1F1F1F1F 0xFC0, 0x1F1F1F1F 0xFC4, 0x1F1F1F1F 0xFC8, 0x1F1F1F1F 0xFCC, 0x1F1F1F1F 0xFD0, 0x1F1F1F1F 0xFD4, 0x1F1F1F1F 0xFD8, 0x1F1F1F1F 0xFDC, 0x1F1F1F1F 0xFE0, 0x1F1F1F1F 0xFE4, 0x1F1F1F1F 0xFE8, 0x1F1F1F1F 0xFEC, 0x1F1F1F1F 0xFF0, 0x1F1F1F1F 0xFF4, 0x1F1F1F1F 0xFF8, 0x1F1F1F1F 0xFFC, 0x1F003F38 Data: 0x00000005 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ``` I tried to adjust Clock control and WL but it failed and threw same error after memory validation on QCVS tool. The following are the parameters for DDR. (TFA version is 1.5 as recommended by NXP for the boards with LS1046A) ``` const struct ddr_cfg_regs static_1600 = { .cs[0].bnds = 0x01FF, .cs[1].bnds = 0x0200023F, .cs[0].config = 0x80010512, .cs[1].config = 0x0202, .cs[2].bnds = 0x0240027F, .cs[3].bnds = 0x028002BF, .cs[2].config = 0x0202, .cs[3].config = 0x0202, .cs[0].config_2 = 0x00, .cs[1].config_2 = 0x00, .cs[2].config_2 = 0x00, .cs[3].config_2 = 0x00, .sdram_cfg[0] = 0x45200000, .sdram_cfg[1] = 0x00401070, .timing_cfg[0] = 0x80770010, .timing_cfg[1] = 0xB8BC02D5, .timing_cfg[2] = 0x005951A5, .timing_cfg[3] = 0x02111100, .timing_cfg[4] = 0x00220002, .timing_cfg[5] = 0x06401400, .timing_cfg[7] = 0x25540000, .timing_cfg[8] = 0x05447A00, .dq_map[0] = 0x1692672C, .dq_map[1] = 0x8C99D5A0, .dq_map[2] = 0x0E50EB14, .dq_map[3] = 0xC8000000, .sdram_mode[0] = 0x01010631, .sdram_mode[1] = 0x00100000, .sdram_mode[2] = 0x00, .sdram_mode[3] = 0x00, .sdram_mode[4] = 0x00, .sdram_mode[5] = 0x00, .sdram_mode[6] = 0x00, .sdram_mode[7] = 0x00, .sdram_mode[8] = 0x0701, .sdram_mode[9] = 0x08800000, .sdram_mode[10] = 0x00, .sdram_mode[11] = 0x00, .sdram_mode[12] = 0x00, .sdram_mode[13] = 0x00, .sdram_mode[14] = 0x00, .sdram_mode[15] = 0x00, .md_cntl = 0x00, .interval = 0x1FFE07FF, .data_init = 0xDEADBEEF, .clk_cntl = 0x02800000, .init_addr = 0x00, .ddr_sr_cntr = 0x0, .init_ext_addr = 0x00, .zq_cntl = 0x8A090905, .wrlvl_cntl[0] = 0x86750609, .wrlvl_cntl[1] = 0x09060603, .wrlvl_cntl[2] = 0x030D0D00, .cdr[0] = 0x800C0000, .cdr[1] = 0x81, }; ``` Re: LS1046A custom board: BL2: Failed to load image Have you found what was the cause of "ERROR: Found training error(s): 0x3000 ERROR: Error: Waiting for D_INIT timeout."? I'm facing the same issue. Re: LS1046A custom board: BL2: Failed to load image There is no SPD on my target board. I did as you said. I have configured DDR according to the data sheet but it is failing again. Here is my DDR registers configuration: const struct ddr_cfg_regs static_2100 = { .cs[0].bnds = 0x01FF, .cs[1].bnds = 0x0200023F, .cs[0].config = 0x80010512, .cs[1].config = 0x0202, .cs[0].config_2 = 0x00, .cs[1].config_2 = 0x00, .cs[2].bnds = 0x0240027F, .cs[3].bnds = 0x028002BF, .cs[2].config = 0x0202, .cs[3].config = 0x0202, .cs[2].config_2 = 0x00, .cs[3].config_2 = 0x00, .timing_cfg[0] = 0xFF770010, .timing_cfg[1] = 0xF8FC1265, .timing_cfg[2] = 0x005951A0, .timing_cfg[3] = 0x021D1100, .timing_cfg[4] = 0x0022D502, .timing_cfg[5] = 0x06401400, .timing_cfg[6] = 0x00000000, .timing_cfg[7] = 0x25540000, .timing_cfg[8] = 0x05447A00, .timing_cfg[9] = 0x00000000, .sdram_cfg[0] = 0x45208000, .sdram_cfg[1] = 0x00401060, .sdram_cfg[2] = 0x00, .dq_map[0] = 0x1692672C, .dq_map[1] = 0x8C99D588, .dq_map[2] = 0x0E50C594, .dq_map[3] = 0x48000000, .sdram_mode[0] = 0x01010631, .sdram_mode[1] = 0x00100000, .sdram_mode[2] = 0x00, .sdram_mode[3] = 0x00, .sdram_mode[4] = 0x00, .sdram_mode[5] = 0x00, .sdram_mode[6] = 0x00, .sdram_mode[7] = 0x00, .sdram_mode[8] = 0x0701, .sdram_mode[9] = 0x08800000, .sdram_mode[10] = 0x00, .sdram_mode[11] = 0x00, .sdram_mode[12] = 0x00, .sdram_mode[13] = 0x00, .sdram_mode[14] = 0x00, .sdram_mode[15] = 0x00, .md_cntl = 0x00, .interval = 0x1FFE07FF, .data_init = 0xDEADBEEF, .clk_cntl = 0x02400000, .init_addr = 0x00, .ddr_sr_cntr = 0x0, .init_ext_addr = 0x00, .zq_cntl = 0x8A090705, .wrlvl_cntl[0] = 0x86750605, .wrlvl_cntl[1] = 0x05060607, .wrlvl_cntl[2] = 0x07080804, .sdram_rcw[0] = 0x00, .sdram_rcw[1] = 0x00, .sdram_rcw[2] = 0x00, .sdram_rcw[3] = 0x00, .sdram_rcw[4] = 0x00, .sdram_rcw[5] = 0x00, .cdr[0] = 0x80080000, .cdr[1] = 0x80, .err_disable = 0x00, .err_int_en = 0x00, }; When DRAM data initialization ( D_INIT bit is set to 1)  i get the following output: INFO: RCW BOOT SRC is IFC NOR INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: total size 8 GB INFO: Need to wait up to 2680 ms ERROR: Found training error(s): 0x3000 ERROR: Error: Waiting for D_INIT timeout. ERROR: Writing DDR register(s) failed ERROR: Programing DDRC error ERROR: DDR init failed. NOTICE: Incorrect DRAM0 size is defined in platfor_def.h ERROR: mmap_add_region_check() failed. error -22 ASSERT: lib/xlat_tables_v2/xlat_tables_internal.c:753 When DRAM data initialization ( D_INIT bit is set to 0): INFO: RCW BOOT SRC is IFC NOR INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: Reading debug[9] as 0x10101010 INFO: Reading debug[10] as 0x10101010 INFO: Reading debug[11] as 0x10101010 INFO: Reading debug[12] as 0x10101010 INFO: cpo_min 0x10 INFO: cpo_max 0x10 INFO: debug[28] 0x70006f WARNING: Warning: A009942 requires setting cpo_sample to 0x37 INFO: *0x1080000 = 0x1ff INFO: *0x1080008 = 0x200023f INFO: *0x1080010 = 0x240027f INFO: *0x1080018 = 0x28002bf INFO: *0x1080080 = 0x80010512 INFO: *0x1080084 = 0x202 INFO: *0x1080088 = 0x202 INFO: *0x108008c = 0x202 INFO: *0x1080100 = 0x21d1100 INFO: *0x1080104 = 0xff770010 INFO: *0x1080108 = 0xf8fc1265 INFO: *0x108010c = 0x5951a0 INFO: *0x1080110 = 0xc5208000 INFO: *0x1080114 = 0x401060 INFO: *0x1080118 = 0x1010631 INFO: *0x108011c = 0x100000 INFO: *0x1080120 = 0x1000 INFO: *0x1080124 = 0x1ffe07ff INFO: *0x1080128 = 0xdeadbeef INFO: *0x1080130 = 0x2400000 INFO: *0x1080160 = 0x22d502 INFO: *0x1080164 = 0x6401400 INFO: *0x108016c = 0x25540000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc6750605 INFO: *0x1080190 = 0x5060607 INFO: *0x1080194 = 0x7080804 INFO: *0x1080220 = 0x701 INFO: *0x1080224 = 0x8800000 INFO: *0x1080250 = 0x5447a00 INFO: *0x1080270 = 0x80000000 INFO: *0x1080280 = 0x444844 INFO: *0x1080284 = 0x1488f482 INFO: *0x1080288 = 0xffffffff INFO: *0x108028c = 0xffff73ff INFO: *0x1080290 = 0x1 INFO: *0x1080400 = 0x1692672c INFO: *0x1080404 = 0x8c99d588 INFO: *0x1080408 = 0xe50c594 INFO: *0x108040c = 0x48000000 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80080000 INFO: *0x1080b2c = 0x80 INFO: *0x1080bf8 = 0x20502 INFO: *0x1080bfc = 0x100 INFO: *0x1080e40 = 0x80 INFO: *0x1080f04 = 0x2000 INFO: *0x1080f08 = 0xd INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x10101010 INFO: *0x1080f28 = 0x10101010 INFO: *0x1080f2c = 0x10101010 INFO: *0x1080f30 = 0x10101010 INFO: *0x1080f34 = 0x10104000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x11000000 INFO: *0x1080f50 = 0xf000f00 INFO: *0x1080f54 = 0xf000e00 INFO: *0x1080f58 = 0xc000c00 INFO: *0x1080f5c = 0xb000b00 INFO: *0x1080f60 = 0x8000000 INFO: *0x1080f64 = 0x9000 INFO: *0x1080f68 = 0x20 INFO: *0x1080f70 = 0x70006f INFO: *0x1080f94 = 0x80000000 NOTICE: 8 GB DDR4, 64-bit, CL=15, ECC off INFO: Time used by DDR driver 1029 ms NOTICE: BL2: v1.5(debug): NOTICE: BL2: Built : 07:08:39, Jul 1 2024 INFO: Configuring TrustZone Controller INFO: Value of region base = ffe00000 INFO: Value of region base = 1ffe00000 INFO: Value of region base = fbe00000 INFO: Value of region base = a80000000 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 WARNING: Firmware Image Package header check failed. WARNING: Failed to obtain reference to image id=3 (-2) ERROR: BL2: Failed to load image (-2) Authentication failure Re: LS1046A custom board: BL2: Failed to load image In QCVS DDR tool, if there is SPD on your target board, please create a QCVS DDR project with "reading from SPD" method, then do validation. If no SPD, please fill the "Properties" panel according to your DDR datasheet, then start validation. After all the validation in DDRv tool passing, please generate files used in atf.

当引导加载程序存在时，LPC1768 从 DeepSleep 中唤醒 我有一块带有 LPC1768 的定制板，我需要使用深度睡眠模式。一切按默认方式正常工作，但是当我安装引导加载程序并且我需要使用深度睡眠的主程序有一个偏移时，当我唤醒 MCU 时，它会清除 ctach IRQ 并随着电流增加而唤醒，它仍然卡在某处...可能进入了错误的地址。我不知道如何调试，因为调试器在深度睡眠下不工作。 有什么想法吗？