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Multi Source Translation Content

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起動後、データ フラッシュを読み取ると、データは 0 にクリアされます。 特定のデータをデータ フラッシュに書き込み、電源を再投入します。起動後、データ フラッシュ内のデータを読み取ると、データ フラッシュ内のデータは 0 にクリアされます。 データが 0 にクリアされる理由として考えられるものはありますか? Re:起動後、データフラッシュを読み取ると、データは0にクリアされます。 ご回答ありがとうございます。 原因は、デバッグコードが誤動作し、0で上書きされたことでした。 お騒ぎしてすみません。 
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32k312はbctuを使ってADCを構成する こんにちは。s32k312 と bctu を使用して ADC を構成する際に、次の質問があります。 BCTU LIST ITEMS は 32 個の ADC チャネルしかサポートしません。現在 42 個の ADC チャネルがあります。bctu を使用してこれらを設定するにはどうすればよいでしょうか? Re: 32k312 bctu を使用して ADC を構成する ADC0 の 25 個のサンプリング チャネルのみを使用する場合、データ シートによると、bctu リストのエントリ形式は次のようになります (adc0、adc1、adc0、adc1......adc0n、adc1n)。adc0 のみを構成する場合は、どのように構成すればよいですか。 Re: 32k312 bctu を使用して ADC を構成する こんにちは。この問題をどう解決すればいいでしょうか? Re: 32k312 bctu を使用して ADC を構成する それで、この問題をどう解決すればいいのでしょうか? Re: 32k312 使用bctu 配置ADC Hello, 私はそれをテストしました、そして私はあなたと同じ制限がS32DSであるように見えます。 私もTresosで試してみました: これは、選択した導関数の変換リストで使用可能な最大要素のRTD制限によるものです。 S32K の場合と同様に、32 CL サイズには制限があります。 よろしくお願いいたします。 ピーター
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32k312 使用bctu 配置ADC 您好,我在使用s32k312 使用bctu 配置ADC时,有以下问题: BCTU LIST ITEMS 只能支持32个adc channel,我现在有42个adc channel 该如何使用bctu进行配置? Re: 32k312 使用bctu 配置ADC 如果我仅使用ADC0 的25个采样通道, 但我根据数据手册,bctu list 的条目格式如下(adc0,adc1,adc0,adc1......adc0n,adc1n),如果我仅配置adc0, 该怎么配置? Re: 32k312 使用bctu 配置ADC 您好,那我应该怎么解决这个问题? Re: 32k312 使用bctu 配置ADC 那我应该怎么解决这个问题哈? Re: 32k312 使用bctu 配置ADC Hello, 我已经测试过了,我发现和你一样的限制是 S32DS。 我也在 Tresos 中尝试过: 这是由于所选衍生物的转换列表中的最大可用元素的 RTD 限制。 正如您所看到的,S32K 的大小限制为 32 CL: 顺祝商祺! Peter
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i.MX8QM Android Automotive 14 Flash the Build to an SD Card Hello, I built Android Automotive OS 14.0.0_1.1.0 for my i.MX8QM MEK board. I want to flash the resulting build into an SD card and boot from it. I found in the past releases (AAOS 12, 13) barely mentions flashing of an SD card, but it no longer appears in the manual/guide for i.MX8's AAOS 14. I found two posts from the same user, but the solutions aren't confirmed by the poster and do not make sense to me. https://community.nxp.com/t5/i-MX-Processors/iMX8QM-Android-Automotive-OS-Prepare-SD-Card-Image/m-p/1539111 https://community.nxp.com/t5/i-MX-Processors/iMX8QM-Android-Automotive-Bootloader-Image-Issue/m-p/1533451 Where can I find the information about how the android partitions should be arranged on an SD card? How about reading the eMMC content and creating an SD card image literally same as the eMMC? Re: i.MX8QM Android Automotive 14 Flash the Build to an SD Card Hi @ycheng  The reason for not providing SD Card boot image for Android Auto images might be like, For consideration of security, Android auto image supports security by default. In addition, from the perspective of practical application, normally auto applications are generally in eMMC, not SD card. Regards Harvey Re: i.MX8QM Android Automotive 14 Flash the Build to an SD Card Hi Harvey, Is there a reason that you know of? I try to port the build to an SD card flash. Maybe it could save some of my wasted effort if I can be notified about known issues with SD card boot. Thanks, Yanghao Re: i.MX8QM Android Automotive 14 Flash the Build to an SD Card Hi @ycheng  Android auto image doesn't support for SD Card boot. Regards Harvey
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S32K312 NXP RTOS flash link scripts file Dear NXP Team. I'm looking for the NXP RTOS flash link scripts. When I checked RTOS example project file, there was ram link scripts file only. So, If you have a flash link scripts file for NXP_RTOS_v0.4.1, please share the file to me. Thanks, BR, Re: S32K312 NXP RTOS flash link scripts file Hi @VaneB  Thanks for your reply. I'll find another  way.  BR, Re: S32K312 NXP RTOS flash link scripts file Hi @WW1984  I am afraid that the examples of this software are delivered only with RAM Linker File and there is no FLASH linker file available. Sorry for the inconvenience. BR, VaneB
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i.MX 8M Mini LPDDR4 EVKB Circuit data is blank I downloaded the following design file for 8MMINILPD4-EVKB, but it was blank. Could you please send me the correct file? 8MMINILPD4-EVK-DESIGNFILES/Base%20Board/LAY-31407_C2/REF-31407_C2.pdf Re: i.MX 8M Mini LPDDR4 EVKB Circuit data is blank Yes. Thank you. Re: i.MX 8M Mini LPDDR4 EVKB Circuit data is blank Do youmean this pdf file? Re: i.MX 8M Mini LPDDR4 EVKB Circuit data is blank Thank you for your reply. I checked the attachment file, and I found that REF-31407_C2.pdf is blank. I mean when I open the pdf file, there are nothing drawn. Re: i.MX 8M Mini LPDDR4 EVKB Circuit data is blank You can download it here: i.MX 8M Mini Evaluation Kit | NXP Semiconductors I also attach them to you. Any questions contact us freely
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DART-MX95 DPDK bring up Hi, I am working on bringing up DPDK on the DART-MX95. I have been following the instructions in the i.MX Linux Reference Manual, specifically Chapter 10: Data Plane Development Kit (DPDK). In section 10.5.2.2, the manual specifies the device tree (dtb) to be used for the i.MX 95 EVK. However, I couldn’t find any mention of a DPDK-supported device tree for the DART-MX95. Are there any recommended device tree configurations or specific modifications required for this platform? Related Information: I am using the nanbield release of Yocto. The Yocto DPDK recipe comes from this source. Additionally, I’ve encountered the following issues: In section 10.5.4.2.1, the command below results in an error: # devlink dev param set pci/0002:00:08.0 name si_num_rings cmode driverinit value 0106 /tmp/devlink dev param set pci/0002:00:08.0 name si_num_rings cmode driverinit value 0106 kernel answers: No such device When attempting to set VF trust mode using the command: # ip link set eth0 vf 0 trust on RTNETLINK answers: Operation not supported My primary issue is that DPDK does not recognize the port bonded for DPDK usage. To test DPDK functionality, I follow these steps: # dpdk-devbind.py --bind=uio_pci_generic 0002:00:00.0 # dpdk-devbind.py -s Network devices using DPDK-compatible driver ============================================ 0002:00:00.0 'Device e101' drv=uio_pci_generic unused=vfio-pci Network devices using kernel driver =================================== 0002:00:08.0 'Device e101' if=eth1 drv=fsl_enetc4 unused=vfio-pci,uio_pci_generic *Active* Other Network devices ===================== 0002:00:10.0 'Device e101' unused=vfio-pci,uio_pci_generic No 'Baseband' devices detected ============================== No 'Crypto' devices detected ============================ No 'DMA' devices detected ========================= No 'Eventdev' devices detected ============================== No 'Mempool' devices detected ============================= No 'Compress' devices detected ============================== No 'Misc (rawdev)' devices detected =================================== No 'Regex' devices detected =========================== # /usr/share/dpdk/examples/dpdk-l2fwd EAL: Detected CPU lcores: 6 EAL: Detected NUMA nodes: 1 EAL: Detected static linkage of DPDK EAL: Multi-process socket /var/run/dpdk/rte/mp_socket EAL: Scan for (fslmc) bus failed. EAL: Selected IOVA mode 'PA' EAL: VFIO support initialized TELEMETRY: No legacy callbacks, legacy socket not created MAC updating enabled EAL: Error - exiting with code: 1  Cause: No Ethernet ports - bye Could you provide guidance on resolving these issues? Are there additional configurations or dependencies I need to address? Thank you for your support. Re: DART-MX95 DPDK bring up i.mx95 is still under preproduction, we don't have further information can share, pls contact local representative to get further help Distributor Network | NXP Semiconductors
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S32K3xx MCU programmer and debugger Hi ,    Kindly suggest cost effective S32K3xx cortex m7  programmer and debugger regards, Karmegan C Re: S32DS IDE installation and development package installation for s32k3xx Hello, Sorry, this is different topic. I am not able to help here. Always respect the release notes of RTD packages, otherwise the packages will not be compatible. Best regards, Peter Re: S32DS IDE installation and development package installation for s32k3xx Hi,     After S32DS 3.5 IDE installation, I opened an example Flex CAN project  from RTD  s32kxx and built it. I got the errors as are below, In file included from ../board/Siul2_Port_Ip_Cfg.c:42: ../board/Siul2_Port_Ip_Cfg.h:46:10: fatal error: Siul2_Port_Ip_Types.h: No such file or directory 46 | #include "Siul2_Port_Ip_Types.h" C:/Users/karme/workspaceS32DS.3.5/FlexCAN_Ip_Example_S32K344/RTD/include/CanIf.h:52:10: fatal error: CanIf_Cfg.h: No such file or directory 52 | #include "CanIf_Cfg.h" | ^~~~~~~~~~~~~ compilation terminated. make: *** [RTD/src/subdir.mk:38: RTD/src/CanIf.o] Error 1 In file included from ../RTD/src/Can_43_FLEXCAN.c:104: C:/Users/karme/workspaceS32DS.3.5/FlexCAN_Ip_Example_S32K344/RTD/include/Can_43_FLEXCAN.h:110:10: fatal error: Soc_Ips.h: No such file or directory 110 | #include "Soc_Ips.h" | ^~~~~~~~~~~ How to fix these mistakes I need your help with the S32DS IDE, S32K3xx development package, and RTD installation since I believe there may have been errors in the package and IDE installation time. There are drivers for the boot loader, CAN, UDS, and FLASHING S32K342 in the RTD or S32K3xx development packages. Re: S32K3xx MCU programmer and debugger Hello, There is wide variety of devices you can use. It depends on how serious you will go with your development. Very basic - is embedded open SDA - free on the evaluation boards. basic - PE micro advanced - iSystem, GHS probe Pro - Lauterbach Best regards, Peter
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[S32K3] Image verificaiton fail in Secure boot Hi.  Now I have developed Secure boot with HSE. In bootloader sequence, application image should be verified.  S32K344_Basic_SecureBoot Project is refered in S32K3_HSE_DemoExamples. The verifying function (HSE_VerifyBootImage) is returning failure (HSE_SRV_RSP_VERIFY_FAILED).  Could you recommand my mistake and comment and fail reason? My project loader and code is attached like below. Thank you. log output) Flash Erase Ok Flash Program ok(7d2040, len:128) [SEC BOOT] Image Verify failed.(0x55a5a164) Code) #define ADKP_LENGTH (uint8_t)16U   #define TAG_LENGTH 28 #define APP_HEADER_LENGTH 0x40U   /* RAM address for GMAC */ uint8_t temp_addr_of_app_image[32] = {0xFF};   const uint8_t* pAppBL = APP_ADDR; //Application Start 0x500000 in ld uint32_t AppBL_codeLength = (APP_SIZE - 0x2000); //APP_SIZE 0x2d4000 in ld --> 0x2d2000   /* ADKP Key/Password required variables */ volatile uint8_t programmed_appdebugkey[ADKP_LENGTH] = {0U}; //Store the reading of the ADKP volatile uint8_t applicationDebugKeyPassword[16U] = { 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,   0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x21 }; hseSrvResponse_t HSE_ProgramAdkp(void) {     hseSrvResponse_t srvResponse;       /* WARNING: This operation is irreversible */     /* Program the ADK/P (Application debug key/password) */     srvResponse = SetAttr(HSE_APP_DEBUG_KEY_ATTR_ID,         sizeof(hseAttrApplDebugKey_t), (void *)&applicationDebugKeyPassword);     return srvResponse; }   /* Reads ADKP hash */ hseSrvResponse_t HSE_ReadAdkp( uint8_t *pDebugKey ) {     hseSrvResponse_t srvResponse;     srvResponse = GetAttr             (                     HSE_APP_DEBUG_KEY_ATTR_ID,                     sizeof(hseAttrApplDebugKey_t),                     (void *)pDebugKey             );     return srvResponse; }   bool secure_boot_fw_verify(void) {   hseSrvResponse_t srvResponse;   uint32_t temp_addr_of_app_image[32] = {0xFF};     memset((void *)&programmed_appdebugkey,0U,ADKP_LENGTH);   srvResponse = HSE_ReadAdkp((uint8_t *)&programmed_appdebugkey);     /*    * First time when ADKP is not programmed,    * read adkp will always result in not allowed    * If ADKP is not programmed then do so    */   if( (HSE_SRV_RSP_NOT_ALLOWED == srvResponse))   {     SYS_TRACE("[SEC BOOT] ADKP is not programmed\r\n");     srvResponse = HSE_ProgramAdkp();     if (HSE_SRV_RSP_OK != srvResponse)     {       SYS_TRACE("[SEC BOOT] Program ADKP is failed.(0x%x)\r\n", srvResponse);       return false;     }   }     /* Generate Tag of size 32 over the provided APPBL */   srvResponse = HSE_SignBootImage(pAppBL, TAG_LENGTH, temp_addr_of_app_image);   if (HSE_SRV_RSP_OK != srvResponse)   {     SYS_TRACE("[SEC BOOT] Sign Image failed.(0x%x)\r\n", srvResponse);     return false;   }     GVP_FlashErase(pAppBL + APP_HEADER_LENGTH + AppBL_codeLength, sizeof(temp_addr_of_app_image));     GVP_FlashProgram(pAppBL + APP_HEADER_LENGTH + AppBL_codeLength, temp_addr_of_app_image, sizeof(temp_addr_of_app_image));       /* Verify that the generated TAG is valid for the APPBL */   srvResponse = HSE_VerifyBootImage(pAppBL);   if (HSE_SRV_RSP_OK != srvResponse)   {     SYS_TRACE("[SEC BOOT] Image Verify failed.(0x%x)\r\n", srvResponse);     return false;   }   else   {     SYS_TRACE("[SEC BOOT] Image Verify ok\r\n");     return true;   }   }   /* bootloader main */ main() { .... secure_boot_fw_verify(); .... }     MEMORY  {     int_pflash               : ORIGIN = 0x00400000, LENGTH = 0x00040000       /* 256K*/     HSE_BINARY              : ORIGIN = 0x00440200, LENGTH = 0x00024000 /* Leave block 0 for HSE FW binary */     int_flash               : ORIGIN = 0x00500000, LENGTH = 0x002D4000 /* Use only blocks 1,2,3 for install project */ ...     #define IVT_BOOT_CFG_WORD_BOOT_SEQ  (1 << 3)   .section ".boot_header","ax"   .long SBAF_BOOT_MARKER /* IVT marker */   .long (CM7_0_ENABLE << CM7_0_ENABLE_SHIFT) | (CM7_1_ENABLE << CM7_1_ENABLE_SHIFT) | IVT_BOOT_CFG_WORD_BOOT_SEQ /* Boot configuration word */ Re: [S32K3] Image verificaiton fail in Secure boot Hi Lukaszadrapa Thank you for your support. Re: [S32K3] Image verificaiton fail in Secure boot Hi @Changhawn  Do you follow this? It's a screenshot from Secure boot application note. You can check how it is implemented in S32K344_SecureBootBlinky project in HSE DemoExamples. Regards, Lukas
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CAN HighLevel API - osci 上无信号 嗨,大家好, 我希望你今天一切顺利。我有一个关于 CAN 的问题。因此,我尝试使用低级 API 的 CAN 示例,即使我将 PINS 从 PTA6/7 重新路由到 PTB0/1,它也能正常工作。我可以在 osci 上看到所有发送信号。可以肯定的是,PTB0/1 没有 CAN 收发器。 但是如果我现在尝试 CAN 高级 API 示例,在 S32DS 中配置 PINS、PORT、CAN_43_FLEXCAN、..。代码生成没有任何错误,项目也正在编译和链接。但我在 osci 上看不到任何信号。PTA6/7 和 PTB0/1 上均不存在。 您可以在附件中找到高级 API 的示例。 提前感谢您的帮助!
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S32K344-Startup sequence without HSE Hello: I have a question about the Boot process: When I used S32DS to generate a sample code, there was no HSE firmware, and I checked the code and found that the address of IVT was 0040_0000h, and the function address of ResetHandler was stored at 0Ch in IVT (Cortex-M7_0 core start address). But I saw the following description in the Boot Overview chapter of RM: After the hardware reset sequence completes, the only CPU available is in the HSE subsystem that is referred to as the HSE CPU. The HSE CPU starts executing firmware code in the HSE code flash memory from a fixed location that contains the SBAF code. So, in the absence of HSE firmware, from the completion of the hardware reset sequence to the execution of the function at the Core0 startup address in IVT, is it also controlled by HSE_SBAF? BestRegards, Simon Re: S32K344-Startup sequence without HSE Hi @Simon-Liu  yes, even if HSE FW is not installed, SBAF is doing this during the reset: Regards, Lukas
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T1042d4rdb-64b building process. I have downloaded the source and ppce5500 yocto cache from https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=7726177, I installed the source iso first and then the yocto cache, ran the host_prepare.sh, and sourced(fsl_env_setup) with machine t1042d4rdb-64b. I ran the command $ bitbake fsl-toolchain Got the error "the '--set-upstream' option is no longer supported. Please use '--track' or '--set-upstream-to' instead." I update the source/poky/bitbake/lib/bb/fetch2/git.py file to use --set-upstream-to command and reran $bitbake fsl-toolchain And now i am getting the error below "ERROR: Function failed: Fetcher failure: Fetch command failed with exit code 128, output: fatal: branch 'origin/master' does not exist". Is there a way to resolve this? I checked the $$ git remote -v fsl-public git://git.freescale.com/yocto/meta-freescale (fetch) fsl-public git://git.freescale.com/yocto/meta-freescale (push) and when i tried openning on chrome, it showed that the site does not exist. T1042 Re: T1042d4rdb-64b building process. Hi, I fetched the yocto sdk dunfell branch and updated the manifest file to use the freescale git source instead of the codeaurora source. Then I updated the src_url in the layers as well and removed nativesdk-cst and I finally had a successful build. Thanks for the assistance. Re: T1042d4rdb-64b building process. You can review as an option dunfell branch, please take a look in the links below: https://github.com/nxp-qoriq/yocto-sdk/tree/dunfell https://github.com/Freescale/meta-freescale/tree/dunfell?tab=readme-ov-file Re: T1042d4rdb-64b building process. Hi, The link  you have provided contains the meta-qoriq repo. I am trying to build the fsl-toolchain or fsl/ls-image-main, on running bitbake-layers show-recipes, it shows that these(fsl-toolchain & fsl-image-main) reference meta-freescale. I am not able to find this from the link you provided. But i have found https://github.com/Freescale/meta-freescale and this depends on openembeddedcore. I understand that i have to replace the url src of my project (meta-freescale) to the ones still being maintained above, but what branch do I have to use? I am not finding any list of supported devices which lists t1022 or t1042. Regards
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CAN HighLevel API - osci に信号がない こんにちは、みんな、 今日はお元気でいらっしゃることを願っています。CANについて質問があります。そこで、低レベルのAPIでCANの例を試しましたが、PTA6/7 -> PTB0/1からPINSを再ルーティングしても問題なく動作しています。osciですべての送信信号を見ることができます。確かに、PTB0/1にはCANトランシーバーがありません。 しかし、今、PINS、PORT、CAN_43_FLEXCAN,..が設定されたCANの高レベルAPIの例を試してみるとS32DSで。コードはエラーなしで生成され、プロジェクトもコンパイルおよびリンクされています。しかし、osciに信号が見当たりません。PTA6/7でもPTB0/1でも。 添付ファイルには、High Level API の例があります。 事前に助けてくれてありがとう!
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T1042d4rdb-64b 构建过程。 我已经从https://nxp.flexnetoperations.com/control/frse/download下载了源代码和ppce5500 yocto缓存?同意=接受&元素=7726177,我首先安装了源 iso,然后安装了 yocto 缓存,运行了 host_prepare.sh,并使用机器 t1042d4rdb-64b 进行采购(fsl_env_setup)。我运行了命令 $ bitbake fsl-工具链 收到错误 “‘--set-upstream’选项不再受支持。请改用‘--track’或‘--set-upstream-to’。”我更新了 source/poky/bitbake/lib/bb/fetch2/git.py 文件以使用 --set-upstream-to 命令并重新运行 $bitbake fsl工具链 现在我收到以下错误 “错误:功能失败:获取程序失败:获取命令失败,退出代码为 128,输出: 致命:分支‘origin/master’不存在”。 有办法解决这个问题吗?我检查了$$ git remote -v fsl-public git://git.freescale.com/yocto/meta-freescale(拿来) fsl-public git://git.freescale.com/yocto/meta-freescale(推) 当我尝试在 chrome 上打开时,它显示该网站不存在。 T1042 回复:T1042d4rdb-64b 构建过程。 你好, 我获取了 yocto sdk dunfell 分支并更新了清单文件以使用 freescale git 源而不是 codeaurora 源。然后我也更新了层中的 src_url 并删除了 nativesdk-cst,最终成功构建。 谢谢您的帮助。
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ADC failed I tested the ADC pins using the S32K312 chip and found that the IO pin PTE18 did not successfully convert data, but the other two pins, PTC7 and PTD28, both worked successfully as ADCs. In the IDE, the configurations for these pins are almost identical. Observing the schematic diagram, I did not find any pull-down situation for the PTE18 pin Re: ADC failed Please try to call Siul2_Port_Ip_Init and check it again. Re: ADC failed Is here wrong ? Re: ADC failed I used SW32K3_RTD_R21-11_4.0.0_P04_D2312 as my RTD.However,I changed it to SW32K3_S32M27x_RTD_R21-11_5.0.0_D2410,the result is same. Re: ADC failed Hi Please tell me what version of RTD you are using. Please check bit 6 MUX_MODE_EN_ADC1_S23 of 38.2.51 Read Write GPR On Functional Reset 4 (DCMRWF4). Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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T1042d4rdb-64b のビルド プロセス。 https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=7726177 からソースとppce5500 yoctoキャッシュをダウンロードし ましたが、最初にソースisoをインストールし、次にyoctoキャッシュをインストールし、host_prepare.shを実行しました。そして、マシンT1042D4RDB-64Bで供給(fsl_env_setup)。コマンドを実行しました $ bitbake fsl-toolchain エラーが発生しました 「'--set-upstream' オプションはサポートされなくなりました。代わりに「--track」または「--set-upstream-to」を使用してください。--set-upstream-toコマンドを使用して再実行するように、source / poky / bitbake / lib / bb / fetch2 / git.py ファイルを更新します $bitbake FSLツールチェーン そして今、私は以下のエラーを取得しています "エラー: 関数が失敗しました: フェッチャーの失敗: フェッチ コマンドが終了コード 128 で失敗しました。出力: fatal: branch 'origin/master' does not exist"というエラー メッセージが表示されるようになりました。 これを解決する方法はありますか?$$を確認しました git remote -v FSL-パブリック git://git.freescale.com/yocto/meta-freescale(フェッチ) FSL-パブリック git://git.freescale.com/yocto/meta-freescale(プッシュ) そして、Chromeで開こうとしたとき、サイトが存在しないことを示しました。 T1042 日時:T1042D4RDB-64Bのビルドプロセス。 こんにちは yocto sdk dunfell ブランチをフェッチし、codeaurora ソースの代わりに freescale git ソースを使用するようにマニフェスト ファイルを更新しました。次に、レイヤーのsrc_urlも更新し、nativesdk-cstを削除して、最終的にビルドに成功しました。 ご協力いただきありがとうございます。
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CAN HighLevel API - No signals on osci Hi Guys, I hope you are doing fine today. I have a question about CAN. So I tried the CAN example with low level API, which is working fine, even if I reroute the PINS from PTA6/7 -> PTB0/1. I can see all the send signals on osci. For sure PTB0/1 are without a CAN transceiver. But If I try now the CAN high level API example, with configured PINS,PORT, CAN_43_FLEXCAN,..in S32DS. Code is generated without any error and project is also compiling and linking. But I cannot see any signals on the osci. Neither on PTA6/7 nor on PTB0/1. In the attachement you can finde the example of the High Level API.  Thanks for any help in advance! Re: CAN HighLevel API - No signals on osci Hi, Loopback was one of the issues, the other was to connect another CAN-node on the bus to get the example working. Re: CAN HighLevel API - No signals on osci Hi, seems you started CanController_0 which is configured for loopback mode in setting, so you get no signals on module pins (PTA6/7 or PTB0/1). CanController_1 is not set for loopback mode, but it is not started at all, so no transfer can be seen on its pins (PTC8/9). BR, Petr
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S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled Hello: I found in the section [32.3.1.2 Configuration details when the HSE_B firmware usage feature flag is enabled] in RM that the Reserved area, Application flash memory area, and Application data flash memory area have all been reduced. What data are stored in these areas after the HSE firmware is installed and used? BestRegards, Simon Re: S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled You'll find out when you download HSE_B Firmware Reference Manual. It is a secure file, so following procedure is needed to follow unless you have already done it before: https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf For better understanding you may also see following link: https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS
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Using SAI1 to drive 3 audio outputs with 2 TX_Data Hello, I'm running RT1024 on a custom board. SAI1 is configured as an I2S master to control 1 PCM4104. This DAC is capable of driving 4 output channels, it drives 2 channels per logic state of LRCK: when LRCK is high, CH1 reproduces whatever comes to DATA0 and CH3 reproduces whatever comes to DATA1. I'm trying to play sounds taking the "evkmimxrt1024_sai_interrupt_transfer" example and changing SAI3 to SAI1 with the next configuration: The routine is as follows: -Initialize clocks -Initialize SAI1 -Create SAI_TransferTxCreateHandle STATE_EMITTING_RIGHT -Turn on LED1 -Configure SAI as left justified, monoright and channel 1 (I leave this channel 1 as the example but don't fully understand why is this value), asynchronous mode, master. -Configure the SAI_TransferTxSetConfig -Set the BCK with SAI_TxSetBitClockRate -Reproduces sound with SAI_TransferSendNonBlocking -Turn off LED1 STATE_EMITTING_LEFT -Turn on LED2 and LED3 -Configure SAI as left justified, monoleft and channel 1 (I leave this channel 1 as the example but don't fully understand why is this value), asynchronous mode, master. -Configure the SAI_TransferTxSetConfig -Set the BCK with SAI_TxSetBitClockRate -Reproduces sound with SAI_TransferSendNonBlocking -Turn off LED2 and LED3 Then repeats alternating playing sound between left and right. Results: So far, debugging with MCUxpresso I've been able to reproduce sounds through channel 1 (left) and channel 2 (right). Issues: 1)This doesn't work all the time, if I try to toggle both LED2 and LED3, the program reproduces 10 times the sound on the left and 9 times on the right and then completely freezes. If I remove writing1&writing0 to LED2 or LED3, the program has no freezing, it alternates reproducing sounds left&right without problem. 1.1) In order to reproduce sounds, I need to run the program through MCUXpresso debugging mode. If I run the program without it, volume goes very low and it only reproduces sound through monoLeft. This doesn't make any sense to me. I'm using the same code I tested on another custom board with the same RT1024 and the same audio DAC, but using SAI3 instead of SAI1 2)I see the audio data coming out from TX_DATA0 but not from TX_DATA1. How could I get data to come out from TX_DATA1 pin too? I've attached the main programming code files for further detail. Please, any help would be appreciated!! Thanks!! Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Thanks @mayliu1 !! I've checked your previous answer as the solution as now data comes out through TX_DATA1. Also, I'll create a new case to troubleshoot the actual control of the data as suggested Thanks again!! Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hi @DigitalBrain , Thanks for your update information. Sorry I don't know the corresponding relationship between audio jack1, audiojack2 ,jack3  with your SAI interface. But I can tell you that SAI_GetClassicI2SConfig, SAI_GetLeftJustifiedConfig, SAI_GetRightJustifiedConfig all can support 2 slot. Please modify your code, set sai_mono_stereo_t as kSAI_Stereo.  I also suggest you can refer to this link. https://www.nxp.com/docs/en/application-note/AN12090.pdf If you still have question, Please create a new case, I will do my best to help you. BR mayliu Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hello @mayliu1  Thanks for your reply!! Utilizing kSAI_Channel#Mask got me to transmit data through TX_DATA1, however I'm wondering how is it possible to control which data is sent to each of the TX_DATAX. For example, is it necessary to reconfigure all each time I want to transmit through audio jack1, audiojack2 audiojack3? Right now, I need to run all of this routine each time I want to transmit through a jack: SAI_GetLeftJustifiedConfig(&saiConfig, AUDIO_BIT_WIDTH, kSAI_MonoRight,kSAI_Channel0Mask); saiConfig.syncMode    = SAI_TX_SYNC_MODE; saiConfig.masterSlave = SAI_MASTER_SLAVE; SAI_TransferTxSetConfig(SAI_MODULE, &txHandle, &saiConfig);   /* set bit clock divider */ SAI_TxSetBitClockRate(SAI_MODULE, AUDIO_MASTER_CLOCK, AUDIO_SAMPLE_RATE, AUDIO_BIT_WIDTH,   AUDIO_DATA_CHANNEL);   GPIO_PinWrite(BOARD_INITPINS_LED_IZDA_GPIO, BOARD_INITPINS_LED_IZDA_PIN, 1); /*  xfer structure */ temp          = (uint32_t)music; xfer.data     = (uint8_t *)temp; xfer.dataSize = MUSIC_LEN; isFinished = false;   status_t result_IZDA = SAI_TransferSendNonBlocking(SAI_MODULE, &txHandle, &xfer); /* Wait until finished */ while (isFinished != true) { }   GPIO_PinWrite(BOARD_INITPINS_LED_IZDA_GPIO, BOARD_INITPINS_LED_IZDA_PIN, 0);   delay_msec(800); Then, if I want to transmit through audiojack 2 I do all the same just changing kSAI_MonoRight to kSAI_MonoLeft. And finally, if I want to transmit through audiojack3 (this is the one connected to TX_DATA1) I do all the same changing to kSAI_MonoLeft, kSAI_Channel1Mask . This time kSAI_Channel1Mask because (as far as I understand) will transmit through TX_DATA1 Thanks!! Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hi @DigitalBrain  I think DEMO_SAI_CHANNEL depend on your needs, what I show you is just a demo. You can also set saiChannelMask, this param can also set multiple SAI channel. function -> SAI_TransferTxSetConfig will call SAI_TxSetConfig In SAI_TxSetConfig function , saiChannelMask  set TCR3 register. BR mayliu Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hello, @mayliu1  Thanks for your input! Could you please  show me the value you set for DEMO_SAI_CHANNEL? If I do the following: #define DEMO_SAI_CHANNEL (0) //Now it doesn't matter as 3 is being hardcoded SAI_TxSetChannelFIFOMask(DEMO_SAI,5); SAI_GetLeftJustifiedConfig(&saiConfig, DEMO_AUDIO_BIT_WIDTH, kSAI_MonoRight,3); The register sets to 3, seems like the value that matters is the sent on SAI_GetLeftJustifiedConfig Also, how is it possible to select the data to transfer through TX_DATA0 and TX_DATA1 ? Thanks! Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hi @DigitalBrain  Thanks for your update information. I did a validation on my side, I can set TCE as 0x03, Please refer to what I did. 1: First , I think you should set your SAI  TX DATA1 . Please note that the GPIO TX DATA1  is not real connect, your code should be based on your customed board. The modified configurations I made are just for giving you a demonstration. Please develop your code strictly base on your customed board. 2: Second, you need call SAI_TxSetChannelFIFOMask(DEMO_SAI, 0x03) in your project I import SDK demo "evkmimxrt1020_sai_interrupt_transfer" , and use MIMXRT1020-EVK board . Wish it helps you. If you still have question about it, please kindly let me know. If you have other question, Please create a new case, Thanks. BR mayliu Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Furthermore, even placing the value directly to 0x3 gets 0x1 as result void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) { base->TCR3 &= ~I2S_TCR3_TCE_MASK; base->TCR3 |= I2S_TCR3_TCE(0x3); } Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hello, @mayliu1  That's true. I've set it to 3: SAI_TxSetChannelFIFOMask(SAI1,3); but after executing the function, the register gets set to 0x1 instead of 0x3. For some reason, I'm not being able to set it to 0x3 Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hi, @DigitalBrain  Thanks for your update information. I notice that your TCE is 1,  I don't think it is a right value. TCE should be 0x03(0b0011) if you want both channel1 and channel 2  working. Please double check your config function. BR mayliu Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hello, @mayliu1  Thanks for your reply. These are the values: TCE is set to 0x1.  Maybe I need to use a different function to transmit through TX_DATA1? Currently I'm using: sai_handle_t txHandle = {0}; sai_transfer_t xfer; SAI_TransferSendNonBlocking(SAI1, &txHandle, &xfer); I understood this function would send the same data at the same time through all the enabled TX_DATA channels. Is it correct? Thanks!! Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hi @DigitalBrain , Thanks for your reply. Could you check your SAI1 TCR3 register value. You can check MCUXpresso IDE -> Peripherals -> SAI1 -> TCR3->TCE Wish it helps you. If you still have question about it, please kindly let me know. BR mayliu Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hello @mayliu1  initialization is as follows: SAI_Init(DEMO_SAI); SAI_TransferTxCreateHandle(DEMO_SAI, &txHandle, callback, NULL); SAI_TxSetChannelFIFOMask(DEMO_SAI,3); I thought that adding the last line would be enough to transmit through TX_DATA1 but it wasn't. What am I missing? Thanks!! Re: Using SAI1 to drive 3 audio outputs with 2 TX_Data Hi @DigitalBrain , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. Question: 1)This doesn't work all the time, if I try to toggle both LED2 and LED3, the program reproduces 10 times the sound on the left and 9 times on the right and then completely freezes. If I remove writing1&writing0 to LED2 or LED3, the program has no freezing, it alternates reproducing sounds left&right without problem. Answer:  I have download your code, but there are no LED1,LED2,LED3 definition. when the project freezing, Please check Register, Fault, Peripherals->SAI status. You can also read SAI status in your code project. Question: 1.1) In order to reproduce sounds, I need to run the program through MCUXpresso debugging mode. If I run the program without it, volume goes very low and it only reproduces sound through monoLeft. This doesn't make any sense to me. I'm using the same code I tested on another custom board with the same RT1024 and the same audio DAC, but using SAI3 instead of SAI1 Answer:  If the volume changed, I suggest you double check Audio format. Question: 2)I see the audio data coming out from TX_DATA0 but not from TX_DATA1. How could I get data to come out from TX_DATA1 pin too? Answer: If you want to use TX_DATA0 and TX_DATA1 of SAI1 , please refer to the content of Section 34.5.1.7 "Transmit Configuration 3 (TCR3)" in the MIMXRT1024RM. You should set the Transmit Enable (TCE) bit in Transmit Configuration 3 (TCR3) when initializing the SAI1. Wish it helps you. If you still have question about it, please kindly let me know. BR mayliu
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AコアのS32G PWM こんにちは、専門家 S32G399A A-COREでPWM出力を制御できますか? Re:AコアのS32G PWM はい。また、S32G399A〜8チャネルのPWM出力を構成できますか?ありがとうございます!
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