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******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: Potentiometers --> ADC inputs * USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) * USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT0 interrupt and external interrupt source 1 are implemented. PIT interrupt * toggle LED every second, external interrupt causes IVOR1 exception. * * This example also shows, how to use exceptions, while HW vector mode is used. * After SW1 button is pressed, uninitialized RAM is read and IVOR1 exception is * reached. In IVOR1, only endless loop is implemented and micro has to be reset * externally if you want to get out from this loop. * * * For correct HW vector mode setup, following files was added to the project: * * - exceptions.s * - handlers_vle.s * - HW_vector.c * * * Following files was modified (all changes are marked by comment): * * - mem.ld * - sections.ld * - Vector.c * - MPC57xx__Interrupt_Init.c * * * Following files was removed from project (files are still place in project, but * not compiled and linked) * * - intc_sw_handlers.S * - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW: X-MPC5744P-144DC, MPC57xx motherboard * MCU: PPC5744PFMLQ8 0N15P * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: User LED 1 connected to A0 (P8.0), * User switch SW1 connected to A1 (P8.1) * * * ------------------------------------------------------------------------------ * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * Example uses external ADC triggering from eTPU channels, that are for purpose * of this example configured for eTPU GPIO function for all eTPU channels that * can trigger start of SDADC conversion. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * eSCI_A is USBtoUART bridge (connector J21) * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

******************************************************************************** Detailed Description: This config tool simplifies DCF records calculation for MPC5746R device. Look at HowToUse sheet for simple guideline, then work with DCF sheet Note: Macros have to be enabled! ******************************************************************************** BR, Petr

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC567XKIT516 it initializes EBI for mounted external SRAM device. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: ETPUC0(J24-0) -> USER_LED_8 (J5-8) * ETPUC1(J24-1) -> USER_LED_7 (J5-7)(to see blinking LEDs) * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

******************************************************************************** * Detailed Description: * * * This example shows usage of FlexPWM and Sine Wave generator (SGEN) modules. * The setting is selected in the way to have a PWM output signal synhronized with * SWG output signal. This is necessary for resolver usage in motor control appls. * The CTU_0 is triggered from FlexPWM_0's. The PMWB output rising edge is used here. * The CTU generates the eTIMER1_TRG signal, that is a trigger signal for the * SGEN module. The delay between PWMB and SGEN trigger is changed so you can see * the generated sinusoidal signal change phase against the PWMB output. * * See attached Excel sheet for calculation of parammeters used here (AUX0_clk_DIV0, * AUX0_clk_DIV1, SGEN_IOFREQ, PWM_PRESCALER, PWM_MODULO). * * This example is set for 9.765625KHz SGEN/PWM frequency. * * Note because the SGEN trigger input is an asynchronous signal, it must be held high * for at least 2 SGEN clock cycles in order to capture the input trigger. * As the CTU generates the trigger as a pulse of single CTU clock width, the CTU clock must be * half of the SGEN clock at least. * * Use the AUX0_clk_DIV0 to test this behaviour. * * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P11.8 - D[7] .. SGEN output * connected to FEC PHY's MIIMODE input on motherboard, * to see full amplitude remove J26 * * P8.12 - A[11] .. FlexPWM A[0] output * P8.11 - A[10] .. FlexPWM B[0] output * * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in FlexCAN RAM (user must choose it in the option at the end of * main function). * Example configures FlexCAN module, initializes ECC for all FlexCAN RAMs, then * it injects ECC error to the Message Buffer 9. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * Reported FlexCAN ECC error address is corrected according RM, section 7.12.2.3 * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** Detailed Description: Configures the FlexCAN_0 to transmit and receive a CAN FD message with or without bit rate switching for data phase. Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. NOTE! Termination resistor (120Ohm) have to be placed on transceivers output ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5748G revD1 Maskset: 0N78S Target : FLASH Fsys: 160 MHz PLL ******************************************************************************** Revision History: 1.0 Jun-21-2021 Petr Stancik Initial Version *******************************************************************************/

This simple example shows the ADC setting for the scan mode and usage of Trimmer on TRK-MPC5604P board. Use Trimmer to dim the LED1. Regards, Petr ******************************************************************************** * Detailed Description: * * ADC testing and usage of Trimmer on TRK board * * ------------------------------------------------------------------------------ * Test HW: TRK-MPC5604P * Maskset: 0M36W * Target : internal_RAM * Terminal: no * Fsys: 64 MHz with 8 MHz XOSC reference * EVB connection: * * Use Trimmer to dim the LED1 * * NOTE! Be sure the ADC is powered, J21 5V jumper ON * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: Potentiometers --> ADC inputs * USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) * USER_DEV_RV3(J4-8) --> ANA_1 (J18-4) * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal RAM (user must choose it in the option at the end of main * function). * ECC fault is generated with using of core register E2EECSR. If error injection * is enabled (E2EECSR0[INVC]=1) and certain mask is set (E2EECSR0[CHKINVT]), * subsequent write to SRAM creates error in SRAM array. * When corrupted data is read the IVOR1 exception handler is called in case of * multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt handler * is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * File: main.c * Owner: Peter Vlna * Version: 1.7 * Date: Oct-10-2017 * Classification: General Business Information * Brief: Example contains startup with PLL0 200MHz as system clock * and demonstrates reset triggered on FCCU Alarm state * counter exppire. ******************************************************************************** * Test HW: MPC57xx * Maskset: 1N83M (cut 2.0B) * Target : internal_FLASH * Fsys: 200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0 Oct-19-2015 Peter Vlna Initial Version 1.1 Nov-11-2015 Peter Vlna Added PPL0 200MHz as system clock 1.2 Dec-02-2015 Peter Vlna Added Flash controller init 1.3 Dec-02-2015 Peter Vlna Fixed system clock init 1.4 Feb-07-2017 Peter Vlna SWT0 and SWT1 disabled in startup 1.5 May-31-2017 Peter Vlna Fixed comments in AC6 (CLKOUT) 1.6 Oct-04-2017 Peter Vlna Added PIT + Interrupts 1.7 Oct-05-2017 Peter Vlna FCCU EOUT test in Alarm state with SMC *******************************************************************************/

This document shows, how to use CRC gen utility in CodeWarrior for MCU IDE. 1) Create new project in CodeWarrior. 2) Create a file calc_crc.crc in the Project/Project_Settings/Linker_File directory. 3) Open project settings, choose C/C++ Build ->Settings and add the following command to Post-build steps: "${MCU_TOOLS_HOME}/bin/crcgen.exe" "${BuildLocation}/${BuildArtifactFileName}" -crc "${ProjDirPath}/Project_Settings/Linker_Files/calc_crc.crc" -srec "${BuildLocation}/${BuildArtifactFileName}.crc.mot" 26 4) Open calc_crc.crc and configure required parameters. Meaning of single lines is described in CodeWarrior reference manual called Targeting_Microcontrollers I used following code (it is only example) 5) Build your project. 6) File MPC5604B-CRCTest.elf.crc.mot was created Now you have s-record, which contains CRC and which could be loaded to microcontroller.

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM module. * The Submodule0 is set to generate independent PWMA and PWMB signals * The PWMX is used as input for the Capture feature. * Capture logic is set to capture one rising and one falling edge in one shot mode. * Thus you can check the edge placing and calculate a generated duty cycle. * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5744P rev.D * Maskset: 1N16P * Target : FLASH * Fsys: 200 MHz PLL1 * Debugger: Lauterbach * * * EVB connection: * * J1.3 - D[9] .. FlexPWM X[0] input * J1.5 - A[11] .. FlexPWM A[0] output * J1.7 - A[10] .. FlexPWM B[0] output * * * to measure generated pulse connect X[0] input with either A[0] or B[0] outputs. * ********************************************************************************

This simple example shows usage of the FlexPWM module on the TRK board. If a PWM output is connected to the LED you can see its dimming. Regards, Petr ******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM module. * The Submodule0 is set to generate independent PWMA and PWMB signals and vary * its duty cycles. The PWMX is also enabled as output and is set for fixed 50% * duty. * * You can remove LED_EN jumpers and connect FlexPWM A an B outputs to LEDs to see * its dimming. * * ------------------------------------------------------------------------------ * Test HW: TRK-MPC5604P * Maskset: 0M36W * Target : internal_RAM * Terminal: no * Fsys: 64 MHz with 8 MHz XOSC reference * Debugger: IDCPPCNEXUS * * TRK board connection: * * P4.10 - D[9] .. FlexPWM X[0] output * P1.11 - A[10] .. FlexPWM B[0] output * P1.12 - A[11] .. FlexPWM A[0] output * * ********************************************************************************

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (located in internal data flash). * Also it shows how to relocate data into FLASH (used linker command file * is MPC5675K_my_sections.lcf and MPC5675K_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * ------------------------------------------------------------------------------ * Test HW: MPC5675KEVB * MCU: PPC5675KFMMSJ in Lock-Step mode * Fsys: 180/150 MHz CORE_CLK * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default ********************************************************************************

* Version: 1.1 * Date: Sep-22-2021 * Classification: General Business Information * Brief: This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 ******************************************************************************** ******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version 1.1 Sep-22-2021 b21190(Vlna Peter) FCCU fault reading