******************************************************************************** * Detailed Description: * Example configures Sigma_Delta ADC and periodically converts ANA0_SDA0 input * (EVB's potentiometer can be connected i.e. J53-1 --> PO15) and displays * results in the terminal window (USBtoUART bridge J21). Terminal settings is * 19200-8-no parity-1 stop bit-no flow control on eSCI_A. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  eSCI_A is USBtoUART bridge (connector J21) * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PO15 (header P22) * ********************************************************************************

********************************************************************************  Detailed Description:  Example created as new Application project, see readme.txt for steps to do.  The purpose of this demo application is to show you the usage of the FlexCAN module  using the S32 SDK API and FreeRTOS.  In the first part, the application will setup the board clocks and pins.  Then it will configure the FlexCAN module features such as Bitrate and Message buffers  It will then create two FreeRTOS tasks, one for receiving frames and one for sending frames.  The two user buttons are used to send std message ID=0x1h with 1byte payload as 1 or 0.  Based on received std message with ID=0x2h to LEDs are toggled upon data0 byte.  Use external 12V to power a board.  Connect board with PCAN-USB to display send message and be able to receive some on DEVKIT  ------------------------------------------------------------------------------  Test HW: DEVKIT-MPC5748G rev.D1  Maskset: 0N78S  Target : FLASH  Fsys: 160 MHz PLL  Debugger: S32DS ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq. * DSPI_A is configured as master, DSPI_B is configured as slave. * DSPI modules are connected together by wires on EVB. * Four DMA descriptors are initialized: * - master transmit * - master receive * - slave transmit * - slave receive * All transfers are done by DMA, master sends/receives 8 words and slave * receives/sends 8 words. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * EVB connection:  PCSA0 (J29-1) -> PCSB0 (J30-1) *                  SIN_A (J29-7) -> SOUT_B (J30-8) *                  SOUT_A (J29-8) -> SIN_B (J30-7) *                  SCK_A (J29-9) -> SCK_B (J30-9) * ********************************************************************************

******************************************************************************** * Detailed Description: * ECSM Error Generation Register EEGR is used to generate a non-correctable ECC * error in RAM. The bad data is accessed then, so the IVOR1 exception is * generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can select particular ME/EE setup by * comment/uncomment of particular function calls. * * ------------------------------------------------------------------------------ * Test HW:        XPC563MKIT * MCU:            PPC5633MMLQ80 * Fsys:           80/60/40/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

This excel tool simplifies setting of PLL on MPC55xx/56xx devices. First select device and define input/output frequency. Possible configurations are calculated and basic PLL init code is generated as well. NOTE: macro has to be enabled! BR, Petr

******************************************************************************** * Detailed Description: * Initializes eQADC module and cyclically converts chosen channel, displaying * it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  For ADC: J53-1 (EVB pot's wiper) --> PW7  - ANB16 *                                                       PW8  - ANB17 *                                                       PW9  - ANB18 *                                                       PW10 - ANB19 ********************************************************************************

******************************************************************************** * Detailed Description: * * Configure the device to wake up by STM_0 timer. * Configure the device to enter STANDBY mode from DRUN * Once the device is woken up by STM_0, the device is restared becase * we wrote address of entry point to register MC_ME.CADDR[1].R * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            Default * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user must choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5643L architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0/TSENS1 are read from Test flash and * eQADC is set to measure Vbg and TSENS outputs. eQADC calibration is also done. * Calculated internal temperature can be displayed on the Terminal. * * See results on PC terminal (19200, 8N1, None). You should see following text * (with different values for sure) * *    TSENS0/TSENS1 temperature measurement *     press any key to continue... * *    Calibration constants read from TSENS registers * *    TSENS0                           TSENS1 * *    TSCA_0 = 207                     TSCA_1 = 148 *    TSCB_0 = 7                       TSCB_1 = 19 * *    T = (232 + TSCA * 2^-6) * TSENS_CODE_T / VBG_CODE_T - (273 + TSCB * 2^-4) [degC] * *    VBG_CODE_T   =  997 *    TSENS0_CODE_T = 1325             TSENS1_CODE_T = 1332 * *    TSENS0 temp = 39.19 degC         TSENS1 temp = 38.86 degC * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  use USB connector (J21) on minimodule * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_1 transmits a message. MCAN_2 receives the message. * * MCAN_1 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_2 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 1-2 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * ------------------------------------------------------------------------------ * Test HW:  MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset:  0N78H * Target :  internal_FLASH * Fsys:     600 MHz PLL1 with 40 MHz crystal reference, *        core2 at 200MHz generated from PPL1 * Terminal: None ******************************************************************************** Revision History: 1.0     Jan-5-2017     PetrS    Initial Version of MCAN example *******************************************************************************/

******************************************************************************** * Detailed Description: * This example shows how to use FCCU module for fake fault injection in order to test FCCU functionality. * * For closer details on how FCCU works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The FCCU_Fake_fault_inject function is setting and injecting FCCU fault NCF[7] - STCU2 fault condition. * Short reset is triggered as soon as FCCU registers injected fault. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is disabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. After data are * received, interrupt for each module is handled and data are saved to global * variables. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  P18.0 to P18.5 (CS_0) *                    P18.2 to P18.7 (SCK) *                    P18.3 to P18.9 (SIN - SOUT) *                    P18.4 to P18.8 (SOUT - SIN) * * ********************************************************************************

******************************************************************************** Detailed Description: Example shows configuration of SIUL External interrupts using SDK driver. EIRQ0 (PA3) and EIRQ11 (PE12) are configured for detecting rising edge. Those pins are connected to switches SW1 and SW2 on DEVKIT board. EIRQ1 (PA6) is configured for detecting falling edge. Within its interrupt routines a LEDs are toggled upon edge detecting. See PinSetting component for pins configuration within "Routing" and "Functionals Properties" tabs. To see falling edge on PA6 just connect pin (J2.1) to GND shortly. * ------------------------------------------------------------------------------ * Test HW:         DEVKIT-MPC5748G * MCU:             PPC5748GSMKU6 0N78S * Target:          Debug_FLASH * EVB connection: * Compiler:        S32DS.POWER.2017.R1 * SDK release:     S32_SDK_S32PA_BETA_2.9.0 * Debugger:        S32DS, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date        Author       Description of Changes 0.1 Jun-13-2019 Petr Stancik Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * ADC end of conversion event is triggering DMA transfer which automatically * moves ADC measurement results of ADC_1 channel_0 into buffer ADC_reseult. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0     Mar-11-2015     b21190(Vlna Peter)  Initial Version 1.1    Feb-21-2017     b21190(Vlna Peter)  ADC triggering DMA *******************************************************************************/

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master *   - sends Header *   - either transmits a data to LIN Slave or receives data from a LIN Slave *   - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave *   - receives header from a LIN Master *   - either receives data from a LIN Master or transmits a data to Master *   - filter is enabled *   - TX interrupt is used to prepare data to send and *   - RX interrupt to read received data * * EVB connection: * *   LIN1 circuitry *   connect 12V to LIN1-VSUP, so connect J23.1 to P11.3 *   J13, J12 jumpers placed * *   LIN0 circuitry *   remove J11 * *   connect LIN1 to LIN0, so connect P11 to P9 *   if do not have desired cable, connect P11.3-P9.3 and P11.4-P9.4 * *   See LIN signal on P11.4 or P9.4. * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates basic functionality of SARADC (10-bit ADC0 and 12-bit ADC1) in one-shot conversion mode. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Mar-10-2016    b21190(Vlna Peter)  Added ADC driver *******************************************************************************/

In the attachment you may find System Input / Output Pin Definition for MPC5744P (as it is common to be a embedded attachment with other MPC57xx devices). Preliminary version for next RM release

******************************************************************************** * Detailed Description: * Example demonstates Shifted PWM generating via eMIOS. * The shift is 25% duty cycle. * ------------------------------------------------------------------------------ * Test HW:  MPC5644A + XPC564A minimodule + XPC56XX mother board * Maskset:  OM14X * Target :  Internal Flash * Fsys:     16MHz IRC * * EVB settings: * PJ8 pin 0 is eMIOS CH[0] * PJ8 pin 2 is eMIOS CH[2] ******************************************************************************** Revision History: 1.0     Jun-23-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * MPU is initialized to cover all resources (flash, RAM, peripheral bridges). * All masters are allowed to read-write-execute from all resources. * * Simple test case is used to check the behavior of MPU in case of access * violation: * - the MPU is reconfigured to disable write access to first 1KB or RAM memory *   (0x4000_0000 - 0x4000_03FF). * - if we write this RAM area, machine check exception is triggered * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Fsys:            264MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * ********************************************************************************