* Version: 1.1
* Date: Sep-22-2021
* Classification: General Business Information
* Brief: This example content a basic PMPLL initialization and
* configuration of Mode Entry module and Clock Generation
* module. By default active is core 2 -> e200z4
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* Detailed Description:
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* Test HW: MPC57xx + S32R274RRUEVB
* Maskset: 1N58R
* Target : internal_FLASH
* Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4
*
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Revision History:
1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version
1.1 Sep-22-2021 b21190(Vlna Peter) FCCU fault reading
