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* Detailed Description:
* Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC
* error in FlexCAN RAM (user must choose it in the option at the end of
* main function).
* Example configures FlexCAN module, initializes ECC for all FlexCAN RAMs, then
* it injects ECC error to the Message Buffer 9.
* When corrupted data is accessed the IVOR1 exception handler is called in case
* of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt
* handler is called in case of single-bit ECC error (FCCU interrupt occurs).
* Both function calls MEMU handler.
* Reported FlexCAN ECC error address is corrected according RM, section 7.12.2.3
* The example displays notices in the terminal window (connector J19 on
* MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A).
* No other external connection is required.
* ------------------------------------------------------------------------------
* Test HW: MPC57xx_Motherboard + MPC5744P-144DC
* MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B
* Fsys: 200 MHz PLL with 40 MHz crystal reference
* Debugger: Lauterbach Trace32
* Target: internal_FLASH, RAM
* Terminal: 19200-8-no parity-1 stop bit-no flow control
* EVB connection: default
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