******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5604P, SPC5604P * Maskset:  0M36W * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference in RUN0. IRC in DRUN * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_0 module transmits a message out of the board.   I/O configuration for the TRK-MPC5604P CAN example:   MCU_PB0 -> SBC_TXD  (MPC5604P CAN0TX PCR[16] ALT1 function) MCU_PB1 <- SBC_RXD  (MPC5604P CAN0RX PCR[17] input function)   SPI bus between the MCU and SBC:   MCU_PC4 -> SBC_!CS    (MPC5604P DSPI_0 CS0  ALT1 function PCR[36]) MCU_PC5 -> SBC_CLK    (MPC5604P DSPI_0 SCK  ALT1 function PCR[37]) MCU_PC6 -> SBC_MOSI   (MPC5604P DSPI_0 SOUT ALT1 function PCR[38]) MCU_PC7 <- SBC_MISO   (MPC5604P DSPI_0 SIN  input function PCR[39])  * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use PIT module for triggering interrupts on its timeout. * * This example shows how to use PIT module for triggering interrupts on its timeout. * For closer details on how PIT works I suggest you to check reference manual as this is quite simple timer. * This example sets PIT timer0 channel0 for 5000000 cycles. * As soon as it exceeds the interrupt is triggered. * Pin state is toggling in ISR * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5744P device.                  Follow these steps                  Note: Macros have to be enabled!                  1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.                 - put values into cells B11, Q10 and Q17 of the "Clocks" sheet                 - check if it is Valid or Invalid                 - "PLLconfig" sheet shows possible PLLs configurations                  2. Configure System and AUX clock selectors and its Dividers                 - check calculated frequency of System/Peripheral clocks                 - if Invalid change source clock and Divider value to keep Max freq                    3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * * CAN0 module is configured to transmit one message with ID 0x555 to CAN1 * module. CAN1 module is configured to use DMA to receive the message. * Once the DMA module reads the received frame, interrupt is triggered. * Follow application note AN4830 regarding the CAN settings. * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830.pdf * http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830SW.zip * The example from AN4830 is modified to use DMA and RXFIFO on CAN1 module. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

This config tool simplifies PLL setting calculation and clock configuration for MPC5777C device. Version 1.3 added option to select between 264/300 MHz MCU versions.                 Follow these steps                 Note: Macros have to be enabled!                 1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.      - put values into cells B14, Q13 and Q20 of the "Clocks" sheet      - check if it is Valid or Invalid      - "PLLconfig" sheet shows possible PLLs configurations                   2. Configure System and AUX clock selectors and its Dividers      - check calculated frequency of System/Peripheral clocks      - if Invalid change source clock and Divider value to keep Max freq                 3. Copy generated code by pressing "Copy Code" button

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test is performed in this example: after initialization, SMPU_1 * configuration is changed to disable write access to last 4kB of RAM for * Process ID 1. Write acess is allowed for Process ID 0. * If this area is written by CPU while the Process ID is 1, exception will * occur due to access violation. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 0 and * displays results into terminal window by interrupt service routine. Analog * input AN[0] requires external connection to converted voltage (potentiometer). * ------------------------------------------------------------------------------ * Test HW:        MPC5554EVB * MCU:            MPC5554MVR132 * Fsys:           132/112/80/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: USER_DEV pin RV2(i.e. pin8) -> pin B7 on I/O header ring *                 (potentiometer RV2 to analog input AN[0])   * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows possible implementation of frequency and duty cycle * measurement with the help of eMIOS module. * Two eMIOS channels are used and set to IPWM and IPM modes. The first channel * measures the positive pulse width and the second channel measures the period. * * EVB connection: * PJ7.5 to PJ7.6 ... connect external pulse signal to this * * See result on PC terminal (9600, 8N1) * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************     BR, Petr

This session will explain how Freescale can enable customers to develop 76-81 GHz short and long range radar applications using the MPC577xK MCU, it will explain the concepts of the radar algorithms, including practical aspects such as SDADC or MIPI CSI sampling, Chirp Generation, Data Compression, R,V FFT, Detection and Tracking algorithms, and the benefits of the new Freescale IP that can allow them to improve their system resolution and accuracy. In this session customers will take away a detailed understanding of how to develop fast modulation radar systems using the MPC577xK MCU including the BOM cost advantages it also brings.

******************************************************************************** * Detailed Description: * Used flash driver:  MPC5700 C55FG Flash Standard Software Driver (REV 1.1.0) * http://www.nxp.com/files/product/software/C55_JDP_SSD.exe * * This example checks four large 256KB flash blocks at address 0x0100_0000 - * 0x010F_FFFF. * Some random data are placed to this section (constant "flash_data[]"), so the * s-record is not empty. * It is necessary to use off-line MISR_C55.exe tool which calculates MISR * values for selected flash blocks. See the "MISR gen" folder included in this * project. File "core0.run" is s-record file which is used for calculation. It * contains the data (constant "flash_data[]") placed to the selected blocks. * "misr.bat" file shows how to call the calculator. * "output.txt" contains the result of this operation - the MISR values. * Once this is done, initialize the SSD drivers, unlock blocks which are going * to be checked and run the FlashArrayIntegrityCheck function. * Notice that the code must be executed from RAM. We cannot access the flash * during this operation. If the operation is successful, FlashCheckStatus will * return opResult C55_OK if the MISR values are equal. It will return * C55_ERROR_MISMATCH if the MISR values are not equal, i.e. the flash is * corrupted and the content does not correspond to s-record file. * ------------------------------------------------------------------------------ * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to reprogram the shadow flash. * * It is highly recommended to read application note "Preventing Device Lockout * via Censorship on MPC55xx and MPC563x Families" * http://www.freescale.com/files/32bit/doc/app_note/AN3787.pdf * * This examples erases the shadow flash, then it restores censorship information * and then NVUSRO nonvolatile register is reprogrammed to disable the watchdog. * The watchdog is disabled by clearing of bit WATCHDOG_EN in NVUSRO. It ensures * that watchdog is disabled automatically during startup of MCU. * Watchdog can be also disabled by software (shown in the code). * * It is important to execute the code from RAM memory because Read-While-Write * is not supported here. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 144LQFP, SPC5604B, silicon mask set 2M27V * Target :  internal_FLASH, RAM * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection: * * It is necessary to remove both J32 jumpers and also both J35 jumpers. * * Connect J32.2 to PC9 (CAN_0 TX) * Connect J32.4 to PC8 (CAN_0 RX) * * Connect J35.2 to PE5 (CAN_1 TX) * Connect J35.4 to PG14 (CAN_1 RX) * * Connect CAN P5.2 to CAN2 P4.2 (CAN_0 and CAN_1 CANL) * Connect CAN P5.1 to CAN2 P4.1 (CAN_0 and CAN_1 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

This document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for MPC57xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. This scripting tool consist of 136 scripts for Lauterbach debugger. It helps user to quickly debug micro without need of reference manual. Here is and example of windows that user can use (detailed description can be found in user guide):

The example does exactly the same operation like this example: https://community.freescale.com/docs/DOC-105380 ...but SSD flash driver is used now.   ******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * Used SSD flash drivers: * http://www.freescale.com/files/product/software/C55_JDP_SSD.exe * Version of the driver is v1.0.0 * ------------------------------------------------------------------------------ * Test HW:    X - PC5748G - MB (rev C) * MCU:        PPC5748GMMN6A * Maskset:    1N81M * Fsys:       160 MHz * Debugger:   Lauterbach Trace32 *              * Target:     Internal_FLASH * ********************************************************************************

Document describes possible reasons of result swap in eQADC's result FIFO and how to avoid it. Very preliminary version!

******************************************************************************** * Detailed Description: * * Simple LINFlex UART mode transmit and receive without interrupts (polled UART) * TXFIFO and RXFIFO macro is used to select between buffer and FIFO mode * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * Enable external interrupt on pin PA[3]. * If falling edge is detected, interrupt is triggered and LED1 on PE[4] is * toggled. * * Connect external signal to PA[3] or connect push button by wire. * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5606B, SPC5606B 0N32E * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL with 8 MHz crystal reference * ********************************************************************************

This excel tool helps to configure Core MPU on MPC57xx devices. It generates asm code and also command for Lauterbach debugger for selected configuration of MPU entry.