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* Detailed Description:
*
* CAN0 module is configured to transmit one message with ID 0x555 to CAN1
* module. CAN1 module is configured to use DMA to receive the message.
* Once the DMA module reads the received frame, interrupt is triggered.
* Follow application note AN4830 regarding the CAN settings.
* http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830.pdf
* http://www.freescale.com/files/microcontrollers/doc/app_note/AN4830SW.zip
* The example from AN4830 is modified to use DMA and RXFIFO on CAN1 module.
*
* ------------------------------------------------------------------------------
* Test HW: MPC57xx
* Maskset: 1N81M
* Target : SRAM
* Fsys: 160 MHz PLL
*
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