******************************************************************************** * Detailed Description: * * eQADC mode: Continuous scan with external trigger. * Periodic trigger from eMIOS_0 ch16. * ANA ch5 is converted and result is sent to RFIFO0. * * eMIOS ch0 duty cycle is modified based on result data, so LED is dimming * if connected to eMIOS ch0 output. * * ADC result is also displayed on terminal each second. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * *           eMIOS ch0 (PortG P14-16)--> USER_LED_4 (P7-4) *                  ANA0       (PortQ P24-5) --> RV1 (J53.1) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter. * * DMA is used to read CAPT1/2 registers and form 32bit values used in calculation. * * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrate DMA transfer triggered by eTimer module compare * event CMPLD1 load into COMP1. Used is eTimer_0 channel_5. * It is necessary to configure DREQ[x] register according to channel_5 of * eTimer_0. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  0N89D * Target :  SRAM * Fsys:     120 MHz PLL * ******************************************************************************** Revision History: 1.0     Apr-08-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

This document gives a basic insight into bit timings relationship and provide easy step-by-step guide to calculate CAN bit timing parameters for desired baudrate.

******************************************************************************** * Detailed Description: * This example content a driver for CGM module configuration. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed * frequency * * * Mode transition to LPU_STOP is executed. CAN_0 is configured to wake up from *  LPU_STOP to LPU_RUN using message with standard IDE = 0 as a wake up *  preselected matching criteria. After wake up from LPU_STOP, user *  LED1 is blinking.   * * Modified files: mem.ld, sections.ld, startup.s, added file z2_restart.s * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574xG Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Default * * * ********************************************************************************

******************************************************************************** * Detailed Description: * This example implements ADC driver and demonstrated the usage of ADC in BCTU mode. * When PIT timer exceeds the trigger is sent to BCTU and BCTU triggers ADC_0 conversion. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Mar-10-2016    b21190(Vlna Peter)  Added ADC driver 1.5    Mar-16-2016    b21190(Vlna Peter)  Added BCTU and PIT drivers *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals. * * This example shows, how to use ADC with ETimer to dim LED diode. Voltage on * the output of the trimmer is converted to digital value which is used to * control duty cycle of the PWM generated by ETimer. * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Terminal: * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  UserLED1 connected to P19.4, connected jumper j53 * * * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates basic functionality of SARADC (10-bit ADC0 and 12-bit ADC1) in one-shot conversion mode. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Nov-20-2014    b21190(Vlna Peter)  Added SWT_0 dissabling in startup 1.3    Mar-10-2016    b21190(Vlna Peter)  Fixed clock configuraion for PLL 1.4    Mar-10-2016    b21190(Vlna Peter)  Added ADC driver *******************************************************************************/

With author's permission I am publishing presentation comparing e200 cores to each other and describing them in detail.   Document was created in year 2010, thus it does not deal with cores subsequently used with MPC57xx devices.   Thanks to Robert Moran for his great job.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * Fsys:               600MHz * * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 connected to P8.0, LED2 connected to P8.1 *                  LED3 connected to P8.2 * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then what's generate IVOR1 * exception or FCCU_Alarm_Interrupt. Both function calls MEMU handler. * Example also offers useful macros for MEMU module. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals. * * This example shows, how to use some of ETimer modes. Channel 0 is set to * Fixed-Frequency PWM Mode and generates PWM signal with approximate frequency * 507Hz. This signal is routed to the UserLED1. * * Channel 1 is set to Count mode and generates 0,25 second interrupt. * In the interrupt service routine, duty cycle is increased from 0% to 100% * with step 6.25%. This shows for example, how can be controlled the brightness * of the LED. * * Channel 2 is set to Variable-Frequency PWM Mode and generates PWM signal with * frequency 10KHz. This signal is routed to the UserLED2. * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Terminal: * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  UserLED1 connected to P19.0 *                     UserLED2 connected to P19.2 * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0/TSENS1 are read from Test flash and * eQADC is set to measure Vbg and TSENS outputs. eQADC calibration is also done. * Calculated internal temperature can be displayed on the Terminal. * * See results on PC terminal (19200, 8N1, None). You should see following text * (with different values for sure) * *    TSENS0/TSENS1 temperature measurement *     press any key to continue... * *    Calibration constants read from TSENS registers * *    TSENS0                           TSENS1 * *    TSCA_0 = 207                     TSCA_1 = 148 *    TSCB_0 = 7                       TSCB_1 = 19 * *    T = (232 + TSCA * 2^-6) * TSENS_CODE_T / VBG_CODE_T - (273 + TSCB * 2^-4) [degC] * *    VBG_CODE_T   =  997 *    TSENS0_CODE_T = 1325             TSENS1_CODE_T = 1332 * *    TSENS0 temp = 39.19 degC         TSENS1 temp = 38.86 degC * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  use USB connector (J21) on minimodule * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * LINFlexD_1 configured as Master *   - sends Header *   - either transmits a data to LIN Slave or receives data from a LIN Slave *   - no interrupt is used, just SW pooling * * LINFlexD_0 as Slave *   - receives header from a LIN Master *   - either receives data from a LIN Master or transmits a data to Master *   - filter is enabled *   - TX interrupt is used to prepare data to send and *   - RX interrupt to read received data * * EVB connection: * *   Switches on Motherboard: *   P6.1 to P8.1  ... SW1 to PA0 *   P6.2 to P8.2  ... SW2 to PA1 *   P6.3 to P8.3  ... SW3 to PA2 *   P6.4 to P8.4  ... SW4 to PA3 * *   Unconnect LINFlexD_0 from UART transceiver *   J14 SCI_RX open *   J13 SCI_TX open * *   As only single LIN transceiver is available LINFlex modules are connected *   together before this transceiver in the way TX pins together and RX pins together. *   TX pins must be configured as open drain and use a pullup resistor. * *   P11.15 to P12.8    TX pins *   P11.16 to P12.7    RX pins * *   Connect LINFlexD_1 to LIN transceiver on Motherboard *   J17 - LIN_TX ON *   J16 - LIN_RX ON *   J15 - LIN_EN ON *   P3 1-2 ON ... VSUP to 12V ** *   See LIN signal on P3.3 or J4.4. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: None ******************************************************************************** Revision History: 1.0     Feb-22-2016     PetrS          Initial Version of LIN example *******************************************************************************/ Original Attachment has been moved to: Example-MPC5744P-LINFlex-LIN-Master-Slave-test-v1_0-GHS614.zip

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection: * * It is necessary to remove both J32 jumpers and also both J35 jumpers. * * Connect J32.2 to PC9 (CAN_0 TX) * Connect J32.4 to PC8 (CAN_0 RX) * * Connect J35.2 to PE5 (CAN_1 TX) * Connect J35.4 to PG14 (CAN_1 RX) * * Connect CAN P5.2 to CAN2 P4.2 (CAN_0 and CAN_1 CANL) * Connect CAN P5.1 to CAN2 P4.1 (CAN_0 and CAN_1 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * LINFlex UART mode transmit and receive with interrupts * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  J14.2 to P12.6 Connect LINFlexD_0 RXD to main RS232 *                  J13.2 to P12.7 Connect LINFlexD_0 TXD to main RS232 * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, Setup access right for Masters and Peripherals * on AIPS_0 * * LINFlex UART mode with FIFO transmit using DMA * LINFlex UART mode with FIFO receive using DMA * * ICache and DCache are both disabled in startup file using CACHE_ENABLE macro. * You can change the value of the macro at the following path: * project Properties/C/C++ General/Paths and Symbols/Symbols * If you change the value to 1, ICahce and DCache will be enabled in startup. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  J14.2 to P12.6 Connect LINFlexD_0 RXD to main RS232 *                  J13.2 to P12.7 Connect LINFlexD_0 TXD to main RS232 * ********************************************************************************

******************************************************************************** * Detailed Description: * * Simple LINFlex UART mode transmit and receive without interrupts (polled UART) * TXFIFO and RXFIFO macro is used to select between buffer and FIFO mode * * PIT channel 0 is also used to generate 1sec interrupt where PA0 pin is toggled. * * EVB connection: * *   Motherboard *   J14 - SCI_RX OFF *   J13 - SCI_TX OFF *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). * ------------------------------------------------------------------------------ * Test HW:  MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset:  0N78H * Target :  RAM, internal_FLASH * Fsys:     600 MHz PLL1 with 40 MHz crystal reference, *        core2 at 200MHz generated from PPL1 * Terminal: 19200, 8N1 ********************************************************************************