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* Detailed Description:
* Application performs basic initialization, setup PLL to maximum allowed freq.,
* start one Z7 core, interrupts initialization, ICache and DCache are disabled
* on both cores because of shared memory, which must not be cached.
*
* There is 4K shared memory defined in the linker file. This memory is used by
* both cores. Both cores access into the structure, which is placed in the shared
* memory. This access is marked as a critical section. Only one core can write
* to the structure at the same time. To ensure this, there are Gates, which
* guarantee data coherence during the access. Only one core can be in critical
* section. Second core has to wait, until first core leaves the critical section
*
*
*
* ------------------------------------------------------------------------------
* Test HW: MPC5775K-356DS, MPC57xx Motherboard
* MCU: PPC5775KMMY3B 0N76P
* Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFlexD_0
* Fsys: PLL0 266MHz
* Z4 Core 133MHz
* Z7 Core 266MHz
* Debugger: Lauterbach Trace32
* PeMicro USB-ML-PPCNEXUS
* Target: internal_FLASH (debug mode, release mode)
* EVB connection: default connection
*
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