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MPC5xxx Knowledge Base

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******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. *   * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************
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******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and *  configuration of Mode Entry module and Clock Generation *  module for core1 and start of core0 and core0s from Core_Init function. * Also containts Lauterbach multicore multi-Trace32 view script for multicore * debugging puproses ******************************************************************************** * Test HW:  Test HW:  MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Jun-09-2015     b21190(Vlna Peter)  Initial Version 1.1     Sep-20-2016     b21190(Vlna Peter)  core0+core0s boot function added *******************************************************************************
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******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal FLASH (user must choose it in the option at the end of * main function). * Flash over-programming is used to generate a non-correctable (or single-bit) * ECC error in FLASH. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************
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This excel tool simplifies setting of PLL on MPC55xx/56xx devices. First select device and define input/output frequency. Possible configurations are calculated and basic PLL init code is generated as well. NOTE: macro has to be enabled! BR, Petr
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******************************************************************************** * Detailed Description: * Read attached document "How to use Register Protection on MPC5748G.pdf" * for detailed explanation. * This example shows how to lock and unlock register MC_ME.RUN_MC[3].R. * One option is to write directly to memory via pointers, second option is * to use macros from header file reg_prot.h. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************
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******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test is performed in this example: after initialization, SMPU_1 * configuration is changed to disable write access to last 4kB of RAM for * Process ID 1. Write acess is allowed for Process ID 0. * If this area is written by CPU while the Process ID is 1, exception will * occur due to access violation. * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************
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WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5644A. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describes how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5644A-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code re-programs content of shadow flash to enable censorship. * Succesful operation is confirmed by notices in terminal window on eSCI_A * (19200-8-no parity-1 stop bit-no flow control). * After power-on-reset the device is censored with private password * 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be allowed by enabling * debug of censored device as decipted in attached pdf document. Shadow flash * re-programming code must be executed from internal RAM. * ------------------------------------------------------------------------------   2) MPC5644A-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5644A-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. Programmed password is 0xFEED_FACE_CAFE_BEEF. * MPC5644A_run_from_ram.cmm script does it by command * SYStem.option.keycode 0xFEEDFACECAFEBEEF. * Then run this code to uncensor the device. Succesful operation is confirmed by * notices in terminal window on eSCI_A (19200-8-no parity-1 stop bit-no flow * control). After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------
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******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:         This example demonstrate SWT functionality *                   On SWT timeout it sent signal to FCCU where is short *                   functional reset reaction on SWT timeout configured *                   FCCU then sent signal to RGM module which triggers short *                   functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-24-2015       b21190(Vlna Peter)  Added SWT short reset *******************************************************************************/
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******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:        This example demonstrate SWT functionality *                 On SWT timeout it sent signal to FCCU where is long *                 functional reset reaction on SWT timeout configured *                 FCCU then sent signal to RGM module which triggers long *                 functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1     Mar-24-2015    b21190(Vlna Peter)  Added SWT long reset *******************************************************************************/
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******************************************************************************** * Detailed Description: * This example shows, how to initialize FlexCAN modules for simple transmission * and reception using RX interrupt. Both modules are configured for 100kbit/s * bit rate. CAN_0 module transmits message using MB0. CAN_1 module receives * message using interrupt via MB0. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574XG - Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Connect jumpers J15 and J16 on motherboard *                    Connect P14 H to P15 H *                    Connect P14 L to P15 L * ********************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed frequency (48MHz) * Setup SIU, and demonstrate frequency modulation. * ------------------------------------------------------------------------------ * Test HW:        XPC560B 64LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             SPC5602D * Cut:               1M18Y * Fsys:             48 MHz * Debugger:     Lauterbach Trace32 * Target:           internal_FLASH * EVB clkout pin : Port J7 - pin 0 * ********************************************************************************
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******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is disabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************
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WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5604B. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describing how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5604B-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code reprogram content of shadow flash to enable censorship. * After succesful operation LED1 is lighting. After power-on-reset the device * is censored with private 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be * allowed by enabling debug of censored device as decipted in attached pdf * document. On this device password must be entered in reverse order i.e. * 0xCAFE_BEEF_FEED_FACE. Shadow flash re-programming code must be executed from * internal RAM. * ------------------------------------------------------------------------------   2) MPC5604B-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5604B-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. On this device password must be entered in reverse * order i.e.0xCAFE_BEEF_FEED_FACE. MPC5604B_run_from_ram.cmm script does it by * command SYStem.option.keycode 0xCAFEBEEFFEEDFACE. * Then run this code to uncensor the device. After succesful operation LED1 is * lighting. After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------
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******************************************************************************** * Detailed Description: * * Configure the device to wake up by STM_0 timer. * Configure the device to enter STANDBY mode from DRUN * Once the device is woken up by STM_0, the device is restared becase * we wrote address of entry point to register MC_ME.CADDR[1].R * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            Default * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************
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******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************
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******************************************************************************** * Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT0 interrupt and external interrupt source 1 are implemented. PIT interrupt * toggle LED every second, external interrupt causes IVOR1 exception. * * This example also shows, how to use exceptions, while HW vector mode is used. * After SW1 button is pressed, uninitialized RAM is read and IVOR1 exception is * reached. In IVOR1, only endless loop is implemented and micro has to be reset * externally if you want to get out from this loop. * * * For correct HW vector mode setup, following files was added to the project: * *  - exceptions.s *  - handlers_vle.s *  - HW_vector.c * * * Following files was modified (all changes are marked by comment): * *  - mem.ld *  - sections.ld *  - Vector.c *  - MPC57xx__Interrupt_Init.c * * *  Following files was removed from project (files are still place in project, but *  not compiled and linked) * *  - intc_sw_handlers.S *  - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW:         X-MPC5744P-144DC, MPC57xx motherboard * MCU:             PPC5744PFMLQ8 0N15P * Fsys:            200 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), *                    User switch SW1 connected to A1 (P8.1) * * * ------------------------------------------------------------------------------ * ********************************************************************************
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******************************************************************************** * Detailed Description: * Example demonstates Shifted PWM generating via eMIOS. * The shift is 25% duty cycle. * ------------------------------------------------------------------------------ * Test HW:  MPC5644A + XPC564A minimodule + XPC56XX mother board * Maskset:  OM14X * Target :  Internal Flash * Fsys:     16MHz IRC * * EVB settings: * PJ8 pin 0 is eMIOS CH[0] * PJ8 pin 2 is eMIOS CH[2] ******************************************************************************** Revision History: 1.0     Jun-23-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/
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******************************************************************************** * Detailed Description: * Example configures LinFlex and eDMA modules and then periodically sends notice * to the terminal window (19200-8-no parity-1 stop bit-no flow control). * * ------------------------------------------------------------------------------ * Test HW:         MPC5607BEVB * Target :         internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * Fsys:            40 MHz PLL with 8 MHz crystal reference * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, third LED by second core, initializes and display notice via UART * terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, PPC5646C 0M87Y silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************
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This excel tool helps to configure MMU on e200z cores. It generates asm code and also command for Lauterbach debugger for selected configuration of TLB entry.
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