S32K知识库

讨论

******************************************************************************************** * Detailed Description: * LPIT_ch0 triggers DMA_ch0 periodically (1ms). * Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO. * There are 8 minor loops per one major loop (64 bytes in 8ms). * LPSPI1 sends two 32bit frames every 1ms. * LPSPI1 RX data are masked, they are not stored in the RX FIFO. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144 0N57U * Debugger: S32DS 2.2, OpenSDA * Target: internal_FLASH ********************************************************************************************

******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************

************************************************************************************************ Detailed Description: WDOG tested in SystemInit() function (system_S32K116.c) after POR. For debugging purposes: - WDOG counter reference clock is pre-scaled to slow the test (CS_PRES = 1). - During CNT_LOW test, BLUE LED (PTE8) ON. - During CNT_HIGH test, RED LED (PTD16) ON. - Once both tests have passed, GREEN LED (PTD15) ON. If either of the test fails, WDOG will stay in its default configuration and rest the MCU. ---------------------------------------------------------------------------------------------------------------- Test HW: S32K116EVB-Q048 REV.B MCU: S32K116 0N96V Debugger: S32DSR1, OpenSDA Target: internal_FLASH ************************************************************************************************

****************************************************************************************************************** Detailed Description: The example code shows CMP in Round-robin mode. CMP is clocked (125kHz) and triggered (80ms) by LPTMR, operates in VLPS. Input channels are CMP0_IN1 (PTA1), CMP0_IN2 (PTC4), CMP0_IN3 (PTE8), CMP0_IN4 (PTC3). The initial state of CMP outputs is 0 (Input analog pins < DAC input (Vin1/2)) The input pins are pulled down internally for debugging purposes. CPM will wake up the MCU if an input has changed. BLUE LED flashes 1x if CMP_IN1 has changed, 2x CMP0_IN2, 3x CMP0_IN3, 4x CMP0_IN4. After that, the MCU goes back to VLPS. ------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100X MCU: S32K144 (0N47T) Debugger: S32DS2.0, OpenSDA Target: internal_FLASH ******************************************************************************************************************

**************************************************************************************************** * Detailed Description: * This example uses BIST and EMCEM drivers from SPD 1.0.6. * BIST and EMCEM can be enabled or disabled using macros. * * BIST runs immediately after a power-on reset and triggers an ST_DONE reset. * EMCEM initialization is only possible after a system reset without an attached debugger. * Therefore, wait loops (controlled by macros) are used to manage execution flow * for both BIST and EMCEM. * * Fault injection is selected via macros: * - FAULT_EMCEM_DCM_NCF_1_AD_EDC_ERR_OUT → handled via NMI * - FAULT_EMCEM_DCM_NCF_2_PRAM1_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_2_ITCM_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_3_PFO_CODE_ERR → FCCU alarm → (if TIMEOUT_PFO_CODE_ERR) → NMI * - FAULT_EMCEM_DCM_NCF_5_STCU_NCF → handled via FCCU alarm * - FAULT_EMCEM_DCM_NCF_7_SW_NCF_0 → FOSU Destructive reset * (read resetReason after reset, MCU_FCCU_FTR_RESET). * FOSU triggers as no FCCU reaction is configured for NCF_7 * while FCCU is enabled and reactions are configured for other faults. * * ------------------------------------------------------------------------------------------------ * MCU: S32K3x4EVB-Q257 * Fsys: 160 MHz PLL with 16 MHz crystal reference * Debugger: Lauterbach Trace32, S32DS IDE 3.6.5 * Target: internal_FLASH ****************************************************************************************************

/********************************************************************************************** * File main.c * Owner Daniel Martynek * Version 1.0 * Date May-12-2026 * Classification General Business Information ********************************************************************************************** * Detailed Description: * The code enables the data cache, reads a value from DFlash to load it into the cache, * then uses the LMEM interface to inspect and directly overwrite the corresponding cache line. * Finally, it reads the same address again through the CPU, which returns the modified value * from the cache instead of the original data stored in DFlash. * * In this simple setup, where only the data cache is enabled, the code executes from PFlash, * and the accessed data is located in DFlas — the cache line is unlikely to be re-evaluated. * Therefore, the CPU may consistently return the modified value - this behavior is not guaranteed. * ------------------------------------------------------------------------------------- * MCU: S32K142 * Fsys: 48MHz, FIRC * RTD: S32K1_RTD_3_0_0_QLP06_D2603_ASR_REL_4_7_REV_0000_20260320 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************

The attached spreadsheet provides mapping between EIM and DCM faults for the S32K3x1, S32K3x2, S32K344, S32K324, and S32K314 devices. Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K344 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions. * * Configuration: * - Updated pin configuration * - Modified FXOSC, PLLAUX + dividers * - Platform: added EMAC_0_IRQn interrupt * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Added DIO * * main.c * - Updated only the header * device.c * - No updates * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: MR-CANHUBK344 * MCU: S32K344 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: EMAC <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected to enable an external debugger. * * TJA1103-SDBR: * mode rev-RMII * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 1-2 * * Configuration: * - Updated pin configuration * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC1_SABRE <-> TJA1103-SDBR (rev-RMII mode) <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1120-SDBR: * mode RGMII-ID (both TXC/RXC), Master, Autonomous, XTAL * CONFIG 3 2-3 * CONFIG 5 1-2 * CONFIG 4,6 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1120-SDBR <-> Media converter TE-1402 (1G, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1103-SDBR: * mode RGMII-ID (both TXC/RXC) * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 100M * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1103-SDBR <-> Media converter TE-1402 (100M, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K388 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions except: jumper J361 must be closed. * - Soldering rework required to connect an external debugger. * See S32K388EVB-Q289_HW_User Manual_A3.pdf, chapter 15 (Errata). * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMACx clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K388_gptp_ds, S32K3xx gPTP Stack 1.0.0) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * --------------------------------------------------------------------------------------- * Test HW: S32K388EVB-Q289 SCH-88925 REV A, 700-88925 REV X1 * MCU: S32K388 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

**************************************************************************************************** * Detailed Description: * * The Flexio I2C driver provides an optional configuration parameter for reducing the number of DMA interrupts * required for transmission that are configured with DMA Optimize option. Instead of being interrupted after each * end of transmitting or receiving a data block or data amount larger than 13 bytes, only one interrupt will be raised to * stop frame and inform to user that the transmission was done. * * More details can be found in "RTD_I2C_UM.pdf", the chapter 3.6.3 FLEXIO DMA Optimize. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 SCH-53148 REV B2 * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Connections： * FXIO_D10_SCL (J4.19) - LPI2C1_SCL (J3.24) * FXIO_D11_SDA (J4.17) - LPI2C1_SDA (J3.27) ***************************************************************************************************/ Test Result:

******************************************************************************************** * Test HW: S32K312 EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.6.2 * SDK release: RTD 6.0.0 QLP04 * Debugger: PE Micro * Target: Internal_FLASH ******************************************************************************************** The objective of this demo application is to generate an interrupt and wakeup using the single GPIO. In this application, USR_SW5 (PTB26) in S32K312_Q172 EVB is used both as an interrupt source in RUN mode and as a wake‑up source from STANDBY mode. Thanks & regards, Krishnakumar V

This example project will show user how to use and configure the basic functionalities of WKPU + GPT RTC API. ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) or S32K344MINI-EVB * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH ------------------------------------------------------------------------------ This example routine configures the WKPU & RTC units for wake-up. The RTC is present in always ON domain, hence available in RUN mode as well as in STANDBY mode. The chip contains one instance of RTC (Real Time Clock) timer and API (Autonomous Periodic Interrupt) timer, where both can perform 32-bit comparisons. Both RTC and API timers can generate interrupts as well as wake-up from low power modes. The following figure highlights the path for RTC API wake-up. Please refer to Chapter 69.3.2 API functional description from the S32K3XX reference manual (Rev. 12) for further information. The routine waits for SW5 to be pressed, then: Turns off the green LED Switches CORE_CLK to Option C - Boot Standby mode (CORE_CLK @ 24 MHz). Initializes the ICU driver. Configures RTC_API channel (WKPU0) Initializes GPT module. Starts timer and sets RTC_API_TIME. Enters standby. After the period defined, RTC API generates an interruption and MCU wakes up. After wake-up, MCU resets and polls for SW5 to be pressed again. The RTC API value can be changed with RTC_API_TIME definition. This example is provided as is with no guarantees and no support.

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K344 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions * * Configuration: * - Updated pin configuration * - Updated clock configuration * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Added DIO * * main.c * - Updated only the header * device.c * - No changes * test.c * - Commented out the code that shuts down the TCP/IP stack after * its predefined timeout * - Added LED task * * ----------------------------------------------------------------------------- * Test HW: S32K344MINI-EVB SCH-94921 REV B, 700-94921 REV B * MCU: S32K344 * Debugger: On Board * Target: internal_FLASH * EVB connection: EMAC <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected * to enable an external debugger. * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMAC0 clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K389_gptp_ds, SW32K3xx_M7_gPTP_1.1.0_CD01_D2602) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ----------------------------------------------------------------------------- * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> * <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

S32K1 vdd falling low voltage POR clear situation 1. Abstract This document primarily aims to explain the situation where the POR flag in the RCM_SSRS of the S32K1 chip is cleared, and to explain the setting status of the reset pin and the POR and LVD bits when VDD is powered down. This article is written because some customers, when using the RCM_SSRS reset flag to determine the corresponding RAM initialization conditions, have made incomplete considerations, leading to component failures in actual projects. They mistakenly believe that as long as the SSRS POR flag is not cleared by software writing a 1 after power-on, the POR bit will remain indefinitely. In reality, even after power-on, if subsequent power fluctuations cause VDD to drop to LVD/LVR and trigger a reset, the POR flag may still be automatically cleared by the chip. 2. Document content This article mainly categorizes VDD power-down scenarios into three main types: (1) VDD drops below the minimum LVR value but above VPOR, and then power is back to normal VDD. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. (2) VDD drops below LVD, above LVR, and LVDRE=0. In this case, reset flag POR=1 and LVD=1 in RCM_SSRS. (3) VDD drops below LVD, above LVR, and LVDRE=1. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. The schematic diagram is as follows: 3. Test result on S32K116 board

特色文章

The S32K3 family of 32-bit AEC-Q100 qualified MCUs combines a scalable family of Arm® Cortex-M7-based microcontrollers built on long-lasting features with a comprehensive suite of production-grade tools. S32K3 MCUs are included in NXP’s Product Longevity Program, guaranteeing a minimum of 15 years of assured supply. The S32K3 offers dedicated peripherals set for rapid motor control loop implementation: enhanced Modular IO Subsystem(eMIOS), Logic Control Unit (LCU), TRGMUX, BodyCross-triggering Unit (BCTU), Analog to Digital Converter(ADC), and Analog Comparator (CMP). The comprehensive motor control ecosystem based on Automotive Math and Motor Control Library(AMMCLib) set, FreeMASTER with Motor Control ApplicationTuning (MCAT) tool and Model-Based Design Toolbox (MBDT) helps to enable S32K3 MCU in wide range of motor control use cases. The table below points to the articles with more detailed description each of S32K3 motor control use cases, hardware description, links to appropriate application notes and their addendums, and software repositories. Device HW Article S32K344 MCSPTE1AK344 12 V development kit engineered for 3-phase PMSM and BLDC motor control applications FOC with dual shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with dual shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API. FOC with single shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with single shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The single shunt current measurement is advanced technique that allows decrese the cost of Bill of Material (BOM). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API. FOC integrated with FreeRTOS Article focuses on integration of motor control software (based on FOC with dual shunt current measurement) and Real Time Operating System (FreeRTOS). The available example code is based ANSI-C code and uses RTD drivers with low-level non-Autosar API. Six-step commutation control. Article focuses on solution based Six-step commutation (6-step) technique (typically used for 3-phase BLDC motors) with Hall position sensor and without any position sensor (sensorless). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with low-level non-Autosar API. Note: the list of use cases cannot cover all combinations of MCU, current measurement scenario, control technique and sensor inputs, but should work as a base reference for most common configurations. This list is not final, please follow this acticle to be notified about updates with new use cases.

S32K知识库

S32K Knowledge Base

讨论

Example S32K144 LPIT DMA LPSPI

Example S32K144 WDOG RCM interrupt

Example S32K116 WDOG Fast Test

Example S32K144 CMP Round-robin S32DS2.0

Where can I get s32k14x data sheet or reference manual?

Example_S32K344_BIST_eMCEM_SPD106_v2_0_S32DS365_RTD700

Example_S32K142_LMEM_Cache_v1_0_S32DS3.6_RTD300

EMCEM DCM EIM mapping for S32K3x1 S32K3x2 S32K344 S32K324 S32K314

Example S32K344 EMAC lwIP FreeRTOS MRCANHUB S32DS 3.6.1 RTD600

Example S32K389 GMAC1 SABRE lwIP FreeRTOS S32DS 3.6.1 RTD600

Example S32K358 GMAC 1G lwIP FreeRTOS S32DS 3.6.1 RTD600

Example S32K358 GMAC 100M lwIP FreeRTOS S32DS 3.6.1 RTD600

Example S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600

Example S32K344 FlexIO I2C with DMA Optimize option S32DS 3.6.0 RTD 6.0.0

S32K312 : Interrupt & Wakeup using single GPIO RTD6.0.0 QLP04 S32DS3.6.2

[RTD600 MCAL] S32K3X4EVB-T172 RTC API Wake-up

Example S32K344 EMAC lwIP FreeRTOS miniEVB S32DS 3.6.1 RTD 6.0.0

Example S32K389 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD 6.0.0

S32K1 vdd falling low voltage POR clear situation

S32K389EVB Demo Code

S32K3 Motor control SW examples