Hi everyone, Welcome to the NXP Tech Days 2025 training session AUT-T437: Hands - On Workshop: Explore Ethernet Integration on the S32K3 Microcontroller. My name is Alejandro Flores Triana (Alex) and I will be your guide during this conference. I am an Automotive Applications Engineer supporting different OEMs, Tier1s, Partners and other internal NXP teams on topics related to communication protocols (e.g. CAN, LIN, SPI, I2C, Ethernet, etc.). The idea of this session is for you to understand how to program the S32K3 Ethernet interface using NXP Real-Time Drivers (RTDs) – Autosar MCAL Layer. We will use a base project and together modify it to create a simple Ethernet application. Therefore, to be ready follow the steps below to get your environment up and running before the session. On your laptop, install the NXP Software environment described in the attached presentation: Hands - On Workshop: S32K3 Ethernet Prerequisites.   Once you have the NXP software environment installed, download the attached project: S32K344_ETH_MCAL_TechDays.exe.   Run the .exe project with administrator rights. Accept the license and install in the desired folder.         Open the NXP Design Studio. Click File -> Import -> Existing Projects into Workspace.   Select root directory and browse the folder where you downloaded the project.   Select Copy projects into workspace. Then, click Finish.   Select the project. Click on the arrow next to the hammer. Click on Debug_FLASH. Then you are ready for the session! See you soon. Best Regards, Alejandro Flores Triana

**************************************************************************************************** * Detailed Description: * This code injects an ECC (Error Correction Code) error into DTCM (Data Tightly Coupled Memory) * using the EIM (ECC Injection Module). * * When the core reads the corrupted DTCM data, it triggers a fault due to the ECC error: * - A Bus Fault exception is raised by the core. * - The ERM (Error Reporting Module) also detects the fault and can generate an interrupt. * * By default, the ERM interrupt has a lower priority than the Bus Fault exception. * In this example, the Bus Fault exception priority is intentionally lowered so that the ERM * interrupt is handled first. This allows the system to respond to the ERM interrupt before * the core's Bus Fault handler executes. *************************************************************************************************** * ------------------------------------------------------------------------------------------------* * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: -- * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************

Hi everyone, Welcome to the NXP Tech Days 2024 training session AUT-T4977: Hands - On Workshop: S32K3 Ethernet- How to Configure Hardware and Software. This session was initially planned for 15 attendees. But due to the popularity of the lecture, we have increased the number of available seats . Therefore, we will work in pairs during the Hands-On. My name is Alejandro Flores Triana (Alex) and I will be your guide during this conference. I am an Automotive Applications Engineer supporting different OEMs, Tier1s, Partners and other internal NXP teams on topics related to communication protocols (e.g. CAN, LIN, SPI, I2C, Ethernet, etc.). The idea of this session is for you to understand how to program the S32K3 Ethernet interface using NXP Real-Time Drivers (RTDs) – Autosar MCAL Layer. We will use a base project and together modify it to create a simple Ethernet application. Therefore, to be ready follow the steps below to get your environment up and running before the session. On your laptop, install the NXP Software environment described in the attached presentation: Hands - On Workshop: S32K3 Ethernet Prerequisites.   Once you have the NXP software environment installed, download the attached project: S32K344_ETH_MCAL_TechDays.exe   Run the .exe project with administrator rights. Accept the license and install in the desired folder         Open the NXP Design Studio. Click File -> Import -> Existing Projects into Workspace   Select root directory and browse the folder where you downloaded the project   Select Copy projects into workspace   Click Finish. Select the project. Click on the arrow next to the hammer. Click on Debug_FLASH. Then you are ready for the session! See you soon. Best Regards, Alejandro Flores Triana

The procedure to restrict JTAG access on the S32K3 MCU depends on whether HSE Firmware (FW) is used: With HSE FW: This scenario is not covered in this document. Without HSE FW: WARNING: ONCE THIS PROCESS IS COMPLETED, HSE CANNOT BE INSTALLED ON THE DEVICE. Development Environment: All code snippets provided represent the essential parts of the application and were developed using: Test HW: S32K344 (not EVB) MCU: S32K344 IDE: S32DS v3.5 Debugger: PEmicro USB Multilink Universal FX (unless otherwise noted) Drivers: S32K3 Real-Time Drivers v3.0.0 (released March 31, 2023) Base Project: Modified version of C40_Ip_Example_S32K344 Step 1: Program the CUST_DB_PSWD_A Field The UTEST Sector is an OTP (One Time Programmable), meaning erase operations are not allowed. You can only append or read data. Memory Range: 0x1B00_0080 to 0x1B00_009 Only the first 16 bytes (0x1B00_0080 to 0x1B00_008F) are usable. The rest is reserved (see Table 202 in the S32K3xx Reference Manual, Rev. 11). Programming Steps: I. Unlock the UTEST sector using PFCBLKU_SPELOCK[SLCK]. II. Write the 16-byte password to address 0x1B00_0080. Code Adjustments: /*============================================================================ * LOCAL MACROS ============================================================================*/ #define FLS_MASTER_ID 0U #define FLS_BUF_SIZE 16U #define FLS_SECTOR_ADDR 0x1B000080U #define FLS_SECTOR_TEST C40_UTEST_ARRAY_0_S000 NOTE: Ensure FLS_MAX_VIRTUAL_SECTOR and C40_SECTOR_ERROR are correctly defined in C40_Ip_Cfg.h: Instead of: #define FLS_MAX_VIRTUAL_SECTOR (527U) … #define C40_SECTOR_ERROR (528U) Use: #define FLS_MAX_VIRTUAL_SECTOR (528U) … #define C40_SECTOR_ERROR (529U) /*============================================================================ * GLOBAL CONSTANTS ============================================================================*/ uint8 TxBuffer[FLS_BUF_SIZE] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F}; /* Password */ You can verify the password using the Memory Viewer (not covered here).   Step 2: Advance the MCU Lifecycle I. Set the lifecycle configuration word address in the IVT/boot header. Refer to sections 32.5 and 32.5.3 of the Reference Manual. NOTE: Ensure the structure of the boot_header (located in Project_Settings → Startup_Code → startup_cm7.s) is defined as follows: #define LF_CONFIG_ADDR (0x007D2000) /* The LC word can be at any flash address, taking care that does not interfere with HSE */ II. Write the LC word to the defined address: Life cycle stage Valid Values for LC Advancement OEM_PROD DADA_DADAh IN_FIELD BABA_BABAh Code Adjustments: /*=========================================================================== * LOCAL MACROS ===========================================================================*/ #define FLS_MASTER_ID 0U #define FLS_BUF_SIZE 8U #define FLS_SECTOR_ADDR 0x007D2000U #define FLS_SECTOR_TEST C40_CODE_ARRAY_0_BLOCK_3_S489 /* Look into C40_Ip_Cfg.h file to find the corresponding sector */ /*=========================================================================== * GLOBAL CONSTANTS ===========================================================================*/ uint8 LC_TxBuffer[FLS_LC_SIZE] = {0xDA, 0xDA, 0xDA, 0xDA, 0x0, 0x0, 0x0, 0x0}; /* Minimum data length 8 bytes */ Confirm the LC word using the Memory Viewer. III. Reset the MCU using the RESET_B pin, not the debugger. If the procedure was done correctly, you should see the following message: Step 3: Debugger Authentication To unlock the MCU, PEmicro provides Python scripts (PEmicro support files package) to facilitate debugger authentication when the password is set. In summary: I. Ensure Python 3.5 or later is installed. II. Open Command Prompt. III. Use cd to navigate to the directory containing the file package. IV. Run the script: py authenticate_password_mode.py -hardwareid=USB1 -password=… hardwareid: Debug hardware IP, name, serial number, or port password: 16-byte hexadecimal password NOTE: This must be done every time the MCU is reset or power cycled.   Step 4: Secure Debugging in S32DS In S32DS, when configuring the Debug Configurations of a project, change the Target to "SECUREDEBUG". This is necessary because during debug entry, a hard reset is toggled, which clears the authentication. Once authenticated, you can securely debug the device in S32DS.  *Additional Resources iSystem: How to unlock secure debug on NXP S32G2/3xx, S32R45x, and S32K3 Segger: NXP S32K3xx - Debug Authentication

[S32K3 Tools Part] How to port RTD's existing MCAL demo to other K3 chips  1. Abstract     From the release notes of NXP's RTD4.0.0, we can see that the supported chip models are very complete: Fig 1 From this point, we can know that RTD4.0.0 can cover all S32K3 series chips. But if you want a ready-made demo, such as MCAL demo, you can see it under the ready-made demo path, for example: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0\examples\EBT Just S32K344,S32K358,S32K388,S32K396,S32M276。 Therefore, if you use other S32 chips, such as K312, in actual use, although it is within the range supported by RTD, but there is no ready-made demo to use, you need to do the porting by yourself. This article will explain how to port the RTD4.0.0 K344 MCAL demo to S32K312 and configure the corresponding EB project. First, implement the execution in the command line. After success, port the working MCAL code EB project to S32DS. 2. Platform and migration steps 2.1 Platform Description This article is based on RTD4.0.0: SW32K3_S32M27x_RTD_R21-11_4.0.0 For other versions with patch or HF, the operation process is the same! Hardware platform: S32K312 mini EVB or S32K312EVB Other official EVBs, such as S32K31XEVB, or the customer's own S32K3 hardware board also have the same steps. Due to the lack of official EVB boards, this article is based on S32K312 mini EVB, combined with P&E Multilink simulator download simulation. The platform situation is as follows: Fig 2 2.2 Migration steps The reference demo can be any existing demo in RTD4.0.0. In order to simplify the process, this article takes DIO as an example: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0\examples\EBT\S32K3XX\Dio_Example_S32K344 2.2.1 Copy the project and configure 2.2.1.1 Copy the project In order not to affect the original RTD default demo, here we directly copy a Dio_TS_T40D34M40I0R0 and open the path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins Copy Dio_TS_T40D34M40I0R0 and save it in a folder named: Dio_TS_T40D34M40I0R0_miniK312_doc The process for other chips is similar. You only need to change the chip name and related configuration to the required chip. Open folder： C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX Copy Dio_Example_S32K344 to Dio_Example_S32K312 Fig 3    Open path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\TresosProject  Modify the EB project Dio_Example_S32K344 to Dio_Example_S32K312 Fig 4 2.2.1.2 Configure the project Enter the newly created Dio_Example_S32K312, open the path with VScode, and save the VScode workspace to this path. Modify project_parameters.mk: GCC_DIR = C:/NXP/S32DS.3.5_RTD400/S32DS/build_tools/gcc_v10.2/gcc-10.2-arm32-eabi TRESOS_DIR = C:/EB/tresos_29_0_0 PLUGINS_DIR = C:/NXP/SW32K3_S32M27x_RTD_R21-11_4.0.0/eclipse/plugins EXAMPLE_DERIVATIVE = S32K312 TRESO_PROJECT_NAME = Dio_Example_S32K312 ​ Fig 5 Fig 6 Check_build_params.mk, delete the following code: ifeq ("$(wildcard $(T32_DIR)/bin/windows/t32marm.exe)","") $(error Invalid path set to Trace32. \ The provided path: from project_parameters.mk T32_DIR=$(T32_DIR) is invalid!) endif This part is used for lauterbach trace32. If it is not deleted, an error will be reported. 2.2.2 EB project configuration The following is the configuration of the EB project. Open the EB tresos Studio 29.0 software and import the project. File->Import->General->Existing Projects into Workspace, add the EB project path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\TresosProject\Dio_Example_S32K312 Note, do not click copy projects into workspace!!! Select the project Dio_Example_S32K344, right-click the mouse, and rename it to: Dio_Example_S32K312 Fig 7 Double-click someId to open the configuration module. Open the Resource module, General->ResourceSubderivative select the target chip partbumber, here select: s32k312_hdqfp172 Fig 8 After saving, you will find many errors reported as follows: Fig 9 There is no need to worry too much here, because if you analyze it carefully, you will find that it is actually because there are many modules on K344 that K312 does not have. So enter the error prompt location and delete the missing K312 module. Mcu->McuModeSettingConf->McuPeripheral If you click in, you can find that if the K312 does not have a module, there is a red cross in front of the peripheral Name. Fig 10 The direct method is to delete all the error items, a total of 41. After deleting, you can find that all the problems are gone: Fig 11 Select someId in the project, right-click, and click Generate Code. You can see that the project can be generated without any errors. Fig12 Don't take it lightly here. Although the code can be generated without error, there is still a place that needs to be modified. Here, we can firstly close the EB tresos tool, then open terminal->new terminal in VScode and enter: Fig13 We can see the error content is : mcucgm0_clockMux0/McuClockMux0Divider5, McuClockMux0Divider6, McuClkMux0Div5_En, McuClkMux0Div6_En. Open S32KRM here, and you can see that K312 actually does not have MUX_0_5,6. Fig 14 At this time, when I opened the EB tresos software again, there was indeed such an error on the interface, and there was no divider 5,6 option in mcucgmClockMux0. Fig 15 Don't worry at this time, there is a way to fix this problem. Close the EB tresos tool and open the text: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\TresosProject\Dio_Example_S32K312\config\ Mcu.xdm file. Directly turn off the enablement and value configuration of divider 5 and 6 in the file. Modify the following code:Modified to:The main thing is to change the enable and frequency value of Mux0Divider5,6 hidden in the file. Reopen it and you can see that the error disappears. Right-click on the EB project someId, generate project, and the code can be generated normally without error. Here is a little trick: In order to prevent the mismatch between the previously generated code and the latest EB project, you can also change: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\generate Folder：src，include clean it，then regenerate in EB tresos when generating a project. Close the EB software and enter make generate again in the terminal of the Vscode project You can see that there are no problems at this time: Fig 16  3.Command line compilation and result testing From the above steps, the code and EB configuration migration of an existing RTD K344 project to a K312 MCAL project has been completed. Now, through VScode, command line form, generate main.elf, and then download and test. Command: make generate make build the main.elf can be found in the following folder path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\out Regarding testing, because there is a main.elf file and PE Multilink, you can create a new K312 project in S32DS. The debug interface is PE Multilink. After compiling and generating the code, copy main.elf to the Debug_FLASH folder of the new project. In the S32DS debug configuration, directly replace the C/C++ application with main.elf and download it for testing.  Fig 17 As you can see, you can enter the debug interface, and the LED light on the actual test board can flash successfully. This means that the MCAL code has been successfully ported to K312. 4. S32DS project migration and testing       In the previous document: https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Tools-Part-How-to-import-RTD-EB-project-into-S32DS/ta-p/1966207 Previously, the RTD MCAL EB project was transplanted to the K344 project of S32DS. Simply modify the project name, project chip model, ld file, driver file inclusion, etc., then clean the project and compile the project.      It is assumed here that you already have an RTD MCAL project imported into the S32DS project, and then modify it based on this. 4.1 S32DS Project Configuration     Because the folder was copied under the original RTD folder, there is a newly created folder in the S32DS project Mcal_Plugins->Link_Source. This folder needs to be excluded from compilation: Select Dio_TS_T40D34M40I0R0_minik312_doc, right-click Build path->remove from->Debug_FLASH.      Fig 18 Rename the project from Mcal_Dio_S32K344_RTD400 to Mcal_Dio_S32K312_RTD400. Modify the following project configuration, project->properties: （1）preprocessor S32K344->S32K312 Fig 19   (2) Sstandard S32DS C Linker->General Modify "${MCAL_PLUGIN_PATH}/Platform${MCAL_MODULE_NAME_SUFFIX}/build_files/gcc/linker_flash_s32k344.ld" To "${MCAL_PLUGIN_PATH}/Platform${MCAL_MODULE_NAME_SUFFIX}/build_files/gcc/linker_flash_s32k312.ld" After modification, click apply and close Now, change the main.c content to the content in path:  C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\src\main.c Add header file: #include "Port_Cfg.h" Comment code: // #include "check_example.h" // Exit_Example(TRUE);   4.2 EB project replacement Copy： C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Dio_TS_T40D34M40I0R0_miniK312_doc\examples\EBT\S32K3XX\Dio_Example_S32K312\TresosProject\Dio_Example_S32K312\config All the .xdm file to the S32DS EB folder, replace the old file: Mcal_Dio_S32K312_RTD400\Tresos_Project\Mcal_Dio_S32K344_RTD400\config Use the EB tresos open the above project, then Generate project，after the code is generated, close the EB project, back to the S32DS side. 4.3 MCAL S32DS project testing clean project：project->clean project,  then build the project Fig 20 You can see that it can be compiled successfully, then RUN->debug configuration selects the downloaded code xxx_Debug_FLASH_PNE. Note that you need to change the Device from S32K344 to S32K312 Fig 21 After successful configuration, click debug, download the code and simulate. The results are as follows: Fig 22 As you can see, we can successfully enter debug, and the light on the board is actually blinking, which means that the RTD MCAL project demo can be successfully ported to S32K312 S32DS. Video: 1.MCAL demo porting K344 to K312 based on RTD500     2.S32DS CT MCAL demo porting K344 to K312 based on RTD500  

This document provides a brief explanation of the Excel-based calculator developed to assist with the computation of TX Arbitration Start Delay as described in the S32K3 reference manual. The tool implements the formula provided in the datasheet, allowing users to input relevant parameters and automatically calculate the delay values. It is intended to support engineers in evaluating CAN transmission timing and optimizing arbitration performance in S32K3-based applications.   1.Fill in the clock and CBT and FDCBT configuration parameters according to your requirements. For example, we fill the parameters according Case 3:  Then we can get the TASD value for non-FD frames is 24.05.   Please note that this summary is not officially released by NXP. It is a personal summary for reference only. If there are any errors, please contact me.

****************************************************************************************************** * Detailed Description: These demos showcase how to configure the eMIOS module on the S32K3 series, highlighting various operational modes and their implementations using the RTD high-level drivers, commonly known as MCAL drivers. The implementations demonstrated in these examples follow the approach outlined in the community thread:  S32M27x/S32K3 – eMIOS Usage. * Connections:  ******************************************************************************************************* * Test HW: S32K31XEVB-Q100 * MCU: S32K311 * Debugger: S32DS 3.6.2, OpenSDA/ PEmicro Multilink Universal FX  * Target: internal_FLASH ******************************************************************************************************* * Important information:  The OPWMT channel does not support the notification function. In this mode, the Sn[FLAG] bit is only set upon an AS2 match, which defines the generation of a trigger event within the PWM period. As a result, OPWMT mode cannot support notifications based on signal edges. A bus exception may occur during the execution of Mcl_Init() if the eMIOS clock is not properly enabled. To avoid this issue, ensure that the eMIOS peripheral clock is activated in the configuration settings under: MCU driver → McuModuleConfiguration → McuModeSettingConf → McuPeripheral *******************************************************************************************************

**************************************************************************************************** * Detailed Description: * * - CMU errors cannot be injected by any means other than manipulating the CMU thresholds, * except for FXOSC_CLK, which can be physically disrupted on the PCB. * * - CMU_FC_0 (FXOSC_CLK) is configured for **synchronous interrupt** on both LFF and HFF CMU events. * - CMU_FC_3 (CORE_CLK) is configured for **asynchronous destructive reset** triggered only by the LFF event; the HFF event is ignored. * - CMU_FC_4 (CORE_CLK) is configured identically to CMU_3: **asynchronous destructive reset** on LFF only; HFF is ignored. * - CMU_FC_5 (HSE_CLK) can be configured by the HSE_B core only. * Refer to the Reference Manual rev.10, Figure 122. Frequency checking (FC) instances * * - The configuration must be identical in both the MCU MCAL driver and the Clock Configuration Tool (clock details). * - To inject a specific CMU error, define one of the following macros: `INJECT_CMU_0`, `INJECT_CMU_3`, or `INJECT_CMU_4`. * * Behavior After Destructive Reset: * - Following a destructive reset (either `MCU_CORE_CLK_FAIL_RESET` or `MCU_AIPS_PLAT_CLK_FAIL_RESET`), * execution will halt in the `while(wait)` loop. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: RTD 6.0.0 * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************

     In fact, this topic has been written by many people before, and it is well written. However, in actual operation, you may encounter some pitfalls, so this article will not write the article steps in detail, but will provide a real and direct operation video process. The main reference article source link is: https://www.wpgdadatong.com.cn/blog/detail/74936 The method is very useful. I have tried the existing RTD4.0.0 MCAL code and also imported it into my own configured MCAL code. The method is reliable and effective. Platform:     SW32K3_S32M27x_RTD_R21-11_4.0.0 S32DS3.5 EB tresos Studio 29.0 S32K344-EVB Attach the video directly: The main steps are as follows: STEP 1. Create a new S32DS project STEP 2. S32DS project configuration Including folder deletion, addition, filter condition addition, include files, link files, optimization conditions, macro definitions, etc. STEP 3. Create a new EB project Configure a new RTD, or copy the existing RTD configuration to avoid unnecessary problems and errors. STEP 4. Compile and download The following are some related files that need to be copied: MCAL_Plugins->Link Source Resource Filters   Fig 1 Includes   Fig 2 "${ProjDirPath}/Generate/include" "${MCAL_PLUGIN_PATH}/Adc${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Ae${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/BaseNXP${MCAL_MODULE_NAME_SUFFIX}/header" "${MCAL_PLUGIN_PATH}/BaseNXP${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Can_43_FLEXCAN${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/CanIf${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/CanTrcv_43_AE${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Crc${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/CryIf${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Crypto_43_HSE${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Csm${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Dem${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Det${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Dio${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Dpga${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/EcuM${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Eth_43_GMAC${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/EthIf${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/EthSwt${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/EthTrcv${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Fee${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Gdu${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Gpt${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/I2c${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/I2s${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Icu${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Lin_43_LPUART_FLEXIO${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/LinIf${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/LinTrcv_43_AE${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Mcl${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Mcu${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Mem_43_EEP${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Mem_43_EXFLS${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Mem_43_INFLS${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/MemAcc${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/MemIf${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Ocotp${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Ocu${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Os${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Platform${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Platform${MCAL_MODULE_NAME_SUFFIX}/startup/include" "${MCAL_PLUGIN_PATH}/Port${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Pwm${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Rm${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Rte${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Sent${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Spi${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Uart${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Wdg${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/WdgIf${MCAL_MODULE_NAME_SUFFIX}/include" "${MCAL_PLUGIN_PATH}/Zipwire${MCAL_MODULE_NAME_SUFFIX}/include"   Preprocessor   Fig  3 S32K3XX S32K344 GCC USE_SW_VECTOR_MODE D_CACHE_ENABLE I_CACHE_ENABLE ENABLE_FPU   Linker   Fig  4 "${MCAL_PLUGIN_PATH}/Platform${MCAL_MODULE_NAME_SUFFIX}/build_files/gcc/linker_flash_s32k344.ld" optimization   Fig 5 -fno-short-enums -funsigned-char -fomit-frame-pointer -fstack-usage   main.c Comment: #include "check_example.h #Exit_Example(TRUE);   Attached code: MCAL_Dio_S32K344_S32DS363_RTD600_CP.zip: RTD MCAL copy to S32DS project Others attachment all link the MCAL to RTD install path.

[S32K3 tool part]：How to use IAR compiler or IAR project to compile MCAL project   1.    Abstract      Through regular observation, it has been found that there are still many customers using platforms such as MCAL+IAR, including those using IAR compilers and those directly using IAR IDEs. In fact, when I was working on industrial MCUs in the past, I also particularly liked IAR IDE for its fast compilation speed, high compilation efficiency, and small code generation. However, when I came to auto MCU, I found that its popularity was not very high, and I also noticed that some customers encountered various problems when importing MCAL into IAR. Therefore, I will directly write a tool article on how to use IAR compiler or IAR IDE project to compile NXP S32K MCAL in combination with EB tresos MCAL. This article uses S32K344 combined with RTD600 to illustrate the compilation of MCAL projects using IAR compiler and the direct import of MCAL into IAR IDE projects 2. IAR Complier with S32K3 RTD MCAL project 2.1 S32K3 HW and SW SW32K3_S32M27x_RTD_R21-11_6.0.0 S32K3X4-EVB Based on Dio_TS_T40D34M60I0R0 IAR：IAR EW for Arm 9.70.1 EB tresos29.0.0 2.2 Compile MCAL project steps using IAR compiler CMD method 2.2.1 Copy one RTD MCAL new project Open path C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins Copy Dio_TS_T40D34M60I0R0 , rename it as Dio_TS_T40D34M60I0R0_IAR Fig 1 2.2.2 Complie EB tresos project Use EB tresos tool open the following EB tresos project ： C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0_IAR\examples\EBT\S32K3XX\Dio_Example_S32K344\TresosProject Generate code: Fig 2 2.2.3 Vscode open Dio_TS_T40D34M60I0R0_IAR project Use VS code open the following path folder: C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0_IAR\examples\EBT\S32K3XX\Dio_Example_S32K344 Of course, you can also directly open this folder path using the command line, as long as you ensure that it is in the same layer path as the. mk and makefile scr Fig 3 2.2.4   Project_parameters.mk modification Mainly modify the following points: TOOLCHAIN = iar IAR_DIR = C:/IAR/ewarm-9.70.1 TRESOS_DIR = C:/EB/tresos_29_0_0 PLUGINS_DIR = C:/NXP/SW32K3_S32M27x_RTD_R21-11_6.0.0/eclipse/plugins The path of IAR must be consistent with the version of IAR software used to ensure that the corresponding IAR compiler can be found. Fig 4 2.2.5   Check_build_params.mk modification Add the following content to check_build_params.mk： else ifeq ($(TOOLCHAIN),iar) ifeq ("$(wildcard $(IAR_DIR)/arm/bin/iccarm.exe)","") $(error Invalid path set to the IAR compiler. \ The provided path: from project_parameters.mk IAR_DIR=$(IAR_DIR) is invalid!) Endif Fig 5 2.2.6        Makefile modification   Makefile need the following 5 points modification: （1）Compilier change ifeq (${TOOLCHAIN},iar) CC := $(IAR_DIR)/arm/bin/iccarm.exe LD := $(IAR_DIR)/arm/bin/ilinkarm.exe AS := $(IAR_DIR)/arm/bin/iasmarm.exe # Intel Hexadecimal Flash image tool GENHEX := $(IAR_DIR)/arm/bin/ielftool.exe HEX_OPTS := --ihex OUT_OPTS := -o endif Fig 6 (2) SRC_DIRS  add TOOLCHAIN SRC_DIRS += $(foreach mod,$(MCAL_MODULE_LIST),$(PLUGINS_DIR)/$(mod)_$(AR_PKG_NAME)/src) \ $(foreach mod,$(MCAL_MODULE_LIST_ADDON),$(PLUGINS_DIR_ADDON)/$(mod)_$(AR_PKG_NAME_ADDON)/src) \ $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/startup/src \ $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/startup/src/m7 \ $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/startup/src/m7/$(TOOLCHAIN) Fig 7 (3) Linker file  modification ifeq ($(LOAD_TO),flash) ifeq (${TOOLCHAIN},iar) LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/${TOOLCHAIN}/linker_flash_$(DERIVATIVE_LOWER).icf else LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/$(TOOLCHAIN)/linker_flash_$(DERIVATIVE_LOWER).ld endif else ifeq (${TOOLCHAIN},iar) LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/$(TOOLCHAIN)/linker_ram_$(DERIVATIVE_LOWER).icf else LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/$(TOOLCHAIN)/linker_ram_$(DERIVATIVE_LOWER).ld endif endif Fig 8 (4) Complier options change ifeq (${TOOLCHAIN},iar) ################################################################################ # iar Compiler options ################################################################################     clib        := $(IAR_DIR)/arm/lib     CCOPT           +=  --cpu=Cortex-M7 \                         -DAUTOSAR_OS_NOT_USED \                         -DUSE_MCAL_DRIVERS \                         --fpu=FPv5-SP \                         --cpu_mode=thumb \                         --endian=little \                         -e \                         -Ohz \                         --debug \                         --no_clustering \                         --no_mem_idioms \                         --do_explicit_zero_opt_in_named_sections \                         --require_prototypes \                         --no_wrap_diagnostics \                         --diag_suppress=Pa050 \                         $(MISRA) \                         -D$(PLATFORM) \                         -D$(DERIVATIVE) \                         -DIAR \                         -DUSE_SW_VECTOR_MODE  \                         -DENABLE_FPU \                         -DD_CACHE_ENABLE \                         -DI_CACHE_ENABLE                             LDOPT           :=  --entry _start \                         --enable_stack_usage \                         --skip_dynamic_initialization \                         --no_wrap_diagnostics \                         --cpu=Cortex-M7 \                         --fpu=FPv5-SP                             ASOPT           :=  $(ASOPT) \                         --cpu Cortex-M7 \                         --cpu_mode thumb \                         -g \                         -r \                         -DMULTIPLE_CORE   endif   Fig 9 Fig  10 So how did these IAR compilation options come about? You can refer to the release note of RTD600, which contains corresponding descriptions Fig 11 (5) Elf related change ifeq (${TOOLCHAIN},iar) %.elf: %.o $(LINKER_DEF)               @echo "Linking $@"               @$(LD) $(ODIR)/*.o $(LDOPT) --config $(LINKER_DEF) --map $(ODIR)/ -o $(ODIR)/$@@               @$(GENHEX) $(HEX_OPTS) "$(ODIR)/$(ELFNAME).elf" "$(ODIR)/$(ELFNAME).hex" else %.elf: %.o $(LINKER_DEF)               @echo "Linking $@"               @$(LD) -Wl,-Map,"$(MAPFILE)" $(LDOPT) -T $(LINKER_DEF) $(ODIR)/*.o -o $(ODIR)/$@@               @$(GENHEX) $(HEX_OPTS) "$(ODIR)/$(ELFNAME).elf" $(OUT_OPTS) "$(ODIR)/$(ELFNAME).hex" endif   Fig 12 2.2.7   Build to generate elf Commander: make clean make build to generate the elf files： Fig 13 After generation, the elf can be burned onto the S32K344 EVB board for testing. The test results show that the onboard red light is flashing, indicating that the IAR compiler can work in command-line mode. 3. Import RTD MCAL to IAR IDE project This chapter explains how to create an IAR IDE project and import MCAL drivers to implement S32K3 MCAL combined with EB tresos for running. 3.1 MCAL IAR IDE project 2 methods Difference between two methods and how to import MCAL drivers: (1) Directly copy the RTD MCAL driver to the IAR IDE project directory (2) Connect the IAR IDE project driver to the original RTD driver path Fig 14 3.2 MCAL IAR IDE project import steps 3.2.1 create the new RTD MCAL IAR project folder    Create a new folder, named as：S32K344_DIO_MCAL_RTD600_IAR 3.2.2 create the sub folder for IAR project       Generate：EB tresos project code       Include：app related include file       Mcal： mcal driver copy from RTD       src： project main file       Tresos_Project：EB tresos project Fig 15 3.2.3 create EB tresos project (1) Create the EB tresos project in the followign path：  S32K344_DIO_MCAL_RTD600_IAR\Tresos_Project\Mcal_Dio_S32K344_RTD600_IAR   (2)Add modules: BaseNXP, Dem, Dio, EcuC, Mcu, Platform, Port, Resource   (3)Copy RTD xdm files in the following path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0\examples\EBT\S32K3XX\Dio_Example_S32K344\TresosProject\Dio_Example_S32K344\config to： S32K344_DIO_MCAL_RTD600_IAR\Tresos_Project\Mcal_Dio_S32K344_RTD600_IAR\config   (4)EB tresos Generate project EB tresos code will be generated to folder: S32K344_DIO_MCAL_RTD600_IAR\Generate Fig 16 3.2.4 Copy RTD related drivers to IAR project folder (1) BaseNXP: header, include, src (2)Det:  include, src (3)Dio:  include, src (4)Mcu:  include, src (5)Platform: build_files, include, src, startup (6)Port: include, src (7)Rte: include, src Copy RTD folder to IAR project is one method, if don’t want to copy the file, also can use the linker to add the RTD install path drivers directly. Fig 17 3.2.5 IAR IDE create IAR project   (1) Project->Create new project   (2) In the IAR project, add group   The related folder in project can be structured like the fig 18, which contains:   Generate: Include and src->EB tresos project generate code   Mcal:  Base, Det, Dio, Mcu, Platform, Port, Rte->Mcal driver   Src: Main.c->project main code      (3) Add RTD mcal related drivers to IAR project The RTD MCAL related driver files can be directly downloaded from the RTD installation path or copied to a folder in the IAR project, and both methods yield the same result. Fig 18 （4）IAR project platform folder added result: Fig 19 （5）main code add Main.c can copy from path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0\examples\EBT\S32K3XX\Dio_Example_S32K344\src to S32K344_DIO_MCAL_RTD600_IAR\src Comment:  //#include "check_example.h"  // Exit_Example(TRUE);   3.2.6 IAR project options configuration (1)General options->Target->Device->NXP S32K344 (2)C/C++ Complier->Preprocessor Addional include directories: Use IAR project folder drivers which copied from RTD install path, the directories are： $PROJ_DIR$\Generate\include $PROJ_DIR$\mcal\BaseNXP_TS_T40D34M60I0R0\header $PROJ_DIR$\mcal\BaseNXP_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Mcu_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Platform_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Rte_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Platform_TS_T40D34M60I0R0\startup\include $PROJ_DIR$\mcal\Det_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Dio_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Port_TS_T40D34M60I0R0\include $PROJ_DIR$\include If use the RTD install path drivers, use the following directories： $PROJ_DIR$\Generate\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\BaseNXP_TS_T40D34M60I0R0\header C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\BaseNXP_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Mcu_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Platform_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Rte_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Platform_TS_T40D34M60I0R0\startup\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Port_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Det_TS_T40D34M60I0R0\include $PROJ_DIR$\include   Defined symbols: S32K3XX S32K344 IAR USE_SW_VECTOR_MODE D_CACHE_ENABLE I_CACHE_ENABLE ENABLE_FPU   Extra options: --no_clustering --no_mem_idioms --do_explicit_zero_opt_in_named_sections --require_prototypes --no_wrap_diagnostics   Languate 1:   Check Require prototypes   Diagnostics Suppress these disgnostics: Pa050 Fig 20 (3)Linker: Two points need to be added： $PROJ_DIR$\mcal\Platform_TS_T40D34M60I0R0\build_files\iar\linker_flash_s32k344.icf Library->Entry symbols: _start Fig 21 (4)Debugger Setup: PE micro, run to main Extra Options: Use command line options: --drv_vector_table_base=__ENTRY_VTABLE Fig 22 3.2.7  Build IAR project Project->Rebuild All Fig 23 3.2.8  Test result Download and debug result: Fig 24 After downloading and running, the red led is blinking on the board, indicating that the IAR IDE MCAL import method project has been successfully run.  

* ================================================================================================== * Detailed Description: * * This example shows how to implement ADC continuous scan with DMA read. * ADC1 is set to perform continuous scan of 4 channels (S10/S11/S12,S13) with DMA request enabled * for last channel S13. DMA reads respective sequential ADC data registers in one major loop. * * ADC1 channel S10 is connected to board's potentiometer, converted value is used to dim board's LED. * * ================================================================================================== * Test HW: S32K312EVB-Q172 * MCU: S32K312_172LQFP * Compiler: S32DS 3.6.3 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: On-Board Debugger (J40), Lauterbach * Target: Internal_FLASH * ==================================================================================================   Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.  

*******************************************************************************  The purpose of this demo application is to present a usage of the  LPSPI IP Driver for the S32K3xx MCU.  The example uses LPSPI2 for transmit & receive Twelve bytes using the DMA. MOSI MISO connected on Hardware in loopback.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** DATA and Instruction CACHE is enabled by default --> in startup code :--     ========= This selection enable the use of CACHE driver API =========     ============= Use this MACRO ==================== #define USE_NON_CHACHABLE_REGION 1 This MACRO comment & uncomment will allocate the buffer in cachable & non cacable region of memory. You can allocate the SPI buffer in in cachable & non cacable region of memory. Enabling & disabling of this MACRO will adjust the example code.     ============ How this example works : Cacheable region used ============ I have connected MOSI and MISO pins of spi at hardware level. Whenever I am  sending and receiving total 10 numbers of 12 byte packet On each transmission of 12 byte packet I am incrementing the first bite of transmit buffer just to distinguish between packets at the receive side Cache_Ip_InvalidateByAddr() --> I have to call this API every time I receive 12 byte of data on receive buffer Cache_Ip_CleanByAddr() --> every time after incrementing the transmit buffer first byte ...I have to call this API then only the correct data is transmitted otherwise it will transmit the same data which was available at first time transfer ================ Cache API operation ============== Cache_Ip_InvalidateByAddr() is for the  invalidate operation. Cache_Ip_CleanByAddr() is for the clean operation or clean&invalidate operation that can be chosen by param of this api: @Param[in]  enInvalidate      Specifies to execute operation Clean&Invalidate. Clean: This operation ensures that all dirty lines—data in the cache that has been modified but not yet written back to the main memory—are written back to the main memory ->(push data from cache memory to main memory)  Invalidate: This operation marks the cache lines as invalid, ensuring that any subsequent access to these lines results in a fetch from the main memory, thus ensuring data consistency ->(push data from main memory to cache memory) Clean&invalidate : A cache clean and invalidate operation behaves as the execution of a clean operation followed immediately by an invalidate operation. Both operations are performed to the same location. ================ Pins used ======================    

*******************************************************************************  The purpose of this demo application is to present a usage of the  FS26 watchdog timer refresh using the SBC_FS26 CDD  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * FS26 : CDD 2.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Please Modify attached code, and add this line of code, in this function Sbc_Wdg_Refresh_Notification  :-- Gpt_StopTimer(GptConf_GptChannelConfiguration_GptChannelConfiguration_0);     This change will make the example work for even starting FS26, driver at 6 msec and above.   Watchdog type :-- NXP eval boards has ASIL-D FS26 part with challenger watchdog. The OTP of FS26 on the board uses challenger watchdog. Change watchdog in code :-- FS26 watchdog is started in disabled mode (means infinite period). Later on we change the watchdog time in the code :--     Array Index for watchdog refresh timing  :-- Example will run once you press switch USER_SW0 connected on PTB26 on the Evaluation board :-- Please add this type of check in your code, during development process so that, avoid any error due to FS26 watchdog mis trigger. When you use Debug FLASH then in that case code goes to flash memory & can cause your MCU to frequent RESET, which caused issue for reprogramming the NEW firmware on the board FLASH memory. If we add this type of check then we can avoid the Faulty FS26 Software to stop misbehaving before flashing new firmware on the board.   In CDD-2.0.0, FS26 goes to INIT_FS state here  :--- Sbc_fs26_InitDevice() --> Sbc_fs26_CheckStateAndGotoInitFS()   In CDD-2.0.0, If we start the Watchdog in enabled mode, watchdog notification function to refresh watchdog is called from this function  :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() -->      In CDD 2.0.0, Following function call will exit Debug mode & Release FS0b & FS1B pin :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() :--- --> Sbc_fs26_ExitDebugMode() --> Sbc_fs26_ReleaseSequence()   In CDD 2.0.1, Following function call will exit Debug mode & Release FS0b & FS1B pin :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() --> Sbc_fs26_ExitDebugMode() ===================== CDD-2.0.1 example ================= RTD used :-- S32K3XX_AASW_4_7_RTM_FS26_2_0_1_DS_updatesite_2311_signed.zip Watchdog started in the Disabled mode (i.e infinite Period) then watchdog period is changed in the code main() function :--   Driver configuration :--   These function get executed :--       One bug in RTD   ---> S32K3XX_AASW_4_7_RTM_FS26_2_0_1_DS_updatesite_2311_signed.zip :-- RTD driver Bug is corrected like this :--   

Abstract This example presents an use case for analogue data capturing using eMIOS, BCTU, SAR-ADC and DMA modules on S32K39-37-36 series based on the RTD low level API to support diverse application needs.   Connections: S32K396-BGA-DC1 -> Pin -> Signal -> Label J62-1 -> PTC30 -> siul2_gpio_xx -> GPIO1_GPT (D0) J58-1 -> PTE14 -> emios_0_ch_19_z -> PWM1 J58-2 -> PTG9 -> siul2_gpio_xx -> GPIO2_eMIOS_Trigger J62-2 -> PTC31 -> siul2_gpio_xx -> GPIO3_BTCU_Trigger J62-4 -> PTD6 -> siul2_gpio_xx -> GPIO4_BTCU_Watermark J62-24 -> PTB14 -> adc1_s21 -> ADC1 *To use the potentiometer of S32X-MB connect: J62-24 (in S32K396-BGA-DC1) to P26-1 (in S32X-MB) Note: Following line should be added in project/generate/src/Bctu_Ip_PBcfg.c every time the code is updated in Config Tools: #define DMA_LOGIC_CH_0 ((uint8)0U)   Detailed Description: The Compare Value of GPT eMIOS_0_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 2 events, which describe the start and the end of the signal sequence. The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels, enabling synchronization between other them—there is just one PWM in this case. This synchronization ensures that channels share the same time base, thereby defining a common period for their operation. The emios_0_ch_19_g channel is configured as OPWMT mode, which offer more flexibility for triggering. An interrupt is requested on every flag event, during which GPIO2 is toggled—happens at half the time high in this case. This flag event, can be configured using Trigger parameter. For more details about eMIOS, please refer to S32M27x/S32K3 – eMIOS Usage, considering differences for porting from S32K3 to S32K39-37-36 in AN14301. The BCTU implements a list for parallel conversions using ADC0 and ADC1. Which is triggered by the eMIOS channel, and the resulting data is stored in FIFO1, as follows: ADC0: VREFH_ChanNum51 -> BANDGAP_ChanNum48 ADC1: VREFL_ChanNum50 -> S21_ChanNum45 For debugging purposed the GPIO3 is toggled every BCTU Trigger Notification. Additionally, the GPIO4 is toggled in BCTU Watermark Notification, which happens every time the number of active entries in FIFO exceeds the watermark level, and therefore the data is available for reading. See full signal sequence in Figure 1: Figure 1. Signals of example project When you suspend debug session, in Expressions tab (Figure 2) you can observe results: g_fifo1Result, which corresponds to the BCTU list measurements, meanwhile g_fifo1Volts corresponds to the conversion in volts. Figure 2. Expressions tab of example project   References S32 Design Studio for S32 Platform Real-Time Drivers (RTD) S32K39, S32K37 and S32K36 Data Sheet [S32K39-S32K37-DS] S32K39, S32K37, and S32K36 Reference Manual [S32K396RM] S32K344 to S32K39/S32K37 Migration Guide [AN14301] S32K39/37/36 Electrification Microcontrollers Evaluation Board [S32K396-BGA-DC1] S32X-MB I/O Extension Evaluation Board for Real-Time Domain Control and Actuation [S32X-MB] S32M27x/S32K3 – eMIOS Usage [S32M Knowledge Base] S32M27x/S32K3 – eMIOS/BTCU/ADC/DMA – [RTD600] [S32M Knowledge Base] S32K39-37-36 – eFlexPWM/TRGMUX/BCTU/SAR-ADC/DMA – [RTD600] [S32M Knowledge Base] Application Software: - S32K396_RTD600_eMIOS_BCTU_SARADC_DMA_Ip_example Example was built and tested using the following IDE and Driver versions: - S32 Design Studio for S32 Platform Version 3.6.3 - S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0

Abstract This example presents an use case for complementary PWM outputs with dead-time insertion and hardware ADC triggering using eFlexPWM, TRGMUX, BCTU, SAR-ADC and DMA modules on S32K39-37-36 series based on the RTD low level API to support diverse application needs. Connections: S32K396-BGA-DC1 -> Pin -> Signal -> Label J62-1 -> PTC30 -> siul2_gpio_94 -> GPIO1_GPT J62-5 -> PTD2 -> pwm_0_a, 2 -> PWM1 J62-6 -> PTD3 -> pwm_0_b, 2 -> PWM2 J62-30 -> PTD24 -> pwm_0_a, 0 -> PWMT J62-2 -> PTC31 -> siul2_gpio_95 -> GPIO3_BTCU_Trigger J62-4 -> PTD6 -> siul2_gpio_102 -> GPIO4_BTCU_Watermark J62-24 -> PTB14 -> adc1_s21 -> ADC1 *To use the potentiometer of S32X-MB connect: J62-24 (in S32K396-BGA-DC1) to P26-1 (in S32X-MB)   Note: Following line should be added in project/generate/src/Bctu_Ip_PBcfg.c every time the code is updated in Config Tools: #define DMA_LOGIC_CH_0 ((uint8)0U)   Detailed Description: The Compare Value of GPT eMIOS 0 channel 0 generates a time-out period. Once time-out is reached its eMIOS notification toggles GPIO1. This allows us to observe in scope 2 events, which describe the start and the end of the signal sequence. The eFlexPWM0 module is used for generating PWMs and hardware ADC triggering. The eFlexPWM0 Submodule 2 is employed to generate center-aligned complementary PWM outputs (PWM1 and PWM2) with dead-time insertion. The eFlexPWM0 Submodule 0 generates another independent PWM output (PWMT) and is utilized to generate the trigger signal for analog data capturing within the same PWM period —happens at half the time high in this case—using VAL0 register. The BCTU implements a list for parallel conversions using ADC0 and ADC1. Which is triggered by the eMIOS channel, and the resulting data is stored in FIFO1, as follows: • ADC0: VREFH_ChanNum51 -> BANDGAP_ChanNum48 • ADC1: VREFL_ChanNum50 -> S21_ChanNum45 For debugging purposed the GPIO3 is toggled every BCTU Trigger Notification. Additionally, the GPIO4 is toggled in BCTU Watermark Notification, which happens every time the number of active entries in FIFO exceeds the watermark level, and therefore the data is available for reading. See full signal sequence in Figure 1: Figure 1. Signals of example project When you suspend debug session, in Expressions tab (Figure 2) you can observe results: g_fifo1Result, which corresponds to the BCTU list measurements, meanwhile g_fifo1Volts corresponds to the conversion in volts. Figure 2. Expressions tab of example project   References S32 Design Studio for S32 Platform Real-Time Drivers (RTD) S32K39, S32K37 and S32K36 Data Sheet [S32K39-S32K37-DS] S32K39, S32K37, and S32K36 Reference Manual [S32K396RM] S32K344 to S32K39/S32K37 Migration Guide [AN14301] S32K39/37/36 Electrification Microcontrollers Evaluation Board [S32K396-BGA-DC1] S32X-MB I/O Extension Evaluation Board for Real-Time Domain Control and Actuation [S32X-MB] S32K39-37-36 – eMIOS/BTCU/SAR-ADC/DMA – [RTD600] [S32K Knowledge Base]   Application Software: - S32K396_RTD600_eFlexPWM_TRGMUX_BCTU_SARADC_DMA Example was built and tested using the following IDE and Driver versions: - S32 Design Studio for S32 Platform Version 3.6.3 - S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0

 ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** For S32K312, please use this correct clock HSE to AIPS clock should be ½. Please make these changes in the below all example code clock setting. HSE clock to 60 MHZ.   S32K312 PIT BTCU ADC-1 BCTU_ADC_DATA_REG DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-BTCU-ADC-1-BCTU-ADC-DATA-REG-DMA-DS3-5/ta-p/1787778 S32K312 UART Transmit & Receive Using DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-UART-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1787799 S32K312 EIRQ Interrupt :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-EIRQ-Interrupt-DS3-5-RTD300/ta-p/1787860 S32K312 SPI Transmit & Receive Using DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SPI-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1787856 Example S32K31 SPI multiple packet Transmit & Receive : solution for DMA Cache issue :- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K31-SPI-multiple-packet-Transmit-amp-Receive-solution/ta-p/2130091 Example S32K312 SPI Transmit & Receive Using Polling DS3.5 RTD300 :-- Example S32K312 SPI Transmit & Receive Using Polling DS3.5 RTD300 - NXP Community Example S32K312 SPI Transmit & Receive Using Interrupt DS3.5 RTD300 :-- Example S32K312 SPI Transmit & Receive Using Interrupt DS3.5 RTD300 - NXP Community S32K312 CAN Transmit & Receive Using Polling mode :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-Polling-mode-DS3/ta-p/1789191 S32K312 CAN Transmit & Receive Using MB & FIFO DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-amp-FIFO-DMA/ta-p/1789196 S32K312 ADC :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-ADC-DS3-5-RTD300/ta-p/1789282 S32K312 Switch Debouncing :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Switch-Debouncing-DS3-5-RTD300/ta-p/1789290 S32K312 UART Freemaster :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-UART-Freemaster-DS3-5-RTD300/ta-p/1789306 S32K312 PIT BTCU parallel ADC FIFO DMA  :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-BTCU-parallel-ADC-FIFO-DMA-DS3-5-RTD300/ta-p/1789908 S32K312 placing variables in DCTM & code in ICTM  :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-placing-variables-in-DCTM-amp-code-in-ICTM-DS3-5/ta-p/1790101 Example S32K312 Standby mode & Standby RAM and PAD keeping DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Standby-mode-amp-Standby-RAM-and-PAD-keeping-DS3/ta-p/1797713 Example S32K312 SWT DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SWT-DS3-5-RTD300/ta-p/1800559 Example S32K312 Printf Semihosting DS3.5 RTD300 :--- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Printf-Semihosting-DS3-5-RTD300/ta-p/1801354 Example S32K312 I2C Transmit & Receive Using DMA DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-I2C-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1801357 Example S32K312 HARDFAULT Handling Interrupt DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259 Example S32K312 Bootloader to Application Jump DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Bootloader-to-Application-Jump-DS3-5-RTD300/ta-p/1809810 Example S32K312 PIT timer Toggle LED DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-timer-Toggle-LED-DS3-5-RTD300/ta-p/1809932 Example S32K312 HARDFAULT Interrupt Handling using a script DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Interrupt-Handling-using-a-script-DS3/ta-p/1818507 Example S32K312 UART Transmit & Receive Using Interrupt DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-UART-Transmit-amp-Receive-Using-Interrupt-DS3-5/ta-p/1818775 Example S32K312 CAN Transmit & Receive Using MB Interrupt DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-Interrupt-DS3/ta-p/1818790 Example S32K312 STANDBY wake up using CAN-0-RX and GPIO Switch DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-STANDBY-wake-up-using-CAN-0-RX-and-GPIO-Switch/ta-p/1891411 Example S32K312 STANDBY wake up using RTC DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-STANDBY-wake-up-using-RTC-DS3-5-RTD300/ta-p/1930115 S32K312 : ADC Clock selection :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-ADC-Clock-selection/ta-p/1997759 Example IP S32K312 PWM ICU using EMIOS Custom IRQ DS3.5 RTD300 :-- Example IP S32K312 PWM ICU using EMIOS DS3.5 RTD300 - NXP Community Example IP S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300 :-- Example IP S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300 - NXP Community Example IP S32K312 EMIO PWM Generation & Duty capture using Polling DS3.5 RTD300 :-- Example IP S32K312 EMIO PWM Generation & Duty capture using Polling DS3.5 RTD300 - NXP Community Example S32K312 Continuous SPI Transmit & Receive Using DMA DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Continuous-SPI-Transmit-amp-Receive-Using-DMA/ta-p/2024597 S32K312 : HSE Demo project :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-HSE-Demo-project/ta-p/2112562 S32K312 : FS26 Watchdog trigger using the SBC_FS26 CDD :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-FS26-Watchdog-trigger-using-the-SBC-FS26-CDD/ta-p/2161357

******************************************************************************************************* * Detailed Description: This demo showcases how to use eMIOS in Input Capture mode with DMA. It demonstrates how timestamp data from captured input signals is stored and how a GPIO toggle provides a simple visual confirmation that the interrupt is being triggered as expected.   * eMIOS Pwm: Configures EMIOS 0 Channel 1 as OPWMB (Output Pulse Width Modulation Buffered). This channel generates a waveform that will be captured by Channel 9 * eMIOS Icu with DMA: Configures EMIOS 0 Channel 9 in ICU_MODE_TIMESTAMP using SAIC (Single Action Input Capture) mode. This channel captures the timestamps of the waveform generated by Channel 1. After a predefined number of captures, a DMA interrupt is triggered. ******************************************************************************************************* * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Debugger: S32DS 3.6.2, OpenSDA * Target: internal_FLASH *******************************************************************************************************

The S32K3 family of 32-bit AEC-Q100 qualified MCUs combines a scalable family of Arm® Cortex-M7-based microcontrollers built on long-lasting features with a comprehensive suite of production-grade tools. S32K3 MCUs are included in NXP’s Product Longevity Program, guaranteeing a minimum of 15 years of assured supply. The S32K3 offers dedicated peripherals set for rapid motor control loop implementation: enhanced Modular IO Subsystem(eMIOS), Logic Control Unit (LCU), TRGMUX, BodyCross-triggering Unit (BCTU), Analog to Digital Converter(ADC), and Analog Comparator (CMP). The comprehensive motor control ecosystem based on Automotive Math and Motor Control Library(AMMCLib) set, FreeMASTER with Motor Control ApplicationTuning (MCAT) tool and Model-Based Design Toolbox (MBDT) helps to enable S32K3 MCU in wide range of motor control use cases. The table below points to the articles with more detailed description each of S32K3 motor control use cases, hardware description, links to appropriate application notes and their addendums, and software repositories.  Device HW Article S32K344       MCSPTE1AK344 12 V development kit engineered for 3-phase PMSM and BLDC motor control applications     FOC with dual shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with dual shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API.    FOC with single shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with single shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The single shunt current measurement is advanced technique that allows decrese the cost of Bill of Material (BOM). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API.    FOC integrated with FreeRTOS Article focuses on integration of motor control software (based on FOC with dual shunt current measurement) and Real Time Operating System (FreeRTOS). The available example code is based ANSI-C  code and uses RTD drivers with low-level non-Autosar API.    Six-step commutation control. Article focuses on solution based Six-step commutation (6-step) technique (typically used for 3-phase BLDC motors) with Hall position sensor and without any position sensor (sensorless). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with low-level non-Autosar API.    Note: the list of use cases cannot cover all combinations of MCU, current measurement scenario, control technique and sensor inputs, but should work as a base reference for most common configurations. This list is not final, please follow this acticle to be notified about updates with new use cases.