S32K ナレッジベース

ディスカッション

******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive a CAN message Baudrate to is set to 500kbps. In this config, RXFIFO is used to receive a messages. 16 filter elements are defined in the RXFIFO table. Both standard and extended IDs are used. DMA is enabled in component inspector to read RXFIFO. MB10 is moreover used to receive a message with given standard ID and MB11 is used to transmit a message upon button press. The callback function is installed as well and is it called each time message is received in MB10, RXFIFO or message is transmitted. Note: EVB must be powered by 12V to have SBC's CAN transceiver active * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K144UAVLL 0N57U * Target: Debug_FLASH * EVB connection: PCAN-View with PCAN-USB Pro connected to CAN port J13 * Compiler: S32DS.ARM.2018.R1 * SDK release: S32SDK_S32K1xx_RTM_3.0.0 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 Petr Stancik Initial version *******************************************************************************/

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 25 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 16 channels, ADC1 9 channels. PDBs are set to back-to-back mode to perform chain conversion. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 channels ADC ch12 is selected, as it is connected to trimmer on the EVB. DMA is used to read result into single buffer, and DMA callbacks are issued to indicate end of transfer for each ADC module. Within those callbacks PTE14 and PTE15 is toggled. PDB0 output pulse is generated on the PTE16 to indicate start of ADC measurement. This is done periodically at LPIT ch0 rate, which is set to 30us. The ADC0 ch0 result is used to dim LEDs. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K144UAVLL 0N57U * Target: Debug_FLASH * EVB connection: * Compiler: S32DS.ARM.2018.R1 * SDK release: S32SDK_S32K1xx_RTM_3.0.0 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 May-04-2019 Petr Stancik Initial version *******************************************************************************/

Hi, If you try to compile the sample project within S32K14X_MCAL4_2_RTM_1_0_0, you should take care of the command if you use Linaro. After you set the environment of compiling and run the command under command window, you should enter "launch.bat MODE=USER TOOLCHAIN=linaro" NOT "launch.bat MODE=USER TOOLCHAIN=LINARO" The command is case sensitivity. Hope you can compile the project successfully. Cheers! Oliver

Hello, NXP does a big change on document structure. Generally, you can find pin assignment table, interrupt mapping and memory map table in RM. But now, these information change to Excel files and attached in RM. For example on S32K. You will find the words in RM, like 'For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.' Then, please go to attachment tab of your PDF file viewer, like Adobe Acrobat Reader DC. These steps are also fit for MPC57xx , S32R family. Cheers! Oliver

******************************************************************************** Detailed Description: Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN module to wake up MCU from STOP mode using SDK. Wake up by Timeout and wake up by Match events are enabled. Also pin interrupt can be used to exit STOP mode. So MCU enters STOP mode by pressing SW3 button. MCU exits STOP mode when one of following happens: - no CAN message comes in 8sec (CAN PN timeout event) - message with standard ID 0x554 or 0x555 comes (CAN PN match event) - SW2 button is pressed (PTC12 interrupt) In run mode blue LED is dimming and the rate is different for each wakeup event ------------------------------------------------------------------------------ Test HW: S32K116EVB-Q48 MCU: PS32K116LAM 0N96V Compiler: S32DS.ARM.2.2 SDK release: S32SDK_S32K1xx_RTM_3.0.0 Debugger: Lauterbach, OpenSDA Target: internal_FLASH ********************************************************************************

******************************************************************************************************* Detailed Description: Configures the MCU to run system clock from XOSC. LPUART1 is set to respond to LIN header sent from master. Based on ID received the LPUART1 either receive frame's data and compare checksum or publish requested data with calculated checksum. Enhanced checksum is used. Interrupt is used for RX and TX operation and 2 versions of interrupt routine are available. VER 1 ... during response transmission receiver disabled and transmit interrupt enabled VER 2 ... during response transmission receiver is kept enabled ------------------------------------------------------------------------------ Test HW: S32K116 EVB-Q048 MCU: PS32K116LAM 0N96V Fsys: 40MHz Debugger: Lauterbach Target: internal_FLASH ******************************************************************************************************

Hi, ARM Cortex-M have a DWT (Data Watchpoint and Trace) unit implemented, and it has a nice feature in that unit which counts the execution cycles. The DWT is usually implemented on most Cortex-M3, M4 and M7 devices, including e.g. the NXP S32K14x. Attachment is the sample project on S32K142 to measure the running time of a function. Password of extraction is nxp. Enjoy the measuring! Cheers! Oliver BTW, Measure the running time of one function on PowerPC could also be gotten through the link.

******************************************************************************************** * Detailed Description: * LPIT_ch0 triggers DMA_ch0 periodically (1ms). * Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO. * There are 8 minor loops per one major loop (64 bytes in 8ms). * LPSPI1 sends two 32bit frames every 1ms. * LPSPI1 RX data are masked, they are not stored in the RX FIFO. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144 0N57U * Debugger: S32DS 2.2, OpenSDA * Target: internal_FLASH ********************************************************************************************

******************************************************************************** Detailed Description: Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN module to wake up MCU from STOP mode. Wake up by Timeout and wake up by Match events are enabled. Also pin interrupt can be used to exit STOP mode. So MCU enters STOP mode by pressing SW3 button. MCU exits STOP mode when one of following happens: - no CAN message comes in 8sec (CAN PN timeout event) - message with standard ID 0x554 or 0x555 comes (CAN PN match event) - SW2 button is pressed (PTC12 interrupt) In run mode blue LED is dimming and the rate is different for each wakeup event ------------------------------------------------------------------------------ Test HW: S32K144 EVB-Q100 MCU: FS32K144UAVLL 0N57U Fsys: 160MHz Debugger: Lauterbach, OpenSDA Target: internal_FLASH ********************************************************************************

Example of usage of AIPS-lite, Protects the access to GPIO port. This example can be used with UART terminal, 115200 bps. The interface menu shows like this: AIPS example has started Please press 0 + enter to set red LED in GPIO port Please press 1 + enter to set red LED in GPIO port Please press 2: GPIO peripheral will only accept accesses from trusted master, M0 (Core) is set as untrusted when a write access, AIPS cannot longer be modified from core and a reset will occur in the next GPIO access Please press 3: GPIO access is write protected, any write access to GPIO will produce a hard fault

******************************************************************************** * Detailed Description: * RAM self-test is performed after reset in startup_S32K144.s file. * The RAM self-test should be executed right after reset, so it does not destroy * data loaded to RAM by init functions. The code is inserted after * initialization of core registers. RAM initialization is commented out because * the same operation is done by the self-test. * The test flow is: * 1. Write pattern 0x55AA55AA to first word in RAM * 2. Read the data back * 3. Compare the data and increment error counter if not equal * 4. Write inverse pattern 0xAA55AA55 to first word in RAM * 5. Read the data back * 6. Compare the data and increment error counter if not equal * 7. Clear the first word in RAM to leave whole RAM erased to ‘0’ at the end of test * This procedure is repeated for whole RAM. * If the error counter is different from zero at the end, the program stays in * endless loop until watchdog reset. * * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K144UAVLL 0N57U * Fsys: Default * Debugger: Lauterbach Trace32 * Target: internal_FLASH * ********************************************************************************

******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************

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******************************************************************************** Detailed Description: This example shows SRAM ECC injection. By default, a double-bit ECC error is injected on read access of a location in SRAM_U region. This can be changed with the SRAM_U and DOUBLE_BIT macros. The errors can be detected by both the ERM and MCM modules and the corresponding interrupts can be called. Although only ERM is needed, for demonstration purposes, the MCM interrupt is enabled as well with a lower priority than the ERM interrupts. The ERM interrupts that are called first disable the injection mechanism so that subsequent errors can not be detected during a stack read access. The default S32 Design Studio start_up file copies the vector table to the SRAM_L region. To be able to inject ECC errors in this SRAM region and call the interrupts, the copying is disabled by __flash_vector_table__ symbol declared in the start_up.h file and defined in the S32K144_64_flash linker file. -------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 Target: internal_FLASH ********************************************************************************

******************************************************************************** Detailed Description: This example shows the use of SRAM retention after SW reset. The SW reset is triggered by pressing the SW3 button on the S32K144 EVB The reset is delayed in RCM module: 514 LPO cycles. In the RCM interrupt, SRAMU_RETEN and SRAML_RETEN are cleared allowing to retain SRAM data during the reset. After software reset, SRAMU_RETEN and SRAML_RETEN are set to1 to allow accesses to SRAM. During software initialization in the startup_S32K144.S, ECC RAM initialization is skipped. After that, we can check the written data before reset are still placed in the SRAM. ------------------------------------------------------------------------------ Test HW: S32K144EVB-Q100 MCU: S32K 0N57U Debugger: S32DSR1 ********************************************************************************

特集記事

The S32K3 family of 32-bit AEC-Q100 qualified MCUs combines a scalable family of Arm® Cortex-M7-based microcontrollers built on long-lasting features with a comprehensive suite of production-grade tools. S32K3 MCUs are included in NXP’s Product Longevity Program, guaranteeing a minimum of 15 years of assured supply. The S32K3 offers dedicated peripherals set for rapid motor control loop implementation: enhanced Modular IO Subsystem(eMIOS), Logic Control Unit (LCU), TRGMUX, BodyCross-triggering Unit (BCTU), Analog to Digital Converter(ADC), and Analog Comparator (CMP). The comprehensive motor control ecosystem based on Automotive Math and Motor Control Library(AMMCLib) set, FreeMASTER with Motor Control ApplicationTuning (MCAT) tool and Model-Based Design Toolbox (MBDT) helps to enable S32K3 MCU in wide range of motor control use cases. The table below points to the articles with more detailed description each of S32K3 motor control use cases, hardware description, links to appropriate application notes and their addendums, and software repositories. Device HW Article S32K344 MCSPTE1AK344 12 V development kit engineered for 3-phase PMSM and BLDC motor control applications FOC with dual shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with dual shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar complient API or low-level non-Autosar API. FOC with single shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with single shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The single shunt current measurement is advanced technique that allows decrese the cost of Bill of Material (BOM). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar complient API or low-level non-Autosar API. FOC integrated with FreeRTOS Article focuses on integration of motor control software (based on FOC with dual shunt current measurement) and Real Time Operating System (FreeRTOS). The available example code is based ANSI-C code and uses RTD drivers with low-level non-Autosar API. Six-step commutation control. Article focuses on solution based Six-step commutation (6-step) technique (typically used for 3-phase BLDC motors) with Hall position sensor and without any position sensor (sensorless). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with low-level non-Autosar API. Note: the list of use cases cannot cover all combinations of MCU, current measurement scenario, control technique and sensor inputs, but should work as a base reference for most common configurations. This list is not final, please follow this acticle to be notified about updates with new use cases.

S32K ナレッジベース

S32K Knowledge Base

ディスカッション

Example S32K144 FlexCAN RXFIFO DMA S32DS.ARM.2018.R1

Example S32K144 PDB ADC DMA S32DS.ARM.2018.R1

Compile the sample project within MCAL, like S32K14X_MCAL4_2_RTM_1_0_0

How to get pin assignment, interrupt mapping and memory map details

Example S32K116 FlexCAN PN STOP S32DS.ARM.2.2

Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2

Measure the running time of one function on S32K

Example S32K144 LPIT DMA LPSPI

Example S32K144 FlexCAN Pretended Networking STOP mode test S32DS.ARM.2.2

S32K LPUART hardware flow control

S32K144 ISELED + Touch Sensor Demo

SENT receiver for S32K118 Design Studio

Uart to SENT protocol transmitter

aips_demo_s32k118.zip

RAM March c test assembly files and example project for S32K118 (GCC compiler)

Example S32K144 RAM selftest simple S32DS 2018.R1

Example S32K144 WDOG RCM interrupt

some useful tips about S32DS for ARM v2018.R1 IDE and S32K1xx development

Example S32K14x SRAM ECC Injection

Example S32K144 RAM Retention S32DS.R1

S32K3 Motor control SW examples