**************************************************************************************************** * Detailed Description:   * * The Flexio I2C driver provides an optional configuration parameter for reducing the number of DMA interrupts * required for transmission that are configured with DMA Optimize option. Instead of being interrupted after each * end of transmitting or receiving a data block or data amount larger than 13 bytes, only one interrupt will be raised to * stop frame and inform to user that the transmission was done. * * More details can be found in "RTD_I2C_UM.pdf", the chapter 3.6.3 FLEXIO DMA Optimize. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 SCH-53148 REV B2 * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Connections： * FXIO_D10_SCL (J4.19) - LPI2C1_SCL (J3.24) * FXIO_D11_SDA (J4.17) - LPI2C1_SDA (J3.27) ***************************************************************************************************/ Test Result: image.png  

******************************************************************************************** * Test HW: S32K312 EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.6.2 * SDK release: RTD 6.0.0 QLP04 * Debugger: PE Micro * Target: Internal_FLASH ******************************************************************************************** The objective of this demo application is to generate an interrupt and wakeup using the single GPIO. In this application, USR_SW5 (PTB26) in S32K312_Q172 EVB is used both as an interrupt source in RUN mode and as a wake‑up source from STANDBY mode.   Thanks & regards, Krishnakumar V

This example project will show user how to use and configure the basic functionalities of WKPU + GPT RTC API.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) or S32K344MINI-EVB * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & RTC units for wake-up. The RTC is present in always ON domain, hence available in RUN mode as well as in STANDBY mode. Julin_AragnM_0-1771625665539.png   The chip contains one instance of RTC (Real Time Clock) timer and API (Autonomous Periodic Interrupt) timer, where both can perform 32-bit comparisons. Both RTC and API timers can generate interrupts as well as wake-up from low power modes. The following figure highlights the path for RTC API wake-up. Please refer to Chapter 69.3.2 API functional description from the S32K3XX reference manual (Rev. 12) for further information. Julin_AragnM_1-1771625661011.png   The routine waits for SW5 to be pressed, then: Turns off the green LED Switches CORE_CLK to Option C - Boot Standby mode (CORE_CLK @ 24 MHz). Initializes the ICU driver. Configures RTC_API channel (WKPU0) Initializes GPT module. Starts timer and sets RTC_API_TIME. Enters standby. After the period defined, RTC API generates an interruption and MCU wakes up. After wake-up, MCU resets and polls for SW5 to be pressed again. The RTC API value can be changed with RTC_API_TIME definition. This example is provided as is with no guarantees and no support.

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected * to enable an external debugger. * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMAC0 clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K389_gptp_ds, SW32K3xx_M7_gPTP_1.1.0_CD01_D2602) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ----------------------------------------------------------------------------- * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> * <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

**************************************************************************************************** * Detailed Description: * * SW triggered conversion of ADC0 internal channel 50 (ANAMUX_OUT). * ANAMUX is used for internal supply monitoring. * Supply to be monitored is configured using DCMRWF1 register. * * PIT is configured to generate interrupt each second then ADC conversion for selected supply is * SW started and measured result is printed to the UART interface * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 Rev B * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Serial: 115200, 8N1 ***************************************************************************************************/ Terminal output PetrS_0-1771351094333.png

S32K1 vdd falling low voltage POR clear situation 1. Abstract This document primarily aims to explain the situation where the POR flag in the RCM_SSRS of the S32K1 chip is cleared, and to explain the setting status of the reset pin and the POR and LVD bits when VDD is powered down. This article is written because some customers, when using the RCM_SSRS reset flag to determine the corresponding RAM initialization conditions, have made incomplete considerations, leading to component failures in actual projects. They mistakenly believe that as long as the SSRS POR flag is not cleared by software writing a 1 after power-on, the POR bit will remain indefinitely. In reality, even after power-on, if subsequent power fluctuations cause VDD to drop to LVD/LVR and trigger a reset, the POR flag may still be automatically cleared by the chip.   2. Document content This article mainly categorizes VDD power-down scenarios into three main types: (1) VDD drops below the minimum LVR value but above VPOR, and then power is  back to normal VDD. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. (2) VDD drops below LVD, above LVR, and LVDRE=0. In this case, reset flag POR=1 and LVD=1 in RCM_SSRS. (3) VDD drops below LVD, above LVR, and LVDRE=1. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. The schematic diagram is as follows: kerryzhou_0-1769060181626.png   3. Test result on S32K116 board kerryzhou_1-1769060181995.png   kerryzhou_2-1769060182346.png   kerryzhou_3-1769060182721.png   kerryzhou_4-1769060182767.png  

This is set of S32K389EVB-Q437 demo projects. S32K389_GPIO_RTD6d0_S32DS3d6d2 S32K389_LPUART_RTD6d0_S32DS3d6d2 S32K389_FlexCAN_RTD6d0_S32DS3d6d2 S32K389_PFLASH_RTD6d0_S32DS3d6d2 S32K389_ADC_RTD6d0_S32DS3d6d2 S32K389_eMIOS_GPT_RTD6d0_S32DS3d6d2 S32K389_LowPower_RTD6d0_S32DS3d6d2 Examples are based on S32K3 RTD version 6.0 and created in S32DS version 3.6.2

NXP has ported FreeRTOS SMP (V11.1.0) to the S32K389. Many customers are interested in how to enable the FreeRTOS SMP on the S32K3xx. The demo is implemented as a single project with a single linker file and a single ELF file. Demo SW/HW Environment: 1. S32DS3.6.4 2. RTD7.0 3.SW32K3_FreeRTOS_11.1.0_7.0.0_CD1_HF1_D2511_DesignStudio_updatesite 4. S32K389 EVB  Demo Code Key Features: 1.FreeRTOS SMP is running on the S32K389 with all cores active. 2.DTCM is used as the task stack. 3.The hardware semaphore (SEMA42) is enabled in FreeRTOS. 4.XRDC is enabled so that each core has a unique core ID for semaphore operations. 5.CAN0 runs on Core0, and CAN4 runs on Core2. 6.LPUART11 is used to print debug information. All cores can output their own messages via LPUART11.  Disclaimer: The code is provided as demo code. NXP makes no commitment regarding its quality.  

Lauterbach FCCU_Utility plugin - S32K3xx MPC57xx_FCCU_Utility_rev0.pdf This Lauterbach debugger plugin alows user to use FCCU configurations directly from debugger interface. Such will speed up development and will not require to recompile and program project each time FCCU configuration is changed. FCCU NCF_TOE1.png  The supplied document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for S32K3xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. In such case this debugger plugin could be of a great value for various use cases like FA or debugging in development. Best regards, Peter

This example project will show user how to use and configure the basic functionalities of WKPU + SIUL2.  ------------------------------------------------------------------------------ * Test HW: S32K312EVB-Q172 (SCH-50892 REV B) * MCU: S32K312 * IDE: S32DS v3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up and defines a section in linker file for 32KB of Standby RAM. How to use Standby RAM? Modify the linker file to separatethe 32KBstandby RAM(0x2040 0000 ~0x2040 8000) from int_sram memory region, and place standby .bss and .data or .text sections into the new region as well as adjust the link address symbols for customized initialization during startup. Initialize the standby RAM only if it’s Power-On Reset. Use key word attribute to define the variable/function in relevant memory section. Counter variable is placed in standby ram section: __attribute__ ((section (".sram_standby_bss"))) volatile int RunStandbyCounter0 = 0; Linker file (.ld) must be modified accordingly. Standby sections and link address symbols must be placed: MEMORY { int_pflash : ORIGIN = 0x00400000, LENGTH = 0x001D4000 /* 2048KB - 176KB (sBAF + HSE)*/ int_dflash : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128KB */ int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */ int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0000F000 /* 60KB */ int_stack_dtcm : ORIGIN = 0x2000F000, LENGTH = 0x00001000 /* 4KB */ int_standbysram : ORIGIN = 0x20400000, LENGTH = 0X00000100 /* standby ram 256B*/ int_sram : ORIGIN = 0x20400100, LENGTH = 0x00007E00 /* 32KB - 0x100, needs to include int_sram_fls_rsv*/ int_sram_fls_rsv : ORIGIN = 0x20407F00, LENGTH = 0x00000100 int_sram_no_cacheable : ORIGIN = 0x20408000, LENGTH = 0x00007F00 /* 32KB , needs to include int_sram_results */ int_sram_results : ORIGIN = 0x2040FF00, LENGTH = 0x00000100 int_sram_shareable : ORIGIN = 0x20410000, LENGTH = 0x00008000 /* 32KB */ ram_rsvd2 : ORIGIN = 0x20418000, LENGTH = 0 /* End of SRAM */ } ... .sram_standby (NOLOAD): { . += ALIGN(4); *(.sram_standby_bss) } > int_standbysram ... __STANDBY_SRAM_START = ORIGIN(int_standbysram); __STANDBY_SRAM_SIZE = LENGTH(int_standbysram); Note 1: RAM ECC must be initialized only if it’s Power-on Reset. Note 2: CM7 CPU D-Cache MUST be disabled to use the Standby RAM area. Or set the standby RAM(0x2040 0000 ~0x2040 8000) as non-cacheable in MPU configuration. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Disables D-Cache. Initializes RAM ECC (if reset was Power-on Reset). Adds +1 to the standby counter placed in Standby RAM. Switches core clock to FIRC. Initializes the WKPU instance. Configures WKPU42 (PTB19). Enters standby. If SW6 is pressed, MCU will perform a software reset through the Power_Ip_PerformReset() API. After wake-up, MCU resets and polls for SW5 to be pressed again. In this application, LPUART6 (connected to USB OpenSDA interface) is enabled and will show previous reset reason (external reset, power-on reset, wakeup, functional reset), as well as printing standby counter between resets/standby cycles. Connect a USB cable to J40, and open a Serial terminal on PC for the serial device with these settings:   9600 baud rate   No parity   One stop bit  No flow control   After either a SW reset, or a wake-up cycle, the standby counter will increase. If a destructive reset or Power-on Reset is asserted, the counter is reset.  Snag_147e19f.png   This example is provided as is with no guarantees and no support.

This example project will show user how to use and configure the basic functionalities of ICU (WKPU) + DIO (GPIO).   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up. This is the simplest WKPU example. Pin PTB19 (WKPU42) is configured for wake-up.  The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Turns off green LED Switch system clock to FIRC (Option C - Boot Standby mode @24MHz). Initialize the Icu driver. Configures WKPU42 (PTB19). Enters standby. After pressing SW6, MCU wakes up, resets and polls for SW5 to be pressed again. This example is provided as is with no guarantees and no support.

This example project will show user how to use and configure the basic functionalities of ICU (WKPU) + CAN.   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This project configures both Can_43_FLEXCAN and CanIf modules for CAN communication, along with the ICU (WKPU) module for wake-up. Transmission is done via POLLING, while reception is configured via INTERRUPT.  Tx MB is set to STD ID 123h. Acceptance mask is set to 0x0 (accept all IDs). CAN messages are sent using Can_43_FLEXCAN_Write() and received using the CanIf_RxIndication() callback. After CanIf_bRxFlag is set, an ACK message is sent back. If TJA1153 transceiver is used, macro TJA1153_EVB_TRCV must be used. If not, use TJA1043_EVB_TRCV for standard transceiver initialization (CAN0_STB & CAN0_EN pins set to HIGH).  FlexCAN bitrate is calculated with: CAN bit timing calculator sheet. CAN classic (non-FD) 24Mhz clock 500Kbps 81.3% Sample Point Main routine: Waits for SW5 to be pressed, or for FlexCAN Rx interrupt. If SW5 is pressed, turns off green LED, disables FlexCAN and switches CORE_CLK to FIRC. It then configures PTA6 (CAN0_RX) for wakeup. If a CAN message is received (edge detect on PTA6), MCU wakes up and will enter main routine again. If a CAN frame is received, MCU will wake-up and wait for SW5 to be pressed again. Note: The first CAN frame may not be fully received since there will be some time for the MCU to warm up from STANDBY mode back to RUN mode, so the application may need to ignore the first CAN frame. Note 2: In order to test this example, another CAN node must be connected to CAN0_OUT. This example is provided as is with no guarantees and no support.

***************************************************************************** *Detailed Description: *This example will show you how to configure Wdg_fs23 Driver. *Sbc_fs23_InitDriver, Sbc_fs23_GoToInitState, Wdg_43_fs23_Init, Sbc_fs23_InitDevice initialize the Sbc device and external Wdg in SLOW MODE(This mode can e.g. be used during system startup/initialization phase). *Sbc_fs23_InitDevice release FS0B, according to the configuration in Sbc_fs23 WatchdogConfig tab: Release safety outputs after init *Sbc_fs23_TimeDelay delay for an amount of time, allow Gpt ISR to trigger watchdog externally. *Wdg_43_fs23_SetMode(WDGIF_FAST_MODE); switch Wdg operation mode to FAST MODE(This mode can e.g. be used during normal operations of the ECU). *Wdg_43_fs23_SetTriggerCondition(10000U); sets a new timeout value to 10 seconds, during which Wdg_fs23_Cbk_GptNotification0 continuously refresh the watchdog. *To demonstrate the watchdog timeout, Wdg_43_fs23_SetTriggerCondition was not called again to set a new timeout value, and Wdg_fs23_Cbk_GptNotification0 no longer refreshed the watchdog. *The watchdog error counter(WD_ERR_CNT) continues to increase reached its maximum value(WD_ERR_LIMIT), causing fault error counter(FLT_ERR_CNT) to increment by 1. *FS23 eventually enters fail-safe mode because FLT_ERR_CNT >= max. At this point, it was observed that LEDs V1 (D7), V2 (D8), and V3 (D9) of KITFS23SKTEVM were turned off. *The SPI data between FS23 and S32K311 are captured and attached to the project. *------------------------------------------------------------------------------ *Test HW: * S32K31XEVB-Q100 Board SCH-55131 REV A P32K311HV 0P98C * KITFS23SKTEVM Dev-kit SCH-53096 REV B2 MFS2320BMBB1EP * My S32K31XEVB-Q100 has an onboard PFS2320A0L1W1, but Step 13/14 of AN14041 mention that A0 devices are not supported, so S32K311 communicate with the FS23 on the KITFS23SKTEVM. *Connections: KITFS23SKTEVM | S32K31XEVB-Q100 ------------------------------|-------------------- SPI_CSB J28-2 | J12-5(PTB-17) SPI_MOSI J29-2 | J12-7(PTB-16) SPI_SCK J31-2 | J12-11(PTB-14) SPI_MISO J32-2 | J12.9(PTB-15) VCC J6-1 | J40-15 GND J6-2 | J40-13 - KITFS23SKTEVM: SW1 - position 2-3 , J30 - ON, J26 5-6 ON, J26 9-10 ON . - Connect KITFS23SKTEVM Dev-kit and S32K3 MCU via on-board Arduino headers. *SDK: * S32K3 RTD 4.0.0 (SW32K3_S32M27x_RTD_R21-11_4.0.0_D2311_DS_updatesite.zip) * FS23 RTD 1.0.0 (S32K3xx_SBC_FS23_R21-11_1.0.0_D2508_DesignStudio_updatesite.zip) *Debugger: S32DS 3.5.8, OpenSDA/ PEmicro Multilink Universal FX *Target: internal_FLASH *Reference: * AN14041 FS23 quick start guide (Rev. 2.0 — 23 January 2025) * AN14129 FS23 implementation and behaviors (Rev. 2.0 — 13 December 2024) * FS23, Safety System Basis Chip (SBC) with Power Management, CAN FD and LIN Transceivers Data Sheet (Rev. 8.0 — 30 June 2025) * RTD_SBC_FS23_UM.pdf C:\NXP\S32DS.3.5\S32DS\software\PlatformSDK_S32K3\SW32K3_FS23_R21-11_1.0.0_D2312\Sbc_fs23_TS_T40D34M10I0R0\doc * RTD_WDG_43_FS23_UM.pdf C:\NXP\S32DS.3.5\S32DS\software\PlatformSDK_S32K3\SW32K3_FS23_R21-11_1.0.0_D2312\Wdg_43_fs23_TS_T40D34M10I0R0\doc * AUTOSAR_SWS_WatchdogDriver.pdf https://www.autosar.org/fileadmin/standards/R21-11/CP/AUTOSAR_SWS_WatchdogDriver.pdf * This example is migrated from Wdg_fs23_example_HLD_S32K344. The method of migrating refers to the video "2.S32DS CT MCAL demo porting K344 to K312 based on RTD500": https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Tools-Part-How-to-port-RTD-s-existing-MCAL-demo-to-other/ta-p/1966315 ***************************************************************************** Example_S32K311_SPI_Wdg_fs23_HLD_v0_0_S32DS358_RTD400 connections.jpg Example_S32K311_SPI_Wdg_fs23_HLD_v0_0_S32DS358_RTD400 saleae Logic 2.png

This example project will show user how to use and configure the basic functionalities of ICU (WKPU) + DIO (GPIO).   ------------------------------------------------------------------------------ * Test HW: S32K396-BGA-DC1 (SCH-55517 Rev B2) * MCU: S32K396 * IDE: S32DS3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PEMicro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up. This is the simplest WKPU example. Pin PTB19 (WKPU42) is configured for wake-up.  The routine waits for SW8 to be pressed, then turns off LED1, and: Switches core clock to FIRC (Mode C Boot default from Table 125.). Initializes the WKPU instance. Configures WKPU42 (SW4). Enters standby (or fast standby). After pressing SW4, MCU wakes up, resets and polls for SW8 to be pressed again. If FAST_STANDBY is selected, Wkup_FastWkupBootAddress() is entered and both LED2 & LED3 blink before jumping to reset handler for full initialization. This example is provided as is with no guarantees and no support.

***************************************************************************** *Detailed Description: *This example will show you how to configure Sbc_fs23 Driver. *It initialization of Sbc_fs23 with watchdog window disabled. The Sbc_fs23_InitDevice() must be done within the dedicated 256 ms INIT window. *It Disable regulator V2, then re-enable it again. FS0b pin is asserted due to V2 Undervoltage reaction setting configured in FailSafe Init Configuration tab. *If the example runs without errors, the D12 LED on S32K31XEVB-Q100 will light up Green; otherwise, it will light up Red. *The SPI data between FS23 and S32K311 are captured and attached to the project. *Use the analog input of a logic analyzer or an oscilloscope to monitor the signals of FS23_V2 (TP27) and FS23_FS0 (TP8) on the KITFS23SKTEVM board. *------------------------------------------------------------------------------ *Test HW: * S32K31XEVB-Q100 Board SCH-55131 REV A P32K311HV 0P98C * KITFS23SKTEVM Dev-kit SCH-53096 REV B2 MFS2320BMBB1EP * My S32K31XEVB-Q100 has an onboard PFS2320A0L1W1, but Step 13/14 of AN14041 mention that A0 devices are not supported, so S32K311 communicate with the FS23 on the KITFS23SKTEVM. *Connections: KITFS23SKTEVM | S32K31XEVB-Q100 ------------------------------|-------------------- SPI_CSB J28-2 | J12-5(PTB-17) SPI_MOSI J29-2 | J12-7(PTB-16) SPI_SCK J31-2 | J12-11(PTB-14) SPI_MISO J32-2 | J12.9(PTB-15) VCC J6-1 | J40-15 GND J6-2 | J40-13 - KITFS23SKTEVM: SW1 - position 2-3 , J30 - ON, J26 5-6 ON, J26 9-10 ON . - Connect KITFS23SKTEVM Dev-kit and S32K3 MCU via on-board Arduino headers. *SDK: * S32K3 RTD 4.0.0 (SW32K3_S32M27x_RTD_R21-11_4.0.0_D2311_DS_updatesite.zip) * FS23 RTD 1.0.0 (S32K3xx_SBC_FS23_R21-11_1.0.0_D2508_DesignStudio_updatesite.zip) *Debugger: S32DS 3.5.8, OpenSDA/ PEmicro Multilink Universal FX *Target: internal_FLASH *Reference Documentation: * AN14041 FS23 quick start guide (Rev. 2.0 — 23 January 2025) * AN14129 FS23 implementation and behaviors (Rev. 2.0 — 13 December 2024) * FS23, Safety System Basis Chip (SBC) with Power Management, CAN FD and LIN Transceivers Data Sheet (Rev. 8.0 — 30 June 2025) * RTD_SBC_FS23_UM.pdf C:\NXP\S32DS.3.5\S32DS\software\PlatformSDK_S32K3\SW32K3_FS23_R21-11_1.0.0_D2312\Sbc_fs23_TS_T40D34M10I0R0\doc * This example is migrated from Sbc_fs23_example_HLD_S32K344. The method of migrating refers to the video "2.S32DS CT MCAL demo porting K344 to K312 based on RTD500": https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Tools-Part-How-to-port-RTD-s-existing-MCAL-demo-to-other/ta-p/1966315 ***************************************************************************** * Revision History: * Ver Date Author Description of Changes * 0.0 10-26-2025 Robin Shen Initial version * 0.1 11-21-2025 Robin Shen Upgrade FS23 RTD 1.0.0 from S32K3xx_SBC_FS23_R21-11_1.0.0_DS_updatesite_D2402_updated_D250115.zip to S32K3xx_SBC_FS23_R21-11_1.0.0_D2508_DesignStudio_updatesite.zip ***************************************************************************** Example_S32K311_SPI_Sbc_fs23_HLD_v0_1_S32DS358_RTD400 Connections.jpg Example_S32K311_SPI_Sbc_fs23_HLD_v0_1_S32DS358_RTD400 saleae Logic 2.png

**************************************************************************************************** * Detailed Description: * This code demonstrates how to inject an ECC (Error Correction Code) fault into either DTCM0 * (Data Tightly Coupled Memory) or SRAM0 using the EIM (ECC Injection Module). * * When the processor reads corrupted data from DTCM0 or SRAM0, an ECC error is detected, resulting in: * - A Bus Fault exception raised by the core. * - An error report generated by the ERM (Error Reporting Module), which can also trigger an interrupt. * * By default, the ERM interrupt has a lower priority than the Bus Fault exception. In this example, * the Bus Fault exception priority is intentionally lowered so that the ERM interrupt is serviced first. * This ensures the system can respond to the ERM interrupt before the core's Bus Fault handler executes. * * IMPORTANT: The interrupt vector table must not reside in SRAM0 or DTCM0 when injecting an * uncorrectable ECC fault into these memories. Otherwise, the ECC fault would corrupt the vector * table during a fetch, leading to unpredictable behavior. * Always check the VTOR (Vector Table Offset Register) * to confirm the vector table location before performing ECC fault injection. * * Memory Selection: * You can select which memory to inject the ECC fault into using the following macros: * #define SRAM0 * #define DTCM0 *************************************************************************************************** * ------------------------------------------------------------------------------------------------* * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: NA * Debugger: Lauterbach Trace32 * Target: internal_FLASH ****************************************************************************************************

Hi everyone, Welcome to the NXP Tech Days 2025 training session AUT-T437: Hands - On Workshop: Explore Ethernet Integration on the S32K3 Microcontroller. My name is Alejandro Flores Triana (Alex) and I will be your guide during this conference. I am an Automotive Applications Engineer supporting different OEMs, Tier1s, Partners and other internal NXP teams on topics related to communication protocols (e.g. CAN, LIN, SPI, I2C, Ethernet, etc.). The idea of this session is for you to understand how to program the S32K3 Ethernet interface using NXP Real-Time Drivers (RTDs) – Autosar MCAL Layer. We will use a base project and together modify it to create a simple Ethernet application. Therefore, to be ready follow the steps below to get your environment up and running before the session. On your laptop, install the NXP Software environment described in the attached presentation: Hands - On Workshop: S32K3 Ethernet Prerequisites.   Once you have the NXP software environment installed, download the attached project: S32K344_ETH_MCAL_TechDays.exe.   Run the .exe project with administrator rights. Accept the license and install in the desired folder.   AlexTriana_0-1729298444699.png   AlexTriana_1-1729298444701.png   AlexTriana_2-1729298444703.png   Open the NXP Design Studio. Click File -> Import -> Existing Projects into Workspace. AlexTriana_3-1729298444705.png   Select root directory and browse the folder where you downloaded the project. AlexTriana_4-1729298444708.png   Select Copy projects into workspace. Then, click Finish. AlexTriana_5-1729298444713.png   Select the project. Click on the arrow next to the hammer. Click on Debug_FLASH. Picture1.png Then you are ready for the session! See you soon. Best Regards, Alejandro Flores Triana

This document provides a brief explanation of the Excel-based calculator developed to assist with the computation of TX Arbitration Start Delay as described in the S32K3 reference manual. Senlent_5-1760435008352.png The tool implements the formula provided in the datasheet, allowing users to input relevant parameters and automatically calculate the delay values. It is intended to support engineers in evaluating CAN transmission timing and optimizing arbitration performance in S32K3-based applications.   1.Fill in the clock and CBT and FDCBT configuration parameters according to your requirements. For example, we fill the parameters according Case 3: Senlent_2-1760432857467.png Senlent_0-1760432107988.png  Then we can get the TASD value for non-FD frames is 24.05. Senlent_4-1760433268477.png   Please note that this summary is not officially released by NXP. It is a personal summary for reference only. If there are any errors, please contact me.

****************************************************************************************************** * Detailed Description: These demos showcase how to configure the eMIOS module on the S32K3 series, highlighting various operational modes and their implementations using the RTD high-level drivers, commonly known as MCAL drivers. The implementations demonstrated in these examples follow the approach outlined in the community thread:  S32M27x/S32K3 – eMIOS Usage. * Connections:  VaneB_0-1759773423423.png ******************************************************************************************************* * Test HW: S32K31XEVB-Q100 * MCU: S32K311 * Debugger: S32DS 3.6.2, OpenSDA/ PEmicro Multilink Universal FX  * Target: internal_FLASH ******************************************************************************************************* * Important information:  The OPWMT channel does not support the notification function. In this mode, the Sn[FLAG] bit is only set upon an AS2 match, which defines the generation of a trigger event within the PWM period. As a result, OPWMT mode cannot support notifications based on signal edges. A bus exception may occur during the execution of Mcl_Init() if the eMIOS clock is not properly enabled. To avoid this issue, ensure that the eMIOS peripheral clock is activated in the configuration settings under: MCU driver → McuModuleConfiguration → McuModeSettingConf → McuPeripheral *******************************************************************************************************

**************************************************************************************************** * Detailed Description: * * - CMU errors cannot be injected by any means other than manipulating the CMU thresholds, * except for FXOSC_CLK, which can be physically disrupted on the PCB. * * - CMU_FC_0 (FXOSC_CLK) is configured for **synchronous interrupt** on both LFF and HFF CMU events. * - CMU_FC_3 (CORE_CLK) is configured for **asynchronous destructive reset** triggered only by the LFF event; the HFF event is ignored. * - CMU_FC_4 (CORE_CLK) is configured identically to CMU_3: **asynchronous destructive reset** on LFF only; HFF is ignored. * - CMU_FC_5 (HSE_CLK) can be configured by the HSE_B core only. * Refer to the Reference Manual rev.10, Figure 122. Frequency checking (FC) instances * * - The configuration must be identical in both the MCU MCAL driver and the Clock Configuration Tool (clock details). * - To inject a specific CMU error, define one of the following macros: `INJECT_CMU_0`, `INJECT_CMU_3`, or `INJECT_CMU_4`. * * Behavior After Destructive Reset: * - Following a destructive reset (either `MCU_CORE_CLK_FAIL_RESET` or `MCU_AIPS_PLAT_CLK_FAIL_RESET`), * execution will halt in the `while(wait)` loop. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: RTD 6.0.0 * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************