FRDM-A-S32K358 LwIP enablement with RTD 6.0.0.

Mapping between SPD eMCEM and DCM for S32K311, S32K312, S32K314, S32K322, S32K324, S32K341, S32K342, S32K344.

**************************************************************************************************** * Detailed Description: * This example uses BIST and EMCEM drivers from SPD 1.0.6. * BIST and EMCEM can be enabled or disabled using macros. * * BIST runs immediately after a power-on reset and triggers an ST_DONE reset. * EMCEM initialization is only possible after a system reset without an attached debugger. * Therefore, wait loops (controlled by macros) are used to manage execution flow * for both BIST and EMCEM. * * Fault injection is selected via macros: * - FAULT_EMCEM_DCM_NCF_1_AD_EDC_ERR_OUT → handled via NMI * - FAULT_EMCEM_DCM_NCF_2_PRAM1_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_2_ITCM_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_3_PFO_CODE_ERR → FCCU alarm → (if TIMEOUT_PFO_CODE_ERR) → NMI * - FAULT_EMCEM_DCM_NCF_5_STCU_NCF → handled via FCCU alarm * - FAULT_EMCEM_DCM_NCF_7_SW_NCF_0 → FOSU Destructive reset * (read resetReason after reset, MCU_FCCU_FTR_RESET). * FOSU triggers as no FCCU reaction is configured for NCF_7 * while FCCU is enabled and reactions are configured for other faults. * * ------------------------------------------------------------------------------------------------ * MCU: S32K3x4EVB-Q257 * Fsys: 160 MHz PLL with 16 MHz crystal reference * Debugger: Lauterbach Trace32, S32DS IDE 3.6.5 * Target: internal_FLASH ****************************************************************************************************

/********************************************************************************************** * File main.c * Owner Daniel Martynek * Version 1.0 * Date May-12-2026 * Classification General Business Information ********************************************************************************************** * Detailed Description: * The code enables the data cache, reads a value from DFlash to load it into the cache, * then uses the LMEM interface to inspect and directly overwrite the corresponding cache line. * Finally, it reads the same address again through the CPU, which returns the modified value * from the cache instead of the original data stored in DFlash. * * In this simple setup, where only the data cache is enabled, the code executes from PFlash, * and the accessed data is located in DFlas — the cache line is unlikely to be re-evaluated. * Therefore, the CPU may consistently return the modified value - this behavior is not guaranteed. * ------------------------------------------------------------------------------------- * MCU: S32K142 * Fsys: 48MHz, FIRC * RTD: S32K1_RTD_3_0_0_QLP06_D2603_ASR_REL_4_7_REV_0000_20260320 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************

The attached spreadsheet provides mapping between EIM and DCM faults for the S32K3x1, S32K3x2, S32K344, S32K324, and S32K314 devices. Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K344 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions. * * Configuration: * - Updated pin configuration * - Modified FXOSC, PLLAUX + dividers * - Platform: added EMAC_0_IRQn interrupt * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Added DIO * * main.c * - Updated only the header * device.c * - No updates * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: MR-CANHUBK344 * MCU: S32K344 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: EMAC <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected to enable an external debugger. * * TJA1103-SDBR: * mode rev-RMII * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 1-2 * * Configuration: * - Updated pin configuration * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC1_SABRE <-> TJA1103-SDBR (rev-RMII mode) <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1120-SDBR: * mode RGMII-ID (both TXC/RXC), Master, Autonomous, XTAL * CONFIG 3 2-3 * CONFIG 5 1-2 * CONFIG 4,6 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1120-SDBR <-> Media converter TE-1402 (1G, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1103-SDBR: * mode RGMII-ID (both TXC/RXC) * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 100M * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1103-SDBR <-> Media converter TE-1402 (100M, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K388 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions except: jumper J361 must be closed. * - Soldering rework required to connect an external debugger. * See S32K388EVB-Q289_HW_User Manual_A3.pdf, chapter 15 (Errata). * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMACx clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K388_gptp_ds, S32K3xx gPTP Stack 1.0.0) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * --------------------------------------------------------------------------------------- * Test HW: S32K388EVB-Q289 SCH-88925 REV A, 700-88925 REV X1 * MCU: S32K388 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

**************************************************************************************************** * Detailed Description:   * * The Flexio I2C driver provides an optional configuration parameter for reducing the number of DMA interrupts * required for transmission that are configured with DMA Optimize option. Instead of being interrupted after each * end of transmitting or receiving a data block or data amount larger than 13 bytes, only one interrupt will be raised to * stop frame and inform to user that the transmission was done. * * More details can be found in "RTD_I2C_UM.pdf", the chapter 3.6.3 FLEXIO DMA Optimize. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 SCH-53148 REV B2 * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Connections： * FXIO_D10_SCL (J4.19) - LPI2C1_SCL (J3.24) * FXIO_D11_SDA (J4.17) - LPI2C1_SDA (J3.27) ***************************************************************************************************/ Test Result:  

******************************************************************************************** * Test HW: S32K312 EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.6.2 * SDK release: RTD 6.0.0 QLP04 * Debugger: PE Micro * Target: Internal_FLASH ******************************************************************************************** The objective of this demo application is to generate an interrupt and wakeup using the single GPIO. In this application, USR_SW5 (PTB26) in S32K312_Q172 EVB is used both as an interrupt source in RUN mode and as a wake‑up source from STANDBY mode.   Thanks & regards, Krishnakumar V

This example project will show user how to use and configure the basic functionalities of WKPU + GPT RTC API.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) or S32K344MINI-EVB * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & RTC units for wake-up. The RTC is present in always ON domain, hence available in RUN mode as well as in STANDBY mode.   The chip contains one instance of RTC (Real Time Clock) timer and API (Autonomous Periodic Interrupt) timer, where both can perform 32-bit comparisons. Both RTC and API timers can generate interrupts as well as wake-up from low power modes. The following figure highlights the path for RTC API wake-up. Please refer to Chapter 69.3.2 API functional description from the S32K3XX reference manual (Rev. 12) for further information.   The routine waits for SW5 to be pressed, then: Turns off the green LED Switches CORE_CLK to Option C - Boot Standby mode (CORE_CLK @ 24 MHz). Initializes the ICU driver. Configures RTC_API channel (WKPU0) Initializes GPT module. Starts timer and sets RTC_API_TIME. Enters standby. After the period defined, RTC API generates an interruption and MCU wakes up. After wake-up, MCU resets and polls for SW5 to be pressed again. The RTC API value can be changed with RTC_API_TIME definition. This example is provided as is with no guarantees and no support.

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected * to enable an external debugger. * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMAC0 clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K389_gptp_ds, SW32K3xx_M7_gPTP_1.1.0_CD01_D2602) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ----------------------------------------------------------------------------- * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> * <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

**************************************************************************************************** * Detailed Description: * * SW triggered conversion of ADC0 internal channel 50 (ANAMUX_OUT). * ANAMUX is used for internal supply monitoring. * Supply to be monitored is configured using DCMRWF1 register. * * PIT is configured to generate interrupt each second then ADC conversion for selected supply is * SW started and measured result is printed to the UART interface * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 Rev B * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Serial: 115200, 8N1 ***************************************************************************************************/ Terminal output

S32K1 vdd falling low voltage POR clear situation 1. Abstract This document primarily aims to explain the situation where the POR flag in the RCM_SSRS of the S32K1 chip is cleared, and to explain the setting status of the reset pin and the POR and LVD bits when VDD is powered down. This article is written because some customers, when using the RCM_SSRS reset flag to determine the corresponding RAM initialization conditions, have made incomplete considerations, leading to component failures in actual projects. They mistakenly believe that as long as the SSRS POR flag is not cleared by software writing a 1 after power-on, the POR bit will remain indefinitely. In reality, even after power-on, if subsequent power fluctuations cause VDD to drop to LVD/LVR and trigger a reset, the POR flag may still be automatically cleared by the chip.   2. Document content This article mainly categorizes VDD power-down scenarios into three main types: (1) VDD drops below the minimum LVR value but above VPOR, and then power is  back to normal VDD. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. (2) VDD drops below LVD, above LVR, and LVDRE=0. In this case, reset flag POR=1 and LVD=1 in RCM_SSRS. (3) VDD drops below LVD, above LVR, and LVDRE=1. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. The schematic diagram is as follows:   3. Test result on S32K116 board        

This is set of S32K389EVB-Q437 demo projects. S32K389_GPIO_RTD6d0_S32DS3d6d2 S32K389_LPUART_RTD6d0_S32DS3d6d2 S32K389_FlexCAN_RTD6d0_S32DS3d6d2 S32K389_PFLASH_RTD6d0_S32DS3d6d2 S32K389_ADC_RTD6d0_S32DS3d6d2 S32K389_eMIOS_GPT_RTD6d0_S32DS3d6d2 S32K389_LowPower_RTD6d0_S32DS3d6d2 Examples are based on S32K3 RTD version 6.0 and created in S32DS version 3.6.2

NXP has ported FreeRTOS SMP (V11.1.0) to the S32K389. Many customers are interested in how to enable the FreeRTOS SMP on the S32K3xx. The demo is implemented as a single project with a single linker file and a single ELF file. Demo SW/HW Environment: 1. S32DS3.6.4 2. RTD7.0 3.SW32K3_FreeRTOS_11.1.0_7.0.0_CD1_HF1_D2511_DesignStudio_updatesite 4. S32K389 EVB  Demo Code Key Features: 1.FreeRTOS SMP is running on the S32K389 with all cores active. 2.DTCM is used as the task stack. 3.The hardware semaphore (SEMA42) is enabled in FreeRTOS. 4.XRDC is enabled so that each core has a unique core ID for semaphore operations. 5.CAN0 runs on Core0, and CAN4 runs on Core2. 6.LPUART11 is used to print debug information. All cores can output their own messages via LPUART11.  Disclaimer: The code is provided as demo code. NXP makes no commitment regarding its quality.  

Lauterbach FCCU_Utility plugin - S32K3xx MPC57xx_FCCU_Utility_rev0.pdf This Lauterbach debugger plugin alows user to use FCCU configurations directly from debugger interface. Such will speed up development and will not require to recompile and program project each time FCCU configuration is changed.   The supplied document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for S32K3xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. In such case this debugger plugin could be of a great value for various use cases like FA or debugging in development. Best regards, Peter

This example project will show user how to use and configure the basic functionalities of WKPU + SIUL2.  ------------------------------------------------------------------------------ * Test HW: S32K312EVB-Q172 (SCH-50892 REV B) * MCU: S32K312 * IDE: S32DS v3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up and defines a section in linker file for 32KB of Standby RAM. How to use Standby RAM? Modify the linker file to separatethe 32KBstandby RAM(0x2040 0000 ~0x2040 8000) from int_sram memory region, and place standby .bss and .data or .text sections into the new region as well as adjust the link address symbols for customized initialization during startup. Initialize the standby RAM only if it’s Power-On Reset. Use key word attribute to define the variable/function in relevant memory section. Counter variable is placed in standby ram section: __attribute__ ((section (".sram_standby_bss"))) volatile int RunStandbyCounter0 = 0; Linker file (.ld) must be modified accordingly. Standby sections and link address symbols must be placed: MEMORY { int_pflash : ORIGIN = 0x00400000, LENGTH = 0x001D4000 /* 2048KB - 176KB (sBAF + HSE)*/ int_dflash : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128KB */ int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */ int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0000F000 /* 60KB */ int_stack_dtcm : ORIGIN = 0x2000F000, LENGTH = 0x00001000 /* 4KB */ int_standbysram : ORIGIN = 0x20400000, LENGTH = 0X00000100 /* standby ram 256B*/ int_sram : ORIGIN = 0x20400100, LENGTH = 0x00007E00 /* 32KB - 0x100, needs to include int_sram_fls_rsv*/ int_sram_fls_rsv : ORIGIN = 0x20407F00, LENGTH = 0x00000100 int_sram_no_cacheable : ORIGIN = 0x20408000, LENGTH = 0x00007F00 /* 32KB , needs to include int_sram_results */ int_sram_results : ORIGIN = 0x2040FF00, LENGTH = 0x00000100 int_sram_shareable : ORIGIN = 0x20410000, LENGTH = 0x00008000 /* 32KB */ ram_rsvd2 : ORIGIN = 0x20418000, LENGTH = 0 /* End of SRAM */ } ... .sram_standby (NOLOAD): { . += ALIGN(4); *(.sram_standby_bss) } > int_standbysram ... __STANDBY_SRAM_START = ORIGIN(int_standbysram); __STANDBY_SRAM_SIZE = LENGTH(int_standbysram); Note 1: RAM ECC must be initialized only if it’s Power-on Reset. Note 2: CM7 CPU D-Cache MUST be disabled to use the Standby RAM area. Or set the standby RAM(0x2040 0000 ~0x2040 8000) as non-cacheable in MPU configuration. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Disables D-Cache. Initializes RAM ECC (if reset was Power-on Reset). Adds +1 to the standby counter placed in Standby RAM. Switches core clock to FIRC. Initializes the WKPU instance. Configures WKPU42 (PTB19). Enters standby. If SW6 is pressed, MCU will perform a software reset through the Power_Ip_PerformReset() API. After wake-up, MCU resets and polls for SW5 to be pressed again. In this application, LPUART6 (connected to USB OpenSDA interface) is enabled and will show previous reset reason (external reset, power-on reset, wakeup, functional reset), as well as printing standby counter between resets/standby cycles. Connect a USB cable to J40, and open a Serial terminal on PC for the serial device with these settings:   9600 baud rate   No parity   One stop bit  No flow control   After either a SW reset, or a wake-up cycle, the standby counter will increase. If a destructive reset or Power-on Reset is asserted, the counter is reset.    This example is provided as is with no guarantees and no support.