S32K ナレッジベース

ディスカッション

Hello, NXP does a big change on document structure. Generally, you can find pin assignment table, interrupt mapping and memory map table in RM. But now, these information change to Excel files and attached in RM. For example on S32K. You will find the words in RM, like 'For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.' Then, please go to attachment tab of your PDF file viewer, like Adobe Acrobat Reader DC. These steps are also fit for MPC57xx , S32R family. Cheers! Oliver

Welcome to the S32K Microcontrollers forum. Get expert advice from the NXP developer community. Our support team also monitors these forums to provide answers and take your feedback. Anyone can read the discussions, but only registered NXP Community members can post questions and comments. Before you ask a question, please search the community to find if someone has already offered a solution. If you don’t see a solution, then ask the community your question. S32K Web page S32K Reference manual S32K Data sheet S32K Application notes and other documents S32K Evaluation Board S32 Design Studio IDE https://community.nxp.com/docs/DOC-334170

******************************************************************************** * Detailed Description: * * This example shows how to use the back-to-back mode of the PDB to trigger * sequence of ADC channels conversion. 4 PDB channel 0 pre-triggers/triggers are * generated upon single PDB SW trigger. The first trigger is started by the PDB, * no delay is used. Next 3 triggers start after corresponding acknowledgment is * received from ADC0. * * Converted data is used to change color of the EVB led based on Trimmer position. * * ------------------------------------------------------------------------------ * Test HW: FRDM-S32K144 * MCU: PS32K144HFVLL 0N77P * Fsys: default * Debugger: S32DS * Target: internal_FLASH * ********************************************************************************

Hi, ARM Cortex-M have a DWT (Data Watchpoint and Trace) unit implemented, and it has a nice feature in that unit which counts the execution cycles. The DWT is usually implemented on most Cortex-M3, M4 and M7 devices, including e.g. the NXP S32K14x. Attachment is the sample project on S32K142 to measure the running time of a function. Password of extraction is nxp. Enjoy the measuring! Cheers! Oliver BTW, Measure the running time of one function on PowerPC could also be gotten through the link.

************************************************************************************************ Detailed Description: WDOG tested in SystemInit() function (system_S32K116.c) after POR. For debugging purposes: - WDOG counter reference clock is pre-scaled to slow the test (CS_PRES = 1). - During CNT_LOW test, BLUE LED (PTE8) ON. - During CNT_HIGH test, RED LED (PTD16) ON. - Once both tests have passed, GREEN LED (PTD15) ON. If either of the test fails, WDOG will stay in its default configuration and rest the MCU. ---------------------------------------------------------------------------------------------------------------- Test HW: S32K116EVB-Q048 REV.B MCU: S32K116 0N96V Debugger: S32DSR1, OpenSDA Target: internal_FLASH ************************************************************************************************

******************************************************************************** Detailed Description: The S32K144 MCU is secure if SEC bits are set to non 0b10 value in Flash Secure Register (FSEC). And can be unsecure using either Mass Erase or Verify Backdoor Access Key command provided they are enabled, again indicated by bits KEYEN and MEEM in the FSEC register. The FSEC register is a read-only register and is loaded with the content of the flash security byte in the Flash Configuration Field located in program flash memory during the reset sequence. The configuration field holds the Backdoor comparison key as well and is configurable in startup_S32K144.S file. The attached example code shows use of Verify Backdoor Access Key flash command. The MCU is secured in the Flash configuration field and therefore once the application has been loaded the debugger does not have access to the MCU which must be run stand-alone. The state of the SEC bits is indicated by LEDs. The RED LED indicates the MCU is secure (SEC != 0b10) after reset. After a delay loop, the Verify Backdoor key command is executed which will unsecure the device and the LED will turn BLUE (SEC = 0b10). NOTE: The Verify Backdoor key command is executed from RAM to avoid simultaneous access to the PFlash block. -------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100 MCU: S32K144 0N47T Debugger: S32DS1.3, OpenSDA Target: internal_FLASH ******************************************************************************** 2.0 Sep-30-2017 Daniel ********************************************************************************

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 25 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 16 channels, ADC1 9 channels. PDBs are set to back-to-back mode to perform chain conversion. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 channels ADC ch12 is selected, as it is connected to trimmer on the EVB. DMA is used to read result into single buffer, and DMA callbacks are issued to indicate end of transfer for each ADC module. Within those callbacks PTE14 and PTE15 is toggled. PDB0 output pulse is generated on the PTE16 to indicate start of ADC measurement. This is done periodically at LPIT ch0 rate, which is set to 30us. The ADC0 ch0 result is used to dim LEDs. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K144UAVLL 0N57U * Target: Debug_FLASH * EVB connection: * Compiler: S32DS.ARM.2018.R1 * SDK release: S32SDK_S32K1xx_RTM_3.0.0 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 May-04-2019 Petr Stancik Initial version *******************************************************************************/

The S32K3 family of 32-bit AEC-Q100 qualified MCUs combines a scalable family of Arm® Cortex-M7-based microcontrollers built on long-lasting features with a comprehensive suite of production-grade tools. S32K3 MCUs are included in NXP’s Product Longevity Program, guaranteeing a minimum of 15 years of assured supply. The S32K3 offers dedicated peripherals set for rapid motor control loop implementation: enhanced Modular IO Subsystem(eMIOS), Logic Control Unit (LCU), TRGMUX, BodyCross-triggering Unit (BCTU), Analog to Digital Converter(ADC), and Analog Comparator (CMP). The comprehensive motor control ecosystem based on Automotive Math and Motor Control Library(AMMCLib) set, FreeMASTER with Motor Control ApplicationTuning (MCAT) tool and Model-Based Design Toolbox (MBDT) helps to enable S32K3 MCU in wide range of motor control use cases. The table below points to the articles with more detailed description each of S32K3 motor control use cases, hardware description, links to appropriate application notes and their addendums, and software repositories. Device HW Article S32K344 MCSPTE1AK344 12 V development kit engineered for 3-phase PMSM and BLDC motor control applications FOC with dual shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with dual shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API. FOC with single shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with single shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The single shunt current measurement is advanced technique that allows decrese the cost of Bill of Material (BOM). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API. FOC integrated with FreeRTOS Article focuses on integration of motor control software (based on FOC with dual shunt current measurement) and Real Time Operating System (FreeRTOS). The available example code is based ANSI-C code and uses RTD drivers with low-level non-Autosar API. Six-step commutation control. Article focuses on solution based Six-step commutation (6-step) technique (typically used for 3-phase BLDC motors) with Hall position sensor and without any position sensor (sensorless). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with low-level non-Autosar API. Note: the list of use cases cannot cover all combinations of MCU, current measurement scenario, control technique and sensor inputs, but should work as a base reference for most common configurations. This list is not final, please follow this acticle to be notified about updates with new use cases.

******************************************************************************** * Detailed Description: * * This example shows how to init DMA for simple memory to memory copy. * Eight 16-bit values are copied upon SW start. * * ------------------------------------------------------------------------------ * Test HW: FRDM-S32K144 * MCU: PS32K144HFVLL 0N77P * Fsys: default * Debugger: S32DS * Target: internal_FLASH * ******************************************************************************** Original Attachment has been moved to: Example-S32K144-DMA-RAM2RAM-test-v1_0-S32DS.zip

S32K1xx S32K144 Example S32K144 CMP Round-robin S32DS2.0 Example S32K144 Verify Backdoor Access Key S32DS1.3 Example S32K144 FlexCAN0 RXFIFO DMA nonSDK S32DS13 Example S32K144 PDB ADC trigger DMA ISR S32DS Example S32K144 Flash RW simple S32DS Example S32K144 DMA memory copy test S32DS Example S32K144 EEEPROM usage Example S32K144 EEEPROM usage - No SDK Example S32K144 RTC VLPS Example S32K144 WDOG RCM interrupt Example S32K144 SRAM ECC Injection Example S32K144 RAM Retention S32DS.R1 Example S32K144 I2C Master MPL3115A2 S32DSR1_v3 Example S32K144 FlexCAN RXFIFO DMA S32DS.ARM.2018.R1 Example S32K144_printf_implementation - S32DS_1.0 Example S32k144 UART printf/scanf under FreeRTOS - S32DS Example S32K144 SDK Function call on configurable period using LPIT timer. Example S32K144 .noinit section usage Example S32K144 PDB ADC DMA S32DS.ARM.2018.R1 Example S32K144 RAM selftest simple S32DS 2018.R1 Example S32K144 Position Independent Code Example S32K144 FlexCAN Pretended Networking STOP mode test S32DS.ARM.2.2 Example S32K144 LPIT DMA LPSPI Example S32K144 FlexCAN TX/RX/Error ISR test S32DS2.2 Example S32K144 FlexIO Idle Detection S32DS2.2 S32K142 Example_S32K142_LMEN_Cache_v1_0_S32DS3.6_RTD300 Lauterbach_Script_For_MDM_AP_Mass_erase_S32K142 S32K146 Example S32K146 Set_whole_FlexRAM-as_RAM S32DS.ARM.2.2 S32K148 Example S32K148 PDB0-PDB1 ring S32DS3.4 RTM4.0.3 Example S32K148 PDB0-PDB1 ring DMA S32DS3.4 RTM4.0.3 Example S32K148 GPIO Interrupt S32K116 Example S32K116 WDOG Fast Test Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2 Example S32K116 FlexCAN PN STOP S32DS.ARM.2.2 Example S32K116 FlexCAN VLPR test S32DS.ARM.2.2 S32K118 Example S32K118-SRAM-keep_data_over_SW_reset v0_1 S32DS.ARM.2.2 S32K3xx S32K312 Example S32K312 ADC_IP Continuous Scan DMA S32DS36 RTD600 S32K344 Example S32K344 PIT BTCU ADC DMA DS3.4 RTD100 Example S32K344 FlexCAN_Ip TX/RX/EnhanceRXFIFO test S32DS3.4 RTD200 Example Siul2_Port_Ip_Example_S32K344_ITCM_DTCM S32DS3.4 RTD300 Example S32K344 LPUART RX/TX ISR FreeRTOS S32DS36 RTD600 Example_S32K344_MCAL_MCU_ClockMonitor_v1_0_S32DS36_RTD600 Example_S32K314_DTCM1_Backdoor_RTD201_DS34_v3 Example_Reg_Prot_Flash_Controller_S32K344 Example_S32K344_EIM_ERM_DTCM_SRAM_Baremetal_v3_0_S32DS36 Example S32K344 PIT SWtrig ADC ANAMUX S32DS 3.6.0 RTD 6.0.0 Example S32K344 EMAC lwIP FreeRTOS miniEVB S32DS 3.6.1 RTD 6.0.0 Example S32K344 EMAC lwIP FreeRTOS MRCANHUB S32DS 3.6.1 RTD600 Example_S32K344_BIST_eMCEM_SPD106_v2_0_S32DS365_RTD700 Example S32K344EVB_T172 UART_ETH_Gateway HLD S32DS368 RTD701 Example_S32K344_CMU_FM_POR_WDG_v1_0_S32DS369_RTD701 Example_S32K344_FLS_Integrity_Margin_Check_v1_0_S32DS36_RTD701 Example S32K344 LPSPI LCD-PAR-S035 FRDM S32DS 3.6.6 RTD 7.0.1 Example FRDM-A-S32K344 FlexCAN TX_RX FreeRTOS S32DS36 RTD600 S32K358 S32K358 Multicore Start CM7_2 from CM7_0 Example S32K358 FlexCAN TXRX ISR S32DS35 RTD400/500 Example S32K358 GMAC 100M lwIP FreeRTOS S32DS 3.6.1 RTD600 Example S32K358 GMAC 1G lwIP FreeRTOS S32DS 3.6.1 RTD600 Example S32K358 GMAC lwIP FreeRTOS RDBESS S32DS 3.6.1 RTD600 Example_S32K358_XRDC_SEMA42_Multicore_v1_0_S32DS369_RTD701 S32K388 Example S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600 S32K389 Example S32K389 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD 6.0.0 Example S32K389 GMAC1 SABRE lwIP FreeRTOS S32DS 3.6.1 RTD600

* ================================================================================================= * Detailed Description: * * This example demonstrates Classical CAN and CAN FD reception and transmission using * interrupt-driven Message Buffers and FreeRTOS. * * FlexCAN0 is configured in Normal mode. MB0 receives standard-ID frames and MB1 receives * extended-ID frames. The FlexCAN callback copies every received frame into a FreeRTOS queue * and immediately rearms the corresponding RX Message Buffer. * * A dedicated FreeRTOS task waits for frames in the queue and echoes them through CAN TX MB2. * The transmitted frame preserves the received identifier type, identifier, payload length, * payload, CAN FD EDL state, and BRS state. The user LED is toggled after a transmit request * is accepted by the driver. * * Note: * FreeRTOS API functions such as xQueueSendFromISR() are used from the FlexCAN callback. * Therefore, the FlexCAN interrupt priority must comply with the FreeRTOS interrupt-priority * requirements defined by configMAX_SYSCALL_INTERRUPT_PRIORITY. * * ================================================================================================= * Test HW: FRDM-A-S32K344 (SCH-94921 / SPF-94921 Rev. C) * MCU: S32K344 * Compiler: S32DS 3.6.x * RTD release: S32K3_RTD_6_0_0_D2506_ASR_REL_4_7_REV_0000_20250610 * Debugger: On-Board Debugger * Target: Internal_FLASH * Communication: Classical CAN / CAN FD, STD and EXT ID, optional BRS * =================================================================================================

**************************************************************************** * Detailed Description: * * CAN <-> Ethernet gateway demo for FRDM-A-S32K344. * * CAN FD frames are encapsulated into raw Ethernet frames and * transmitted over the 100BASE-TX link. Received Ethernet frames * are decapsulated and forwarded to the CAN FD bus. * * Key Functionality: * - Interrupt-driven CAN FD reception via CanIf_RxIndication callback. * - Interrupt-driven Ethernet reception via EthIf_RxIndication callback * (EthCtrlEnableIngressQueueInterrupt, GMAC0_CH_RX_IRQHandler). * - GMAC TX confirmation interrupt processing (GMAC0_CH_TX_IRQHandler). * - Custom gateway format for CAN ID, DLC, flags and * payload (up to 64 bytes CAN FD) in a fixed 72-byte Ethernet payload. * - PHY CAN transceiver initialization. * - Ethernet PHY auto-detection and MDIO configuration via EthPhy driver. * - PHY initialization selectable at compile time: * PHY_INIT_BY_PIN_STRAPPING (default) * PHY_INIT_BY_SOFTWARE (MDIO register write) * * Main Loop Flow: * - CAN -> ETH : CanIf_bRxFlag set by ISR -> App_EthTransmit() * - ETH -> CAN : ethReceiveFlag set by ISR -> App_CanTransmit() * * Notes: * - Red LED set if Gateway_Init returns E_NOT_OK. * - Green LED toggles upon CAN reception. * - Blue LED toggles upon ETH reception. * - EthIf.c contains the custom EthIf_RxIndication gateway implementation. * - During S32 Configuration Tool code generation select "Keep Existing" * for EthIf.c to avoid overwriting the custom callback. * - Eth_43_GMAC_ReleaseRxBuffer() must be called unconditionally inside * EthIf_RxIndication. * * ------------------------------------------------------------------------- * Test HW : FRDM-A-S32K344 Rev A * MCU : S32K344_257BGA * IDE : S32DS 3.6.10 * RTD : S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * AUTOSAR : 4.9.0 * Debugger : P&E Micro * Target : Internal_FLASH * CAN : CAN FD, 500 Kbps nominal / 2 Mbps data, TJA1043 transceiver * Ethernet : RMII 100BASE-TX, DP83848 PHY **************************************************************************** ETH Reception with Wireshark: CAN Reception with PCAN-USB. Note 1: Inside project you can comment NODE_1 and define NODE_2 as 1 to enable simple routine which sends out a CAN frame if SW3 is pressed, and an ETH frame if SW2 is pressed. Note 2: For a real gateway application, use a queue or ring buffer instead of one global frame; otherwise, a second CAN frame can overwrite the first before Ethernet transmission completes. This example is for demostration purposes only.

********************************************************************************* * Detailed Description: * * ADC hardware trigger demonstration using BCTU Trigger Mode on S32K358. * * An eMIOS1 Channel 23 reload event is used as a trigger source for the BCTU). * The BCTU initiates a hardware-triggered conversion of an ADC1 group containing * three channels. * * The result of the third ADC channel, connected to the on-board potentiometer * (ADCPOT0), is used to dynamically update the duty cycle of an * eMIOS Channel 5 PWM output. * * The PWM output drives the on-board LED, allowing the potentiometer position * to control LED brightness. * * Key Functionality: * - eMIOS-triggered BCTU operation. * - BCTU Trigger Mode configuration. * - ADC1 hardware-triggered group conversion. * - ADC notification callback processing. * - PWM duty-cycle update based on ADC result. * - LED brightness control using the potentiometer. * * ------------------------------------------------------------------------------ * Test HW: S32K3x8EVB-Q289 * MCU: S32K358 * IDE: EB Tresos 29.0.0 * RTD Release: S32K3_RTD_6_0_0_D2506_ASR_REL_4_7_REV_0000_20250610 * Debugger: Lauterbach * Target: Internal_FLASH ******************************************************************************** * Revision History: * Ver Date Author Description of Changes * 1.0 02-10-2026 Petr Stancik Initial version ********************************************************************************

********************************************************************************************** * Detailed Description: * This example demonstrates the S32K344 internal flash UTest (User Test) sequence using the * Mem_43_INFLS AUTOSAR driver. It covers Array Integrity Check (MISR-based) and User Margin * Read Check, exercised over the full configured Block 3 address range (starting at * 0x00700000), as defined in the Mem_43_INFLS instance configuration. * * Setup: * ProgramBlock3() erases one sector (8 KB) at 0x00700000 and programs the first 512 bytes * with a sequential byte pattern (0x00..0xFF repeating). The remainder of the block * contains erased cells (0xFF). The UTest operations in Steps 1–3 are performed over the * entire Block 3 — not only the 512 programmed bytes. * * Step 1 — Array Integrity Check, Golden MISR Capture: * Runs the Array Integrity Check at NORMAL read margin using sequential addressing over * the full block. UM0–UM9 are seeded with 0xA5A5A5A5. MisrExpectedValues is intentionally * set to 0x0, so JOB_FAILED is the expected outcome. A custom wait function polls the AID * bit directly (without calling Mem_43_INFLS_MainFunction) so that the UM registers are * read before the driver clears them on job completion. The captured MISR becomes the * golden reference (goldenMisr) for Steps 2 and 3. * GETSTATEUTEST_JOB is called afterward to confirm no real hardware fault occurred * (ECC error, breakpoint, or suspension) during the capture run. * * Step 2 — Array Integrity Check, Verification Run: * Re-runs the identical Array Integrity Check over the full block (same seed, same * sequential addressing) with MisrExpectedValues = goldenMisr captured in Step 1. * JOB_OK confirms flash content is unchanged; JOB_FAILED indicates corruption. * GETSTATEUTEST_JOB is called to verify clean hardware completion. * * Step 3 — User Margin Read Check, Cell Margin Verification: * Re-reads the full block at a tighter read margin (C40_IP_MARGIN_LEVEL_PROGRAM). * Same seed and goldenMisr are used. If all cells retain sufficient voltage margin at * the tighter threshold, the MISR matches and JOB_OK is returned. A JOB_FAILED result * indicates one or more cells are degrading before they produce a detectable ECC error * under normal read conditions. * Note: both Array Integrity Check and User Margin Read Check must use sequential * addressing (C40_IP_SEQUENTIAL) to produce a comparable MISR signature. * * Results are accumulated in the utestResults structure (Utest_TestResultType), recording * both the MISR job outcome (Utest_JobResultType) and the hardware UTest state * (Utest_HwStateType) for each step independently. * * NOTE: This example must be executed from SRAM. The Mem_43_INFLS UTest operations * (Array Integrity Check, User Margin Read Check) place the internal flash controller * in UTest mode, during which the flash array is not available for normal read access. * ------------------------------------------------------------------------------------- * MCU: S32K344 * FX_OSC: 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************

This example is based on AN13458: Implement IPv6 + IPv4 Communication on One ENET Port based on LWIP. /* * Copyright 2017-2026 NXP * * NXP Confidential and Proprietary. This software is owned or controlled by NXP * and may only be used strictly in accordance with the applicable license terms. * By expressly accepting such terms or by downloading, installing, activating * and/or otherwise using the software, you are agreeing that you have read, * and that you agree to comply with and are bound by, such license terms. * If you do not agree to be bound by the applicable license terms, * then you may not retain, install, activate or otherwise use the software. ********************************************************************************* * File main.c * Owner Julián Aragón * Version 1.0 * Date 21-09-2026 * Classification General Business Information ********************************************************************************* * Detailed Description: * Updated the example lwip_baremetal_s32k344 to enable simultaneous IPv4 and * IPv6 pinging of the lwIP stack from the command window, based on AN13458. * * ping -4 192.168.0.200 * * Pinging 192.168.0.200 with 32 bytes of data: * Reply from 192.168.0.200: bytes=32 time<1ms TTL=255 * Reply from 192.168.0.200: bytes=32 time=1ms TTL=255 * Reply from 192.168.0.200: bytes=32 time<1ms TTL=255 * Reply from 192.168.0.200: bytes=32 time<1ms TTL=255 * * Ping statistics for 192.168.0.200: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), * Approximate round trip times in milli-seconds: * Minimum = 0ms, Maximum = 1ms, Average = 0ms * * ping -6 FE80::3DD7:9303:126c:0df0%23 * * Pinging fe80::3dd7:9303:126c:df0%23 with 32 bytes of data: * Reply from fe80::3dd7:9303:126c:df0%23: time<1ms * Reply from fe80::3dd7:9303:126c:df0%23: time<1ms * Reply from fe80::3dd7:9303:126c:df0%23: time<1ms * Reply from fe80::3dd7:9303:126c:df0%23: time<1ms * * Ping statistics for fe80::3dd7:9303:126c:df0%23: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), * Approximate round trip times in milli-seconds: * Minimum = 0ms, Maximum = 0ms, Average = 0ms * * EVB: * - All jumpers in default positions * * Configuration: * - Updated pin configuration * - Updated clock configuration * - IPv4 address: 192.168.0.200 * - IPv6 address: FE80::3DD7:9303:126c:0df0 (static link-local) * - Enabled LWIP_IPV6 in lwipopts.h * - Enabled LWIP_RAW in lwipopts.h * - Set has_IPv6 = 1 in netifcfg.c * * main.c * - Updated header only * device.c * - No changes * test.c * - Added IPv6 static address assignment in interface_init() * (IP6_ADDR + netif_add_ip6_address + netif_ip6_addr_set_state) * - Added icmp_led_init() call in apps_init() * - Added icmp_led_callback(): raw PCB for IPv4 ICMP (protocol 1) * flashes GREEN LED on ping receive * - Added icmp_led_callback(): raw PCB for IPv6 ICMPv6 (protocol 58) * flashes BLUE LED on ping receive * - Commented out TCP/IP stack shutdown timeout * * ----------------------------------------------------------------------------- * Test HW: FRDM-A-S32K344 SCH-94921 PDF: SPF-94921 Rev. C * MCU: S32K344 * Debugger: On Board * Target: internal_FLASH * EVB connection: EMAC <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11 ********************************************************************************* * Revision History: * Ver Date Author Description of Changes * 1.0 Sep-21-2026 Julián Aragón Initial version **********************************************************************************/ Note: In order to ping with IPv6 from Windows 11 Command Prompt, you must specify Ethernet port Idx being used: ping -6 FE80::3DD7:9303:126c:0df0%<interface_index> You can find your numeric index with the following command: netsh interface ipv6 show interfaces.

**************************************************************************************************** * Detailed Description: * * CM7_0 Safety Core (Lockstep): * * Runs as Domain 0 on the CM7_0+CM7_1 lockstep core pair of the S32K358. * Acts as the system master: performs full initialization of clocks, XRDC * domain assignment and memory region protection (Rm_Init), Port, Platform, * and releases CM7_2 from reset via Mcu_SetMode(McuModeSettingConf_1). * * XRDC memory layout configured by Rm_Init: * - 0x20480000 (SHARED_VARIABLE): Domain 0 RW, Domain 1 RW — Sema42 Ch 0 protected * - 0x20480010 (SHARED_FAULT_FLAG): Domain 0 RW, Domain 1 RW — Sema42 Ch 1 protected * - 0x20490000 (CM_0_OWNED_VARIABLE):Domain 0 RW, Domain 1 NO ACCESS — exclusive to CM7_0 * * Two Sema42 channels are used: * - Channel 0: guards the shared counter at 0x20480000 (competed with CM7_2) * - Channel 1: guards the fault flag at 0x20480010 (CM7_0 monitors CM7_2 violations) * * Main loop (continuous): * - Writes to the owned SRAM region (0x20490000) directly, without a semaphore — * XRDC guarantees exclusive Domain 0 access. Blinks BLUE LED on each write. * - Acquires Sema42 Ch 0, increments the shared counter at 0x20480000, * releases Ch 0. Competes with CM7_2 for the gate — mutual exclusion * is visible as either core stalls while the other holds the semaphore. * * XRDC_ISR_Handler (triggered by XRDC interrupt when CM7_2 violates 0x20490000): * - Spins on Sema42 Ch 1 until CM7_2's HardFault handler sets the shared * fault flag at 0x20480010, confirming CM7_2 has handled the violation. * - Acquires Ch 1 and clears the fault flag, signaling CM7_2 to resume * its main loop cycle. * - Together with CM7_2's HardFault handler, this implements a lightweight * cross-core fault notification and recovery handshake. * * CM7_2 Application Core * * Runs as Domain 1 on the independent CM7_2 core of the S32K358. * Only Sema42 is initialized here — XRDC and full RM initialization * are handled exclusively by CM7_0 (Domain 0, lockstep) before this core is released from reset. * * Two Sema42 channels are used: * - Channel 0: guards the shared counter at 0x20480000 (competed with CM7_0) * - Channel 1: guards the fault flag at 0x20480010 (CM7_2 signals CM7_0) * * Main loop (repeating cycle of 10 iterations, i = 0..8 + violation): * - Before each iteration, CM7_2 reads the shared fault flag via Ch 0 * and spins until CM7_0 clears it (fault recovery synchronization). * - Iterations 0..8 (9x): acquires Ch 0, increments the shared counter, * releases Ch 0, blinks GREEN LED to indicate successful access. * - Iteration 9: deliberately writes 0xDEAD to CM7_0's owned SRAM region * (0x20490000), which has no XRDC access for Domain 1. * This triggers a HardFault on CM7_2. After fault handling, variable i is reset * to 0 and the cycle repeats indefinitely. * * HardFault handler (triggered by XRDC violation on iteration 9): * - Lights RED LED immediately. * - Calls Rm_XrdcGetDomainIDErrorStatus() to read and decode the XRDC * error registers (domain, faulting address, access type, attribute). * Error registers are cleared automatically inside this API call. * - Acquires Sema42 Ch 1 and sets the shared fault flag at 0x20480010 * to notify CM7_0 that a violation was detected. ------------------------------------------------------------------------------------------------ * MCU: S32K358 * FXOSC 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: PE Micro Multilink * Target: Internal_FLASH ****************************************************************************************************

********************************************************************************************** * Detailed Description: * CMU_FM minimum reference count requirement: * RCCR[REF_CNT]_MIN = CEILING(MAX(3 * (f_reference_clock / f_bus_clock), * 8 + 5 * (f_reference_clock / f_monitored_clock))) * where: * f_reference_clock = FXOSC clock frequency * f_bus_clock = AIPS_SLOW_CLK frequency (40 MHz) * f_monitored_clock = metered clock frequency * * CMU_1 * ----- * FIRC clock frequency (fmonitored) = 48 MHz * FXOSC clock frequency (fref) = 16 MHz * * 3 * (fref / fbus) = 3 * (16 / 40) = 1.2 * 8 + 5 * (fref / fmonitored) = 8 + 5 * (16 / 48) = 9.667 * RCCR[REF_CNT]_MIN = CEILING(MAX(1.2, 9.667)) = 10 * The first term would dominate only at f_bus_clock < 4.96 MHz, for example. * * CMU_2 * ----- * SIRC clock frequency fmonitored = 32 kHz * FXOSC clock frequency (fref) = 16 MHz * * 3 * (fref / fbus)= 3 * (16 MHz / 40 MHz) = 1.2 * 8 + 5 * (fref / fmonitored) = 8 + 5 * (16 MHz / 32 kHz) = 2508 * RCCR[REF_CNT]_MIN = CEILING(MAX(1.2, 2508)) = 2508 * * * SR_FMTO (Frequency Meter Time Out): * --------------------------------------------------------------------- * FMTO could theoretically be triggered by configuring RCCR[REF_CNT] * to a value lower than the minimum number of reference clock cycles * required to observe one full monitored clock period. * This however cannot be guaranteed by NXP as the value is lower then RCCR_MIN. * NXP guarantees the MCU functionality only if RCCR > RCCR_MIN * When SR_FMTO is set, the SR_FMC is never set, and therefore the CMU_FM interrupt is never called. * * CMU_FM_1: * RCCR[REF_CNT] < f_FIRC / f_FXOSC < (48 MHz / 16 MHz) < 3 * CMU_FM_2: * RCCR[REF_CNT] < T_SIRC / T_FXOSC < 31.25 µs / 62.5 ns < 500 * * * POR_WDG: * --------------------------------------------------------------------- * In case CMU_FM_1 ISR is not executed within POR_WDG timeout, the MCU is reset by the POR_WDG. * Read DCMROPP1-4 * To inject this reset, select CMUFM_1_POR_WDG = 1 and CMUFM_1. * ------------------------------------------------------------------------------------- * MCU: S32K344 * FX_OSC: 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************

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