* Detailed Description: * Updated the example lwip_FreeRTOS_s32K344 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions. * * Configuration: * - Updated pin configuration * - Modified FXOSC, PLLAUX + dividers * - Platform: added EMAC_0_IRQn interrupt * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Added DIO * * main.c * - Updated only the header * device.c * - No updates * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: MR-CANHUBK344 * MCU: S32K344 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: EMAC <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected to enable an external debugger. * * TJA1103-SDBR: * mode rev-RMII * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 1-2 * * Configuration: * - Updated pin configuration * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC1_SABRE <-> TJA1103-SDBR (rev-RMII mode) <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1120-SDBR: * mode RGMII-ID (both TXC/RXC), Master, Autonomous, XTAL * CONFIG 3 2-3 * CONFIG 5 1-2 * CONFIG 4,6 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1120-SDBR <-> Media converter TE-1402 (1G, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1103-SDBR: * mode RGMII-ID (both TXC/RXC) * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 100M * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1103-SDBR <-> Media converter TE-1402 (100M, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K388 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions except: jumper J361 must be closed. * - Soldering rework required to connect an external debugger. * See S32K388EVB-Q289_HW_User Manual_A3.pdf, chapter 15 (Errata). * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMACx clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K388_gptp_ds, S32K3xx gPTP Stack 1.0.0) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * --------------------------------------------------------------------------------------- * Test HW: S32K388EVB-Q289 SCH-88925 REV A, 700-88925 REV X1 * MCU: S32K388 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

**************************************************************************************************** * Detailed Description:   * * The Flexio I2C driver provides an optional configuration parameter for reducing the number of DMA interrupts * required for transmission that are configured with DMA Optimize option. Instead of being interrupted after each * end of transmitting or receiving a data block or data amount larger than 13 bytes, only one interrupt will be raised to * stop frame and inform to user that the transmission was done. * * More details can be found in "RTD_I2C_UM.pdf", the chapter 3.6.3 FLEXIO DMA Optimize. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 SCH-53148 REV B2 * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Connections： * FXIO_D10_SCL (J4.19) - LPI2C1_SCL (J3.24) * FXIO_D11_SDA (J4.17) - LPI2C1_SDA (J3.27) ***************************************************************************************************/ Test Result:  

This article provides a software package with additional example projects for wakeup use case using RTD6.0.0. All the wakeup example projects mentioned in this page are developed based on RTD, delivered with LLD and HLD.

******************************************************************************************** * Test HW: S32K312 EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.6.2 * SDK release: RTD 6.0.0 QLP04 * Debugger: PE Micro * Target: Internal_FLASH ******************************************************************************************** The objective of this demo application is to generate an interrupt and wakeup using the single GPIO. In this application, USR_SW5 (PTB26) in S32K312_Q172 EVB is used both as an interrupt source in RUN mode and as a wake‑up source from STANDBY mode.   Thanks & regards, Krishnakumar V

* Detailed Description: * Updated the example lwip_FreeRTOS_s32K344 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions * * Configuration: * - Updated pin configuration * - Updated clock configuration * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Added DIO * * main.c * - Updated only the header * device.c * - No changes * test.c * - Commented out the code that shuts down the TCP/IP stack after * its predefined timeout * - Added LED task * * ----------------------------------------------------------------------------- * Test HW: S32K344MINI-EVB SCH-94921 REV B, 700-94921 REV B * MCU: S32K344 * Debugger: On Board * Target: internal_FLASH * EVB connection: EMAC <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

********************************************************************************* * Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected * to enable an external debugger. * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMAC0 clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K389_gptp_ds, SW32K3xx_M7_gPTP_1.1.0_CD01_D2602) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ----------------------------------------------------------------------------- * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> * <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

**************************************************************************************************** * Detailed Description: * * SW triggered conversion of ADC0 internal channel 50 (ANAMUX_OUT). * ANAMUX is used for internal supply monitoring. * Supply to be monitored is configured using DCMRWF1 register. * * PIT is configured to generate interrupt each second then ADC conversion for selected supply is * SW started and measured result is printed to the UART interface * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3x4EVB-T172 Rev B * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.0 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: Lauterbach, P&Emicro * Target: Internal_FLASH * Serial: 115200, 8N1 ***************************************************************************************************/ Terminal output

The procedure to restrict JTAG access on the S32K3 MCU depends on whether HSE Firmware (FW) is used: With HSE FW: This scenario is not covered in this document. Without HSE FW: WARNING: ONCE THIS PROCESS IS COMPLETED, HSE CANNOT BE INSTALLED ON THE DEVICE. Development Environment: All code snippets provided represent the essential parts of the application and were developed using: Test HW: S32K344 (not EVB) MCU: S32K344 IDE: S32DS v3.5 Debugger: PEmicro USB Multilink Universal FX (unless otherwise noted) Drivers: S32K3 Real-Time Drivers v3.0.0 (released March 31, 2023) Base Project: Modified version of C40_Ip_Example_S32K344 Step 1: Program the CUST_DB_PSWD_A Field The UTEST Sector is an OTP (One Time Programmable), meaning erase operations are not allowed. You can only append or read data. Memory Range: 0x1B00_0080 to 0x1B00_009 Only the first 16 bytes (0x1B00_0080 to 0x1B00_008F) are usable. The rest is reserved (see Table 202 in the S32K3xx Reference Manual, Rev. 11). Programming Steps: I. Unlock the UTEST sector using PFCBLKU_SPELOCK[SLCK]. II. Write the 16-byte password to address 0x1B00_0080. Code Adjustments: /*============================================================================ * LOCAL MACROS ============================================================================*/ #define FLS_MASTER_ID 0U #define FLS_BUF_SIZE 16U #define FLS_SECTOR_ADDR 0x1B000080U #define FLS_SECTOR_TEST C40_UTEST_ARRAY_0_S000 NOTE: Ensure FLS_MAX_VIRTUAL_SECTOR and C40_SECTOR_ERROR are correctly defined in C40_Ip_Cfg.h: Instead of: #define FLS_MAX_VIRTUAL_SECTOR (527U) … #define C40_SECTOR_ERROR (528U) Use: #define FLS_MAX_VIRTUAL_SECTOR (528U) … #define C40_SECTOR_ERROR (529U) /*============================================================================ * GLOBAL CONSTANTS ============================================================================*/ uint8 TxBuffer[FLS_BUF_SIZE] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F}; /* Password */ You can verify the password using the Memory Viewer (not covered here).   Step 2: Advance the MCU Lifecycle I. Set the lifecycle configuration word address in the IVT/boot header. Refer to sections 32.5 and 32.5.3 of the Reference Manual. NOTE: Ensure the structure of the boot_header (located in Project_Settings → Startup_Code → startup_cm7.s) is defined as follows: #define LF_CONFIG_ADDR (0x007D2000) /* The LC word can be at any flash address, taking care that does not interfere with HSE */ II. Write the LC word to the defined address: Life cycle stage Valid Values for LC Advancement OEM_PROD DADA_DADAh IN_FIELD BABA_BABAh Code Adjustments: /*=========================================================================== * LOCAL MACROS ===========================================================================*/ #define FLS_MASTER_ID 0U #define FLS_BUF_SIZE 8U #define FLS_SECTOR_ADDR 0x007D2000U #define FLS_SECTOR_TEST C40_CODE_ARRAY_0_BLOCK_3_S489 /* Look into C40_Ip_Cfg.h file to find the corresponding sector */ /*=========================================================================== * GLOBAL CONSTANTS ===========================================================================*/ uint8 LC_TxBuffer[FLS_LC_SIZE] = {0xDA, 0xDA, 0xDA, 0xDA, 0x0, 0x0, 0x0, 0x0}; /* Minimum data length 8 bytes */ Confirm the LC word using the Memory Viewer. III. Reset the MCU using the RESET_B pin, not the debugger. If the procedure was done correctly, you should see the following message: Step 3: Debugger Authentication To unlock the MCU, PEmicro provides Python scripts (PEmicro support files package) to facilitate debugger authentication when the password is set. In summary: I. Ensure Python 3.5 or later is installed. II. Open Command Prompt. III. Use cd to navigate to the directory containing the file package. IV. Run the script: py authenticate_password_mode.py -hardwareid=USB1 -password=… hardwareid: Debug hardware IP, name, serial number, or port password: 16-byte hexadecimal password NOTE: This must be done every time the MCU is reset or power cycled.   Step 4: Secure Debugging in S32DS In S32DS, when configuring the Debug Configurations of a project, change the Target to "SECUREDEBUG". This is necessary because during debug entry, a hard reset is toggled, which clears the authentication. Once authenticated, you can securely debug the device in S32DS.  *Additional Resources iSystem: How to unlock secure debug on NXP S32G2/3xx, S32R45x, and S32K3 Segger: NXP S32K3xx - Debug Authentication   Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

******************************************************************************************************* * Detailed Description: These demos showcase how to use eMIOS in Input Capture mode with DMA, utilizing both low-level drivers (Ip) and high-level drivers (MCAL). They demonstrate how timestamp data from captured input signals is stored and how a GPIO toggle provides a simple visual confirmation that the interrupt is being triggered as expected. * Connections:  ******************************************************************************************************* * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Debugger: S32DS 3.6.2, OpenSDA * Target: internal_FLASH ******************************************************************************************************* * Important information:  eMIOS Pwm: Configures EMIOS 0 Channel 1 as OPWMB (Output Pulse Width Modulation Buffered). This channel generates a waveform that will be captured by Channel 9 eMIOS Icu with DMA: Configures EMIOS 0 Channel 9 in ICU_MODE_TIMESTAMP using SAIC (Single Action Input Capture) mode. This channel captures the timestamps of the waveform generated by Channel 1. After a predefined number of captures, a DMA interrupt is triggered. ******************************************************************************************************* Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

NXP has ported FreeRTOS SMP (V11.1.0) to the S32K389. Many customers are interested in how to enable the FreeRTOS SMP on the S32K3xx. The demo is implemented as a single project with a single linker file and a single ELF file. Demo SW/HW Environment: 1. S32DS3.6.4 2. RTD7.0 3.SW32K3_FreeRTOS_11.1.0_7.0.0_CD1_HF1_D2511_DesignStudio_updatesite 4. S32K389 EVB  Demo Code Key Features: 1.FreeRTOS SMP is running on the S32K389 with all cores active. 2.DTCM is used as the task stack. 3.The hardware semaphore (SEMA42) is enabled in FreeRTOS. 4.XRDC is enabled so that each core has a unique core ID for semaphore operations. 5.CAN0 runs on Core0, and CAN4 runs on Core2. 6.LPUART11 is used to print debug information. All cores can output their own messages via LPUART11.  Disclaimer: The code is provided as demo code. NXP makes no commitment regarding its quality.  

This is set of S32K389EVB-Q437 demo projects. S32K389_GPIO_RTD6d0_S32DS3d6d2 S32K389_LPUART_RTD6d0_S32DS3d6d2 S32K389_FlexCAN_RTD6d0_S32DS3d6d2 S32K389_PFLASH_RTD6d0_S32DS3d6d2 S32K389_ADC_RTD6d0_S32DS3d6d2 S32K389_eMIOS_GPT_RTD6d0_S32DS3d6d2 S32K389_LowPower_RTD6d0_S32DS3d6d2 Examples are based on S32K3 RTD version 6.0 and created in S32DS version 3.6.2

S32K1 vdd falling low voltage POR clear situation 1. Abstract This document primarily aims to explain the situation where the POR flag in the RCM_SSRS of the S32K1 chip is cleared, and to explain the setting status of the reset pin and the POR and LVD bits when VDD is powered down. This article is written because some customers, when using the RCM_SSRS reset flag to determine the corresponding RAM initialization conditions, have made incomplete considerations, leading to component failures in actual projects. They mistakenly believe that as long as the SSRS POR flag is not cleared by software writing a 1 after power-on, the POR bit will remain indefinitely. In reality, even after power-on, if subsequent power fluctuations cause VDD to drop to LVD/LVR and trigger a reset, the POR flag may still be automatically cleared by the chip.   2. Document content This article mainly categorizes VDD power-down scenarios into three main types: (1) VDD drops below the minimum LVR value but above VPOR, and then power is  back to normal VDD. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. (2) VDD drops below LVD, above LVR, and LVDRE=0. In this case, reset flag POR=1 and LVD=1 in RCM_SSRS. (3) VDD drops below LVD, above LVR, and LVDRE=1. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. The schematic diagram is as follows:   3. Test result on S32K116 board        

 ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** For S32K312, please use this correct clock HSE to AIPS clock should be ½. Please make these changes in the below all example code clock setting. HSE clock to 60 MHZ.   S32K312 PIT BTCU ADC-1 BCTU_ADC_DATA_REG DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-BTCU-ADC-1-BCTU-ADC-DATA-REG-DMA-DS3-5/ta-p/1787778 S32K312 UART Transmit & Receive Using DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-UART-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1787799 S32K312 EIRQ Interrupt :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-EIRQ-Interrupt-DS3-5-RTD300/ta-p/1787860 S32K312 SPI Transmit & Receive Using DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SPI-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1787856 Example S32K31 SPI multiple packet Transmit & Receive : solution for DMA Cache issue :- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K31-SPI-multiple-packet-Transmit-amp-Receive-solution/ta-p/2130091 Example S32K312 SPI Transmit & Receive Using Polling DS3.5 RTD300 :-- Example S32K312 SPI Transmit & Receive Using Polling DS3.5 RTD300 - NXP Community Example S32K312 SPI Transmit & Receive Using Interrupt DS3.5 RTD300 :-- Example S32K312 SPI Transmit & Receive Using Interrupt DS3.5 RTD300 - NXP Community S32K312 CAN Transmit & Receive Using Polling mode :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-Polling-mode-DS3/ta-p/1789191 S32K312 CAN Transmit & Receive Using MB & FIFO DMA :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-amp-FIFO-DMA/ta-p/1789196 S32K312 ADC :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-ADC-DS3-5-RTD300/ta-p/1789282 S32K312 Switch Debouncing :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Switch-Debouncing-DS3-5-RTD300/ta-p/1789290 S32K312 UART Freemaster :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-UART-Freemaster-DS3-5-RTD300/ta-p/1789306 S32K312 PIT BTCU parallel ADC FIFO DMA  :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-BTCU-parallel-ADC-FIFO-DMA-DS3-5-RTD300/ta-p/1789908 S32K312 placing variables in DTCM & code in ITCM  :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-placing-variables-in-DCTM-amp-code-in-ICTM-DS3-5/ta-p/1790101 Example S32K312 Standby mode & Standby RAM and PAD keeping DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Standby-mode-amp-Standby-RAM-and-PAD-keeping-DS3/ta-p/1797713 Example S32K312 SWT DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SWT-DS3-5-RTD300/ta-p/1800559 Example S32K312 Printf Semihosting DS3.5 RTD300 :--- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Printf-Semihosting-DS3-5-RTD300/ta-p/1801354 Example S32K312 I2C Transmit & Receive Using DMA DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-I2C-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1801357 Example S32K312 HARDFAULT Handling Interrupt DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259 Example S32K312 Bootloader to Application Jump DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Bootloader-to-Application-Jump-DS3-5-RTD300/ta-p/1809810 Example S32K312 PIT timer Toggle LED DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-timer-Toggle-LED-DS3-5-RTD300/ta-p/1809932 Example S32K312 HARDFAULT Interrupt Handling using a script DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Interrupt-Handling-using-a-script-DS3/ta-p/1818507 Example S32K312 UART Transmit & Receive Using Interrupt DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-UART-Transmit-amp-Receive-Using-Interrupt-DS3-5/ta-p/1818775 Example S32K312 CAN Transmit & Receive Using MB Interrupt DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-Interrupt-DS3/ta-p/1818790 Example S32K312 STANDBY wake up using CAN-0-RX and GPIO Switch DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-STANDBY-wake-up-using-CAN-0-RX-and-GPIO-Switch/ta-p/1891411 Example S32K312 STANDBY wake up using RTC DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-STANDBY-wake-up-using-RTC-DS3-5-RTD300/ta-p/1930115 S32K312 : ADC Clock selection :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-ADC-Clock-selection/ta-p/1997759 Example IP S32K312 PWM ICU using EMIOS Custom IRQ DS3.5 RTD300 :-- Example IP S32K312 PWM ICU using EMIOS DS3.5 RTD300 - NXP Community Example IP S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300 :-- Example IP S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300 - NXP Community Example IP S32K312 EMIO PWM Generation & Duty capture using Polling DS3.5 RTD300 :-- Example IP S32K312 EMIO PWM Generation & Duty capture using Polling DS3.5 RTD300 - NXP Community Example S32K312 Continuous SPI Transmit & Receive Using DMA DS3.5 RTD300 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Continuous-SPI-Transmit-amp-Receive-Using-DMA/ta-p/2024597 S32K312 : HSE Demo project :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-HSE-Demo-project/ta-p/2112562 S32K312 : FS26 Watchdog trigger using the SBC_FS26 CDD :-- https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-FS26-Watchdog-trigger-using-the-SBC-FS26-CDD/ta-p/2161357

******************************************************************************* The purpose of this demo application is to place variables in DTCM memory for the S32K3xx MCU.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** ZERO table : is for bss segment variables :  contains RAM start & end address of BSS section which need to be initialized with ZER). Init_table : is for DATA segment variables : contains RAM start address of DATA section & START & end address of ROM address where the initialization values of the variables are stored.   Startup file startup_cm7.s call function init_data_bss() . Inside this function uses these section :-- Variables declared :-- Linker file changes :--   startup_cm7.s file changes :--   MAP file :--     Debug window results :--         https://www.kernel.org/doc/html/v5.9/arm/tcm.html   Due to being embedded inside the CPU, the TCM has a Harvard-architecture, so there is an ITCM (instruction TCM) and a DTCM (data TCM).  The DTCM can not contain any instructions, but the ITCM can actually contain data.   TCM is used for a few things: FIQ and other interrupt handlers that need deterministic timing and cannot wait for cache misses. Idle loops where all external RAM is set to self-refresh retention mode, so only on-chip RAM is accessible by the CPU and then we hang inside ITCM waiting for an interrupt. Other operations which implies shutting off or reconfiguring the external RAM controller.  

**************************************************************************************************** * Detailed Description: * * - CMU errors cannot be injected by any means other than manipulating the CMU thresholds, * except for FXOSC_CLK, which can be physically disrupted on the PCB. * * - CMU_FC_0 (FXOSC_CLK) is configured for **synchronous interrupt** on both LFF and HFF CMU events. * - CMU_FC_3 (CORE_CLK) is configured for **asynchronous destructive reset** triggered only by the LFF event; the HFF event is ignored. * - CMU_FC_4 (CORE_CLK) is configured identically to CMU_3: **asynchronous destructive reset** on LFF only; HFF is ignored. * - CMU_FC_5 (HSE_CLK) can be configured by the HSE_B core only. * Refer to the Reference Manual rev.10, Figure 122. Frequency checking (FC) instances * * - The configuration must be identical in both the MCU MCAL driver and the Clock Configuration Tool (clock details). * - To inject a specific CMU error, define one of the following macros: `INJECT_CMU_0`, `INJECT_CMU_3`, or `INJECT_CMU_4`. * * Behavior After Destructive Reset: * - Following a destructive reset (either `MCU_CORE_CLK_FAIL_RESET` or `MCU_AIPS_PLAT_CLK_FAIL_RESET`), * execution will halt in the `while(wait)` loop. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: RTD 6.0.0 * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************