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Hi all,   Many customers complained about the K3 FlexIO I2S can not support continuous transferring because there is a gap time between 2 times of invoking SendData. This gap time will break the audio continuity and bring jitters. It is gapped by the transfer API closing and re-entry time cost.   To avoid this gap and implement a real continuous transferring, we made some changes with eDMA configurations. Finally, it works!   Besides, we also enabled eDMA half-complete interrupt to support double-buffer (ping-pong buffer) operation for user's further development.   Attachments are the example projects and corresponding introduction slides, please kindly check if you are interested in. Any problem, just let me know. Welcome your comments here.   Best Regards, Shuailin Li NXP GPIS, AE   --- Additional topic: Regarding the use of S32K3 SAI I2S to receive continuous audio data, user can use DMA continuous or S/G mode + ping-pong buffer. For details, please refer to the attached file & related codes (Use Case Share-S32K3 SAI I2S is used for audio data reception.pdf). For reference only.
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This post is an additional project to the S32K3 Low Power Management AN and demos.  A simple FlexCAN routine is configured for RX/TX and wakeup through the CAN0_RX pin (PTA6/WKPU19). The example is based on the S32K3X4EVB-T172, meaning that transceiver TJA1443 is used. TJA1443 only needs CAN0_EN & CAN0_STB pins in HIGH for normal configuration. In the example, the GREEN led is used to indicate that the MCU is in RUN mode. Once SW5 is pressed, MCU enters low power (STANDBY), and led is turned off. BLUE led toggles each time a CAN frame is received. MCU can be woken up with SW6 (WKPU42) or through a CAN RX. Note that CAN is not enabled in low-power, rather PTA6 (WKPU19) is configured for wake up, and once a rising edge signal is detected on the pin, MCU wakes up and reconfigures CAN module.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS3.6.2 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + FlexCAN.   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the FlexCAN0 instance for reception. Since RevB2 of the EVB was used for development, CAN TRXCVR used is TJA1443. TJA1443 is initialized in main code (CAN0_STB = 1 & CAN0_EN = 1). FlexCAN bitrate: Bitrate: 500 Kbps Sampling point: 81.25% Individual mask is set to 0x0, meaning all IDs are accepted. Main routine: Waits for SW5 to be pressed, or for FlexCAN interrupt. If SW5 is pressed, turns off green LED, disables FlexCAN and switches CORE_CLK to FIRC. It then configures both PTB19 (SW6) and PTA6 (CAN0_RX) for interrupt wakeups. If either SW6 is pressed or a CAN message is received (edge detect on PTA6), MCU wakes up and will wait for SW5 to be pressed again. FlexCAN is configured for INTERRUPT; If a CAN frame is received, bRxFlag is set to 1 inside the callback, blue LED is toggled, and an ACK frame is sent back. CAN communication can be tested either with another EVB, or with a PCAN analyzer connected to J32. PCAN-View log for dummy and ACK messages: This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + LPCMP.   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & LPCMP units for wake-up. The S32K3XX's LPCMP can operate in trigger mode in both standby and run mode to continuously scan the input channels. RTC-API and LPCMP must be configured before entering into standby mode as per below shown figure:   See chapters 61.1.5 Comparator Trigger Mode & 61.1.6 Interaction with RTC API to cause wakeup from the S32K3XXRM (Rev. 12) for further information.   The register configurations before entering Standby mode for LPCMP trigger mode operation is the following:   Configure RTC.APIVAL to set the period of the round robin operation. Execute standby mode entry. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Switches CORE_CLK to FIRC. Initializes the WKPU instance. Configures WKPU2 & WKPU42 (PTB19). Initializes and enables interrupt for LPCMP. Initializes RTC and sets the timer value (in RTCC - APIVAL) to 100ms. Starts timer. Enters standby (or fast standby). While in standby, PTA0/1/2 are active; if a voltage higher than 2.5V is detected (ICU LPCMP DAC Voltage Level = 127), or SW6 is pressed MCU will wake-up.  After wake-up, MCU resets and polls for SW5 to be pressed again. The RTC timer value can be changed with RTC_PERIOD_DELAY_MS(x) macro defined in Wkpu.h. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + RTC API.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & RTC units for wake-up. The RTC is present in always ON domain, hence available in RUN mode as well as in STANDBY mode. The chip contains one instance of RTC (Real Time Clock) timer and API (Autonomous Periodic Interrupt) timer, where both can perform 32-bit comparisons. Both RTC and API timers can generate interrupts as well as wake-up from low power modes. The following figure highlights the path for RTC API wake-up. Please refer to Chapter 69.3.2 API functional description from the S32K3XX reference manual (Rev. 12) for further information. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Switches CORE_CLK to FIRC. Initializes the WKPU instance. Configures WKPU2 & WKPU42 (PTB19). Initializes and enables interrupt for RTC. Enables RTC API and loads the APIVAL to 3000ms.  Starts timer. Enters standby (or fast standby). After the period defined, RTC API generates an interruption and MCU wakes up. After wake-up, MCU resets and polls for SW5 to be pressed again. The RTC API value can be changed with RTC_PERIOD_DELAY_MS(x) macro defined in Wkpu.h. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + RTC timeout.   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & RTC units for wake-up. The RTC is present in always ON domain, hence available in RUN mode as well as in STANDBY mode. The RTC can trigger a single wake-up event (timeout). When the RTC counter reaches a specific, pre-defined alarm time set by the user. RTC timeout is mapped as wake-up source 1. RTC0_CLK source is configured as SIRC_CLK, and SIRC_CLK must be enabled in standby mode. Chapter 69.3.1 RTC explains the functionality of the RTC timer. RTCVAL is updated at the point where no counter match is due as per the previous RTCVAL, the RTCF flag is set when the counter matches the new value. If there is a match when in the low-power mode, then the RTC first generates a wakeup request to force a wakeup to run mode, and then the RTCF flag is set. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Switches CORE_CLK to FIRC. Initializes the WKPU instance. Configures WKPU1 & WKPU42 (PTB19). Initializes and enables interrupt for RTC. Loads the RTCVAL value to 5000ms.  Starts the counter. Enters standby (or fast standby). After the period defined with RTC_TIME or RTC_PERIOD_DELAY_MS(x) macros defined in Wkpu.h, MCU wakes up. After wake-up, MCU resets and polls for SW5 to be pressed again. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + RTI (PIT0).  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & PIT for wake-up. The PIT0 instance includes a dedicated RTI (Real Time Interrupt) timer that runs on a separate oscillator clock and can be used for system wakeup. A key feature of this is power saving with a separate input clock for the RTI timer. All other timers share a common core clock. Note: Only PIT_0 supports the RTI feature, and exists in the Standby domain. This example does not poll for a SW press to enter and configure standby; Instead, the main function directly enters the Wkpu_EnterStandby() function which: Switches core clock to FIRC. Initializes and configures WKPU instance and wake-up source 3 (RTI). Initializes and configures PIT0 and PIT0 CH0 as set in Config Tools view. If EN_RUN_ICYCL_DUTY macro is enabled, configures PIT1 for user code before going to standby. Once Pit1_Notification is entered, runFlag is set to FALSE. Turns off LED. Enables RTI channel interrupt (otherwise, MCU cannot be woken up). Finally, sets the timeout value (WKPU_ICYCL_DUTY_TIME macro) and enters standby. This showcases the basic configuration for template on a fast-scanning power saving routine (for example, wake-up, measure ADC, go back to sleep). Keep in mind that power saving depends on the frequency of wake-up events. If MCU spends more time in Run mode rather than in Standby mode, power consumption is affected. The transition time from Standby mode to Run mode is quick. If the MCU only spends 9ms in Run and 1ms in Standby, the average current of the system will be considerably higher than if the MCU was running only 1ms every 1 second. Refer to S32K3 Low Power Management AN and demos for further information. After the period defined with either WKPU_ICYCL_DUTY_TIME, MCU wakes up. After wake-up, MCU resets and the cycle repeats. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + SIUL2.  ------------------------------------------------------------------------------ * Test HW: S32K312EVB-Q172 (SCH-50892 REV B) * MCU: S32K312 * IDE: S32DS v3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up and defines a section in linker file for 32KB of Standby RAM. How to use Standby RAM? Modify the linker file to separatethe 32KBstandby RAM(0x2040 0000 ~0x2040 8000) from int_sram memory region, and place standby .bss and .data or .text sections into the new region as well as adjust the link address symbols for customized initialization during startup. Initialize the standby RAM only if it’s Power-On Reset. Use key word attribute to define the variable/function in relevant memory section. Counter variable is placed in standby ram section: __attribute__ ((section (".sram_standby_bss"))) volatile int RunStandbyCounter0 = 0; Linker file (.ld) must be modified accordingly. Standby sections and link address symbols must be placed: MEMORY { int_pflash : ORIGIN = 0x00400000, LENGTH = 0x001D4000 /* 2048KB - 176KB (sBAF + HSE)*/ int_dflash : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128KB */ int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */ int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x0000F000 /* 60KB */ int_stack_dtcm : ORIGIN = 0x2000F000, LENGTH = 0x00001000 /* 4KB */ int_standbysram : ORIGIN = 0x20400000, LENGTH = 0X00000100 /* standby ram 256B*/ int_sram : ORIGIN = 0x20400100, LENGTH = 0x00007E00 /* 32KB - 0x100, needs to include int_sram_fls_rsv*/ int_sram_fls_rsv : ORIGIN = 0x20407F00, LENGTH = 0x00000100 int_sram_no_cacheable : ORIGIN = 0x20408000, LENGTH = 0x00007F00 /* 32KB , needs to include int_sram_results */ int_sram_results : ORIGIN = 0x2040FF00, LENGTH = 0x00000100 int_sram_shareable : ORIGIN = 0x20410000, LENGTH = 0x00008000 /* 32KB */ ram_rsvd2 : ORIGIN = 0x20418000, LENGTH = 0 /* End of SRAM */ } ... .sram_standby (NOLOAD): { . += ALIGN(4); *(.sram_standby_bss) } > int_standbysram ... __STANDBY_SRAM_START = ORIGIN(int_standbysram); __STANDBY_SRAM_SIZE = LENGTH(int_standbysram); Note 1: RAM ECC must be initialized only if it’s Power-on Reset. Note 2: CM7 CPU D-Cache MUST be disabled to use the Standby RAM area. Or set the standby RAM(0x2040 0000 ~0x2040 8000) as non-cacheable in MPU configuration. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Disables D-Cache. Initializes RAM ECC (if reset was Power-on Reset). Adds +1 to the standby counter placed in Standby RAM. Switches core clock to FIRC. Initializes the WKPU instance. Configures WKPU42 (PTB19). Enters standby. If SW6 is pressed, MCU will perform a software reset through the Power_Ip_PerformReset() API. After wake-up, MCU resets and polls for SW5 to be pressed again. In this application, LPUART6 (connected to USB OpenSDA interface) is enabled and will show previous reset reason (external reset, power-on reset, wakeup, functional reset), as well as printing standby counter between resets/standby cycles. Connect a USB cable to J40, and open a Serial terminal on PC for the serial device with these settings:   9600 baud rate   No parity   One stop bit  No flow control   After either a SW reset, or a wake-up cycle, the standby counter will increase. If a destructive reset or Power-on Reset is asserted, the counter is reset.    This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of ICU (WKPU) + DIO (GPIO).   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up. This is the simplest WKPU example. Pin PTB19 (WKPU42) is configured for wake-up.  The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Turns off green LED Switch system clock to FIRC (Option C - Boot Standby mode @24MHz). Initialize the Icu driver. Configures WKPU42 (PTB19). Enters standby. After pressing SW6, MCU wakes up, resets and polls for SW5 to be pressed again. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of ICU (WKPU) + DIO (GPIO).   ------------------------------------------------------------------------------ * Test HW: S32K396-BGA-DC1 (SCH-55517 Rev B2) * MCU: S32K396 * IDE: S32DS3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PEMicro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up. This is the simplest WKPU example. Pin PTB19 (WKPU42) is configured for wake-up.  The routine waits for SW8 to be pressed, then turns off LED1, and: Switches core clock to FIRC (Mode C Boot default from Table 125.). Initializes the WKPU instance. Configures WKPU42 (SW4). Enters standby (or fast standby). After pressing SW4, MCU wakes up, resets and polls for SW8 to be pressed again. If FAST_STANDBY is selected, Wkup_FastWkupBootAddress() is entered and both LED2 & LED3 blink before jumping to reset handler for full initialization. This example is provided as is with no guarantees and no support.
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This post presents two complementary FlexCAN communication examples for the S32K3X4EVB-T172 evaluation board, showcasing both low-level IP layer and AUTOSAR MCAL layer implementations. These examples are basic routines for configuring the component in normal/user mode, as the RTD examples are configured for loopback mode. To test CAN communication, another board or a CAN analyzer must be used. Since Rev. B2 of S32K3X4EVB-T172 was used to test the project, TJA1043 transceiver is mounted on the board and used to test the examples. ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS 3.6.2 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH ------------------------------------------------------------------------------ Example 1: FlexCAN IP Layer (LLD) This project demonstrates a basic FlexCAN setup using the IP-level driver. It configures a standard CAN message; with transmission through POLLING and reception using INTERRUPT. If TJA1153 transceiver is used, macro TJA1153 must be uncommented at the top of the project, and it will be initialized through a custom configuration sequence. If not used and the macro is commented, normal transceiver initialization is done (only CAN0_EN_PIN & CAN0_STB_PIN set to HIGH). Rx Filter mask type is individual and set to receive STD ID 123h.  Tx MB is set to STD ID 001h. FlexCAN bitrate was calculated with MPC5xxx/S32Kxx/LPCxxxx: CAN / CAN FD bit timing calculation. FlexCAN bitrate settings are 500kbps with 81.25% sample point  FPE_CLK: 24MHz Synch seg: 1 Prop seg: 4 Phase 1 seg: 8 Phase 2 seg: 3 Prescaler: 3 RJW: 3    Example 2: FlexCAN MCAL Layer (HLD) This project configures both Can_43_FLEXCAN and CanIf modules for CAN communication. Transmission is done via POLLING, while reception is configured via INTERRUPT.  Tx MB is set to STD ID 123h. Acceptance mask is set to 0x0 (accept all IDs). CAN messages are sent using Can_43_FLEXCAN_Write() and received using the CanIf_RxIndication() callback. After CanIf_bRxFlag is set, an ACK message is sent back. The GREEN LED toggles every 10 received messages. FlexCAN bitrate was calculated with MPC5xxx/S32Kxx/LPCxxxx: CAN / CAN FD bit timing calculation. FlexCAN bitrate settings are 500kbps with 81.25% sample point  FPE_CLK: 24MHz Synch seg: 1 Prop seg: 4 Phase 1 seg: 8 Phase 2 seg: 3 Prescaler: 3 RJW: 3  If TJA1153 transceiver is used, macro TJA1153_EVB_TRCV must be used. If not, use TJA1043_EVB_TRCV for standard transceiver initialization (CAN0_STB & CAN0_EN pins set to HIGH).          These examples are provided as is with no guarantees and no support. These are basic routines meant to be used as reference only.
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This simple example demonstrates how to configure and handle UART interrupts using the LPUART module on both S32K312EVB-Q172 & S32K312MINI-EVB. It sets up a UART callback function and initiates reception in single-byte mode. After each byte is received, the buffer is updated using  Lpuart_Uart_Ip_SetRxBuffer() , unless a newline character ( '\n' ) is detected, in which case a reception flag is set to signal the main loop. When the  LPUART_UART_IP_EVENT_END_TRANSFER  event occurs, reception is re-enabled using  Lpuart_Uart_Ip_AsyncReceive() . Note: Only basic event handling is implemented; other UART events are acknowledged but not processed. The example uses LPUART instance 6, enabling serial communication via the USB port (J40 on EVB & J9 on MINI EVB).  ------------------------------------------------------------------------------ * Test HW: S32K312EVB-Q172 & S32K312MINI-EVB  * MCU: S32K312 * IDE: S32DS3.6.2 * RTD release: 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ Running the example: 1. Open a Serial terminal on PC for the serial device with these settings:   115200 baud rate   No parity   One stop bit  No flow control   If using TeraTerm, ensure the transmit setting is configured to LF (Line Feed) to properly send newline characters when pressing Enter. 2. Build and run the example. Test result:   Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.
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This example project will show user how to use and configure the basic functionalities of ICU (WKPU) + CAN.   ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This project configures both Can_43_FLEXCAN and CanIf modules for CAN communication, along with the ICU (WKPU) module for wake-up. Transmission is done via POLLING, while reception is configured via INTERRUPT.  Tx MB is set to STD ID 123h. Acceptance mask is set to 0x0 (accept all IDs). CAN messages are sent using Can_43_FLEXCAN_Write() and received using the CanIf_RxIndication() callback. After CanIf_bRxFlag is set, an ACK message is sent back. If TJA1153 transceiver is used, macro TJA1153_EVB_TRCV must be used. If not, use TJA1043_EVB_TRCV for standard transceiver initialization (CAN0_STB & CAN0_EN pins set to HIGH).  FlexCAN bitrate is calculated with: CAN bit timing calculator sheet. CAN classic (non-FD) 24Mhz clock 500Kbps 81.3% Sample Point Main routine: Waits for SW5 to be pressed, or for FlexCAN Rx interrupt. If SW5 is pressed, turns off green LED, disables FlexCAN and switches CORE_CLK to FIRC. It then configures PTA6 (CAN0_RX) for wakeup. If a CAN message is received (edge detect on PTA6), MCU wakes up and will enter main routine again. If a CAN frame is received, MCU will wake-up and wait for SW5 to be pressed again. Note: The first CAN frame may not be fully received since there will be some time for the MCU to warm up from STANDBY mode back to RUN mode, so the application may need to ignore the first CAN frame. Note 2: In order to test this example, another CAN node must be connected to CAN0_OUT. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + GPT RTC API.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) or S32K344MINI-EVB * MCU: S32K344 * IDE: S32DS3.5 & S32DS3.6 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU & RTC units for wake-up. The RTC is present in always ON domain, hence available in RUN mode as well as in STANDBY mode.   The chip contains one instance of RTC (Real Time Clock) timer and API (Autonomous Periodic Interrupt) timer, where both can perform 32-bit comparisons. Both RTC and API timers can generate interrupts as well as wake-up from low power modes. The following figure highlights the path for RTC API wake-up. Please refer to Chapter 69.3.2 API functional description from the S32K3XX reference manual (Rev. 12) for further information.   The routine waits for SW5 to be pressed, then: Turns off the green LED Switches CORE_CLK to Option C - Boot Standby mode (CORE_CLK @ 24 MHz). Initializes the ICU driver. Configures RTC_API channel (WKPU0) Initializes GPT module. Starts timer and sets RTC_API_TIME. Enters standby. After the period defined, RTC API generates an interruption and MCU wakes up. After wake-up, MCU resets and polls for SW5 to be pressed again. The RTC API value can be changed with RTC_API_TIME definition. This example is provided as is with no guarantees and no support.
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This example project will show user how to use and configure the basic functionalities of WKPU + SIUL2 (GPIO).  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 (SCH-53148 REV B2) * MCU: S32K344 * IDE: S32DS v3.5 & S32DS v3.6.x * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ This example routine configures the WKPU unit for a GPIO interrupt wake-up. This is the simplest WKPU example. Pin PTB19 (WKPU42) is configured for wake-up.  The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Switches core clock to FIRC. Initializes the WKPU instance. Configures WKPU42 (PTB19). Enters standby (or fast standby). After pressing SW6, MCU wakes up, resets and polls for SW5 to be pressed again. This example is provided as is with no guarantees and no support.
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The attached spreadsheet provides mapping between EIM and DCM faults for the S32K3x1, S32K3x2, S32K344, S32K324, and S32K314 devices. Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.
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S32K1xx   S32K144 Example S32K144 CMP Round-robin S32DS2.0  Example S32K144 Verify Backdoor Access Key S32DS1.3  Example S32K144 FlexCAN0 RXFIFO DMA nonSDK S32DS13  Example S32K144 PDB ADC trigger DMA ISR S32DS  Example S32K144 Flash RW simple S32DS  Example S32K144 DMA memory copy test S32DS  Example S32K144 EEEPROM usage Example S32K144 EEEPROM usage - No SDK  Example S32K144 RTC VLPS  Example S32K144 WDOG RCM interrupt  Example S32K144 SRAM ECC Injection  Example S32K144 RAM Retention S32DS.R1 Example S32K144 I2C Master MPL3115A2 S32DSR1_v3  Example S32K144 FlexCAN RXFIFO DMA S32DS.ARM.2018.R1  Example S32K144_printf_implementation - S32DS_1.0  Example S32k144 UART printf/scanf under FreeRTOS - S32DS Example S32K144 SDK Function call on configurable period using LPIT timer.  Example S32K144 .noinit section usage Example S32K144 PDB ADC DMA S32DS.ARM.2018.R1   Example S32K144 RAM selftest simple S32DS 2018.R1  Example S32K144 Position Independent Code  Example S32K144 FlexCAN Pretended Networking STOP mode test S32DS.ARM.2.2  Example S32K144 LPIT DMA LPSPI  Example S32K144 FlexCAN TX/RX/Error ISR test S32DS2.2  Example S32K144 FlexIO Idle Detection S32DS2.2   S32K142 Example_S32K142_LMEN_Cache_v1_0_S32DS3.6_RTD300  Lauterbach_Script_For_MDM_AP_Mass_erase_S32K142    S32K146 Example S32K146 Set_whole_FlexRAM-as_RAM S32DS.ARM.2.2   S32K148 Example S32K148 PDB0-PDB1 ring S32DS3.4 RTM4.0.3  Example S32K148 PDB0-PDB1 ring DMA S32DS3.4 RTM4.0.3  Example S32K148 GPIO Interrupt     S32K116 Example S32K116 WDOG Fast Test  Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2  Example S32K116 FlexCAN PN STOP S32DS.ARM.2.2 Example S32K116 FlexCAN VLPR test S32DS.ARM.2.2   S32K118 Example S32K118-SRAM-keep_data_over_SW_reset v0_1 S32DS.ARM.2.2   S32K3xx   S32K312 Example S32K312 ADC_IP Continuous Scan DMA S32DS36 RTD600    S32K344 Example S32K344 PIT BTCU ADC DMA DS3.4 RTD100   Example S32K344 FlexCAN_Ip TX/RX/EnhanceRXFIFO test S32DS3.4 RTD200     Example Siul2_Port_Ip_Example_S32K344_ITCM_DTCM S32DS3.4 RTD300   Example S32K344 LPUART RX/TX ISR FreeRTOS S32DS36 RTD600    Example_S32K344_MCAL_MCU_ClockMonitor_v1_0_S32DS36_RTD600    Example_S32K314_DTCM1_Backdoor_RTD201_DS34_v3    Example_Reg_Prot_Flash_Controller_S32K344   Example S32K344 PIT SWtrig ADC ANAMUX S32DS 3.6.0 RTD 6.0.0   Example S32K344 EMAC lwIP FreeRTOS miniEVB S32DS 3.6.1 RTD 6.0.0   Example S32K344 EMAC lwIP FreeRTOS MRCANHUB S32DS 3.6.1 RTD600   Example_S32K344_BIST_eMCEM_SPD106_v2_0_S32DS365_RTD700      S32K358 Example S32K358 FlexCAN TXRX ISR S32DS35 RTD400/500   Example S32K358 GMAC 100M lwIP FreeRTOS S32DS 3.6.1 RTD600   Example S32K358 GMAC 1G lwIP FreeRTOS S32DS 3.6.1 RTD600     S32K388 Example S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600   S32K389 Example S32K389 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD 6.0.0   Example S32K389 GMAC1 SABRE lwIP FreeRTOS S32DS 3.6.1 RTD600  
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The script performs secure‑recovery and mass‑erase initialization of locked S32K142 MCUs by keeping the device in system reset (PTA5 RESET_B held low) from the moment of power‑on. Before running the script, connect PTA5 (RESET_B) to VSS, power‑cycle the MCU, and start the script. The script first reads the MDM‑AP Status register to determine the MCU’s security and flash‑ready state, then prompts the user to initiate a mass‑erase operation through the MDM‑AP Control register. After the mass erase completes, the user is instructed to release RESET_B (remove PTA5 from VSS), after which the debugger re‑attaches and displays the flash configuration area at address 0x400. Finally, the script prompts whether the MCU should be reprogrammed from an ELF file, and if confirmed, programs flash, loads the project, and executes it.
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**************************************************************************************************** * Detailed Description: * This example uses BIST and EMCEM drivers from SPD 1.0.6. * BIST and EMCEM can be enabled or disabled using macros. * * BIST runs immediately after a power-on reset and triggers an ST_DONE reset. * EMCEM initialization is only possible after a system reset without an attached debugger. * Therefore, wait loops (controlled by macros) are used to manage execution flow * for both BIST and EMCEM. * * Fault injection is selected via macros: * - FAULT_EMCEM_DCM_NCF_1_AD_EDC_ERR_OUT → handled via NMI * - FAULT_EMCEM_DCM_NCF_2_PRAM1_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_2_ITCM_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_3_PFO_CODE_ERR → FCCU alarm → (if TIMEOUT_PFO_CODE_ERR) → NMI * - FAULT_EMCEM_DCM_NCF_5_STCU_NCF → handled via FCCU alarm * - FAULT_EMCEM_DCM_NCF_7_SW_NCF_0 → FOSU Destructive reset * (read resetReason after reset, MCU_FCCU_FTR_RESET). * FOSU triggers as no FCCU reaction is configured for NCF_7 * while FCCU is enabled and reactions are configured for other faults. * * ------------------------------------------------------------------------------------------------ * MCU: S32K3x4EVB-Q257 * Fsys: 160 MHz PLL with 16 MHz crystal reference * Debugger: Lauterbach Trace32, S32DS IDE 3.6.5 * Target: internal_FLASH ****************************************************************************************************
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/********************************************************************************************** * File main.c * Owner Daniel Martynek * Version 1.0 * Date May-12-2026 * Classification General Business Information ********************************************************************************************** * Detailed Description: * The code enables the data cache, reads a value from DFlash to load it into the cache, * then uses the LMEM interface to inspect and directly overwrite the corresponding cache line. * Finally, it reads the same address again through the CPU, which returns the modified value * from the cache instead of the original data stored in DFlash. * * In this simple setup, where only the data cache is enabled, the code executes from PFlash, * and the accessed data is located in DFlas — the cache line is unlikely to be re-evaluated. * Therefore, the CPU may consistently return the modified value - this behavior is not guaranteed. * ------------------------------------------------------------------------------------- * MCU: S32K142 * Fsys: 48MHz, FIRC * RTD: S32K1_RTD_3_0_0_QLP06_D2603_ASR_REL_4_7_REV_0000_20260320 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************
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