I don’t use SDHC, and we use SPI at 2.5V (CVDD=2.5V). In this case for P4080 unused SDHC pins are pulled up to 2.5V. If I want to maintain compatibility with P4040, what happens when unused SDHC pins (SDHC_DATA [0-3], SDHC_CMD) in P4040 are pulled up to 2.5V instead of 3.3V? As long as the pullup on these pins satisfies the minimum Vih of 2.0 V for a 3.3V input then this would be ok. Alternative is to pull to ground. I want to lower the CPU power consumption with make CPU frequency from 1.2GHz to 1 GHz or 800 MHz for P4080 hardware. When P4080 core is configured to be 1GHZ/ 800 MHz, what is the core’s power consumption? If you disable L2 cache, you can use 47mW/100MHz per core for lower bins. If L2 is not disabled, then you need to use 65mW/100MHz per core for the lower bin. If I don’t use SDHC, how should I connect the SDHC_DATA and SDHC_CLK? SDHC is output signal and you can leave as NC. It shouldn't matter to either pull-up or pull-down for unused SDHC interfaces. In Freescale P4080_DS schematics, the "HRST" button is connected to the LRST_B signal which is routed to the FPGA. What logic is applied to the LRST_B signal inside the FPGA, and what is the FPGA output signal connected to on the CPU? LRST is one of the Reset sources that is coming from the Pushbutton. It will cause: CPU_PORESET CPU_TRST And Peripheral_reset (PHY_RST_B, GEN_RST_B, SGMII_XAUI_SLOT_RST_B) Does access to CCSR & DCSR registers require CoreNet usage in P4080? Can a SEU single-bit error in any CoreNet register prevent further reading from internal config registers? Yes, CCSR/DCSR accesses go through CoreNet. There is no ECC on CCSR internal registers so there is no automatic scrubbing or repair that is possible. So such prevention is not possible. I have NOR Flash, NAND Flash, NVRAM and CPLD connected on eLBC with data buffer in between. All devices are in high impedance when not selected. Should the OE of data buffer be connected to GND directly or by using “AND” gate with CS0, CS1…CSn as the OE? It should be “AND”ed with all used CSn to generate the OE. This can prevent any potential data bus conflict. I do not use Secure Boot feature in my P4080 design. What should I do with Vdd_LP pin? If Secure Boot feature is not to be used, VDD_LP can be left unconnected, but should be tied to GND to reduce noise.

Usually, when I turn on the option of "reset target on launch" CW resets CPU again while connecting to CPU. With P4040, CodeWarrior (CW) does not connect to CPU when the option is on, only when I disable the option, CW can connect to CPU. What could be the problem? . "Reset target on launch" asserts HRESET to the target, thereby resetting the hardware. In most cases this is a required step, but where you don't want to assert HRESET or where your Target Initialization (.cfg) file does this for you with the "reset 1" command, you can do without this option enabled. "P10xx-P20xxRDB_P1011_jtag.txt" JTAG Configuration file is required by 8.8 CW PA for all single-core P10xx processors. Please load the “P20xxRDB_P1011_jtag.txt" JTAG Configuration file in your USB TAP configuration panel you mentioned about. 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1.

How can I ensure that Ethernet flow control is turned on through the register setting in P4040? Please try the below steps to enable Ethernet flow control: 1) Set MACCFG1[Rx_Flow] && MACCFG1[Tx_Flow] to 1 2) Set RCTRL[LFC] to 1. Setting the flow control bits Rx_Flow and Tx_Flow means that the MAC can detect and act on PAUSE flow control frames, receive and transmit respectively. There are two ways you can confirm or see them in action: 1) Software sending a PAUSE frame through TCTRL[TFC_PAUSE] 2) Changing some hidden FIFO threshold registers, such that the FIFO is about to overflow and that triggers eTSEC logic to send a PAUSE.

Can the P4040 eSPI controller address 4-byte (32-bit) addressable EEPROMs in any situation? Yes, eSPI controller addresses 4-byte addressable EEPROMs in any situation. For P4040, is it possible to boot from a 4-byte EEPROM using the on-chip ROM? No. The software in the on-chip ROM only supports 16-bit addressable or 24-bit addressable EEPROMs.

Do we have an internal pull up on LA20 pin in P4040E? According to hardware spec for P4040, LA20 pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. Assuming that I did not include a pull up or pull down and assuming no device was asserting LA20--what state do we sample at POR? If LA20 is left floating at POR, would one read the SVR for P4040E (80ED0211) OR P1011E (80ED0011)? According to hardware spec for P4040, LA20 pin "must be pulled down with a 4.7K resistor". So the default in case that a design doesn't include an external pull (as required by the spec) is for it to sample as a '1'. Leaving the pin NC (floating) at POR is effectively an out of spec configuration.

For P4040, does DDRCLK and PCIe (SerDes) ref clock support a spread spectrum reference? DDRCLK and PCIe (SerDes) ref clock support spread spectrum. Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF clock. What are the DDRCLK and PCIe (SerDes) reference clock spread spectrum parameters for P4040?  DDRCLK and PCIe (SerDes) reference clock are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used.

If I don’t use the USB interface in the 3041, can I leave USBx_VDD_3P3 and USBx_VDD_1P0 pins not connected? In P4040 they are reserve with note do not connect. Can they be connected to 3.3V and 1.0V respectively? USB_VDD_1P0 must be tied to 1V or the platform voltage (based on whatever the SOC core digital power supply is). USB_VDD_3P3 can be left floating. If I don’t use USB, is it safe to leave USBx_IBIAS_REXT and USBx_VDD_1P8_DECAP unconnected? If USB is not to be used at all, keep the following USB signals floating : USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP and USB2_VDD_1P8_DECAP, USB1_VDD_3P3, USB2_VDD_3P3.

What is requirement for the voltage ripple of DDR3 controller MVref? The nominal value of MVref is 1.5V. 1%, +/- 7.5mV is the tolerance value for MVref (ripple range). Can you please explain the RDRVR resistance for DDR3 SDRAM memory interface? RDRVR is the "Driver" resistance. It is the resistance at the driver side. Half strength is ~40 ohms and full strength is ~20 ohms. How can I determine the power rating of the resistor connected to MDIC0 and MDIC1 for both half strength and full strength? The MDIC resistors connected to MDIC [0:1] signals used for either full or half drive strength calibration do not draw much current. So you can use 1/16W rated resistors for either half or full drive calibration.

The SGMII SerDes of the 3041 can operate at either 1.25G or 2.5G. Is there a register to configure this or it just depends on the clock multipliers of the SerDes PLL? As long as you select the RCW settings for SRDS_PRTCL and the DIV and RATIO settings to select the clock speed, the SerDes registers will default to the correct value based on those RCW settings. Does P3041 SerDes in XAUI mode support 10GBase-CX4 (IEEE802.3 clause54)? In other words, are SerDes XAUI receivers and transmitters capable of communication over a 15 meter 10GBase-CX4 cable? P3041 is not designed for such long distances. An appropriate 10GBASE-CX4 PHY is needed to support such distances.

I don’t use SDHC, and we use SPI at 2.5V (CVDD=2.5V). In this case for P3041 unused SDHC pins are pulled up to 2.5V. If I want to maintain compatibility with P4040, what happens when unused SDHC pins (SDHC_DATA [0-3], SDHC_CMD) in P4040 are pulled up to 2.5V instead of 3.3V? As long as the pullup on these pins satisfies the minimum Vih of 2.0 V for a 3.3V input then this would be ok. Alternative is to pull to ground. I want to lower the CPU power consumption with make CPU frequency from 1.2GHz to 1 GHz or 800 MHz for P1031 hardware. When P3041core is configured to be 1GHZ/ 800 MHz, what is the core’s power consumption? If you disable L2 cache, you can use 47mW/100MHz per core for lower bins. If L2 is not disabled, then you need to use 65mW/100MHz per core for the lower bin. If I don’t use SDHC, how should I connect the SDHC_DATA and SDHC_CLK? SDHC is output signal and you can leave as NC. It shouldn't matter to either pull-up or pull-down for unused SDHC interfaces. In Freescale P3041_DS schematics, the "HRST" button is connected to the LRST_B signal which is routed to the FPGA. What logic is applied to the LRST_B signal inside the FPGA, and what is the FPGA output signal connected to on the CPU? LRST is one of the Reset sources that is coming from the Pushbutton. It will cause: CPU_PORESET CPU_TRST And Peripheral_reset (PHY_RST_B, GEN_RST_B, SGMII_XAUI_SLOT_RST_B) I do not use Secure Boot feature in my P3014 design. What should I do with Vdd_LP pin? If Secure Boot feature is not to be used, VDD_LP can be left unconnected, but should be tied to GND to reduce noise. I have Nor Flash, Nand Flash, NVRAM and CPLD connected on eLBC with data buffer in between. All devices are in high impedance when not selected. Should the OE of data buffer be connected to GND directly or by using “AND” gate with CS0, CS1…CSn as the OE? It should be “AND”ed with all used CSn to generate the OE. This can prevent any potential data bus conflict. Does access to CCSR & DCSR registers require CoreNet usage in P3041? Can a SEU single-bit error in any CoreNet register prevent further reading from internal config registers? Yes, CCSR/DCSR accesses go through CoreNet. There is no ECC on CCSR internal registers so there is no automatic scrubbing or repair that is possible. So such prevention is not possible.

If I select a SerDes Mux config using a PCIe controller on 2 lanes, is it possible to use just one lane, although it is configured to two lanes PCIe? Do you have any advice for such configuration? A13. Yes, it is possible to use just one lane while selecting SerDes Mux config using a PCIe controller. From the P2040 SERDES options ECI will be setting PCIe2 to use lanes E & F. If you have them pinned out to x2 connector then it will automatically train down to x1 if a x1 device is inserted. If you don't want to use lane F then power lane F down during reset and set SRDSPCCR0[PEX2_CFG] to x1. What is the function of TRSTDIR bit found in Table 3-26/B1GCRA1–B1GCRJ1 Field Descriptions B1GCRA1 [TRSTDIR] in P2041 RM? It controls Lynx Tx lane reset function for multi-lane protocols. For multi-lane protocols where the lanes are from left to right (PEX, XAUI), it should be set to 1 while for protocols where the lanes are from right to left (SRIO, Aurora), it should be set to 0. For single-lane protocols (SGMII, SATA) it doesn’t matter. It is paired with BnGCRm0[1STLANE], which determines the master source clock lane for a multi-lane protocol (must always be =1 for nominal lane 0 for the protocol, e.g. lane A for PEX on lanes A-D, and =0 for all other lanes).

For P2041, if USB1 and USB2 ports are not implemented, what to do with the unused USB ports ie tie them to ground, 3.3V or leave them unconnected? If USB is not to be used at all, keep the following USB signals floating: USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP, USB2_VDD_1P8_DECAP, USB1_VDD_3P3 and USB2_VDD_3P3. The following signals should be pulled-down: USB1_VBUS_CLMP, USB2_VBUS_CLMP and USB_CLKIN. Also, pins USB_VDD_1P0 and USB2_VDD_1P0 must be tied to 1V or the platform voltage (whatever is the SOC core digital power supply) If USB_VDD_3P3 must be connected to 3.3V, will the power sequence be same as other 3.3V (OVDD) (no special power sequence for USB_VDD_3P3)? Even if PHY is not used, USB_VDD_1P0 must be tied to 1V or the platform voltage (whatever is the SOC core digital power supply), other pins can be left floating: USB1_IBIAS_REXT, USB2_IBIAS_REXT, USB1_VDD_1P8_DECAP and USB2_VDD_1P8_DECAP, USB1_VDD_3P3, USB2_VDD_3P3. If signals USB_VDD_3P3 and USB_VDD_1P8 are left floating, there is no need to take of power sequencing on these pins, only USB_VDD_1P0 must be a part of standard power sequencing requirements. If signals USB_VDD_3P3 and USB_VDD_1P8 are used (i.e. not left floating), power sequencing is to be done as under: Follow a minimum ramp time of 350us on USB_VDD_3P3(most regulators would give a 350us ramp time) and standard power sequencing on USB_VDD_1P0,USB_VDD_3P3. USB_VDD_1P8_DECAP would only have 1uF capacitor and is automatically tolerant of sequencing on rest of the supplies are sequenced properly. Also based on silicon validation: There is no power down sequencing to be followed on the PHY. There requirements were added as a backup strategy in case the new regulator in the IP had a problem. We have tested this regulator, so no power down sequencing requirements is needed. There is no need to supply any power to USB_VDD_1P8_DECAP, as the circuit is working fine.

I wanted to choose boot location for P2040. Does P2040 supports GPCM 16 bit NOR boot? Yes, P2040 supports GPCM 16 bit NOR boot. It can be done by configuring 4 bits (bit 192 to 195) of RCW source location to 1101. If I use NOR FLASH as boot device, can NOR FLASH be used as RCW storage device? Do I need an extra SPI flash is required or not? Yes, you can use NOR flash and the options are 0x1100 and 0x1101 (listed in the table 4-26 in P2040 Reference Manual). Does P2040 support to boot from SPI flash? Yes, P2040 can boot from SPI flash. But it is different from booting from NOR flash. One eSPI pre-bootloader is required.

Does P2040 dTSEC support 1000Base-X with an opposite 1000Base-X device like FPGA? I can see it is supported in P3041 Reference Manual (RM) but there is no description regarding TBI registers in P2040RM RM revE. Yes, P2040 dTSEC support 1000Base-X with an opposite 1000Base-X device using the same TBI mode as P3041. Does P2041 support pre-emphasis on SGMII ports? If yes, please send me the reference. There is no requirement of pre-emphasis in the SGMII protocol. However, Lynx5G based products such as Lynx20/ P2041 support the pre-emphasis in the SGMII protocol. The following are the settings:- 3dB : tx_ratio_post1q[2:0] = 100, tx_eq_type[1:0] = 01, tx_sgn_post1q = 1 6dB : tx_ratio_post1q[2:0] = 110, tx_eq_type[1:0] = 01, tx_sgn_post1q = 1 Please note Lynx3G based products do not support the pre-emphasis in the SGMII protocol. Is IEEE 1588 supported on all 5 Ethernet ports or on only 4 ports for P2040? In the Reference Manual on page 37-3, the only restriction mentioned is that 1588 is not supported for SGMII mode when using 10/100Mbps. On page 38-1, first paragraph it is mentioned that, "The 1588 timer module interfaces to up to four 10/100/1000 or one 10G Ethernet MACs (P2041 only)." Can you please clarify? IEEE 1588 is supported on all ethernet MACs in P2040. It is supported in below combinations: P2040: The 1588 timer module interfaces to up to five 10/100/1000 Ethernet MACs, providing current time, alarm, and fiper support. What are the DC specifications of IEEE1588 pins in P2040? i.e. Vih/Vil. The DC specification of 1588 would be similar to Ethernet Management Interface DC spec. You can use the table 34 and table 35 for 1588 DC given in P2040 reference manual.

Can you please give more details about 32 address signals for the eLBC implementation on P2040? Below is a detailed explanation of 32 address signals for the eLBC implementation on P2040: LAD[0:15] - these are multiplexed address/data signals that need to be externally latched using the LALE signal. LA[16:31] - these are dedicated address signals. LAD[0] is the most significant address signal and LA[31] is the least significant address signal. Can the Local Bus FCM support two, 2GByte (16Gbit) NAND devices, if they are the appropriate page size (2K SLC)? FCM can support two devices, each one is connected to a separate /CS.

What is the integrated phase noise jitter requirement for SD_REF_CLK and SYSCLK for P2041? We don't have the integrated phase noise jitter, the SYSCLK we defined the period jitter and phase noise. For SD_REF_CLK, we follow the PCIe industrial standard spec and it defined peak-to-peak jitters. What is the PLL loop bandwidth of internal PLL in P2040 which uses 100MHz and 125MHz refclks from system? The PLL loop bandwidth of internal PLL is >= 500 KHz. The PLL bandwidth varies with many factors including ref clock rate.

P2041 hardware spec recommends that pins EM2_MDC and EM2_MDIO must be pulled up to 1.2 V through a 180 Ω ± 1% resistor for EM2_MDC and a 330 Ω ± 1% resistor for EM2_MDIO. If these pins are not being used and there is no 1.2V on board, what should be done to these pins? EM2_MDC can be left as floating. EM2_MDIO needs to be tied low to GND or through a 2–10 kΩ resistor to GND. P2041 Hardware spec mentions that local bus address pins LA16 and LA17 must not be pulled down during power-on reset, while P204x RDB Schematics document mentions that LA17 and LA16 are pulled down optionally for CFG_SVR [1:0]. Can you please clarify? Pin LA17 and LA16 are POR pins for CFG_SVR [1:0], and they have internal weak pull-up. To get correct SVR value for P2041, pin LA17 needs external pull low. LA16 = 1 and LA17 = 1 for P2040. LA16 = 1 and LA17 = 0 for P2041. Is IEEE 1588 supported on all 5 Ethernet ports or on only 4 ports for P2040? In the Reference Manual on page 37-3, the only restriction mentioned is that 1588 is not supported for SGMII mode when using 10/100Mbps. On page 38-1, first paragraph it is mentioned that, "The 1588 timer module interfaces to up to four 10/100/1000 or one 10G Ethernet MACs (P2041 only)." Can you please clarify? IEEE 1588 is supported on all ethernet MACs in P2040. It is supported in below combinations: P2040: The 1588 timer module interfaces to up to five 10/100/1000 Ethernet MACs, providing current time, alarm, and fiper support. What are the DC specifications of IEEE1588 pins in P2040? i.e. Vih/Vil. The DC specification of 1588 would be similar to Ethernet Management Interface DC spec. You can use the table 34 and table 35 for 1588 DC given in P2040 reference manual. To which rail should the TEST_SEL pin be pulled up to disable cores two and three, the OVdd (3.3V) rail or the Vdd (1.0V) rail? You can follow below steps to disable the two cores: 1. TEST_SEL pin must be pulled high (100 kΩ to 1 kΩ) to OVDD. 2. Disable Core2 and Core3 by setting core disable register, COREDISR[CD2] and COREDISR[CD3], to 1. Also, do not tie VDD_CB to GND as it is tied to VDD_CA_PL now. What is the consumption current of POVdd for P2040? The maximum current per eFuse block is 25mA. Since we have 2 such block, maximum current is 50mA. Note that except for programming period, POVDD must be grounded at all times (zero current). Pins F24 and E23 are documented as emi2_mdio and emi2_mdc in the P2041 data sheet and as reserved in the P2040 data sheet. Can F24 (reserved on P2040, MDC on P2041) be left floating? Can E23 (reserved on P2040, MDIO on P2041) be tied low or pulled high to a voltage other than 1.2V? What is the recommended connection for these unused pins? emi2_mdc can be left as floating, but emi2_mdio needs to be tied to GND or through a 2–10 kΩ resistor to GND. For P2040, table 12 indicates that TSEC_1588_ALARM_OUT1/EC1_TXD0 should be tied low if not used. TSEC_1588_ALARM_OUT1/EC1_TXD0 is an output, does it need to be tied low or can it be left no connect? TSEC_1588_ALARM_OUT1/EC1_TXD0 is an output, it can be left no connect.

Can you please share throughput numbers for P2010 and eSDHC interface? The basic data rate is 200MB/s for SD/MMC cards using 4 parallel lanes and 416Mbps for MMC using 8 parallel lanes For P2010/P2020, is the SD device / card handled as a block device as it is for Compact flash device? If handled as block device is that implemented by internal logic or should it be implemented in sw / fw? Yes, P2010/P2020 is handled as a block device and it does single or multi-block read/writes. This is handled by internal logic and is set up via the eSDHC register set through the drivers. Does P2010/P2020 eSDHC interface support a SDHC card above 4GB? Yes, eSDHC interface does support a SDHC card above 4GB. The eMMC standard is introduced in JESD84-A44. The new features of the eMMC that eSDHC does not support, are not supported. However, the basic operation of the MMC card is supported.

For P2010/P2020, is any way that the CPU can read and write the full 72-bit wide DDR memory bus, bypassing the ECC logic? I want to know if the memory controller can be configured for the 72-bit wide DDR memory bus to bypass the ECC logic. It is not possible to bypass the ECC and read/write using full 72-bit wide bus. The controller uses the last byte lane to generate ECC info and cannot be bypassed. For P2010/P2020 DDR SDRAM refresh, can you please advise how to "exactly" calculate the appropriate value of [REFINT] if such worst case scenario in which refresh command issue timing is postponed is taken into account? The refresh interval should be set as high as allowable by the DRAM specifications. This should be calculated by using tREFI in the DRAM specifications, which may depend upon the operating temperature of the DRAM. In addition, to allow a memory transaction in progress to be completed when the refresh interval is reached and not violating the device refresh period, set the REFINT value to a value less than that calculated by using tREFI. The value selected for REFINT could be larger than tREFI if the DDR_SDRAM_CFG[NUM_PR] has a value higher than 1. To calculate the max possible value when DDR_SDRAM_CFG[NUM_PR] is higher than 1, use the following formula: (tREFI/clk period) x (NUM_PR) = REFINT A timing tDISKEW (skew between MDQS and MDQ) is depicted in DDR2 and DDR3 SDRAM Interface Input Timing Diagram in P2010/P2020 Hardware spec. For measuring tDISKEW, please instruct me from which point of the MDQS waveform and to which point of MDQ waveform should be measured? For measuring MDQS, it should be at the cross point. For case of MDQ it is derated to the VREF. Why does MCK to MDQS Skew tDDKHMH has such a high value of +/-525ps for DDR3 800M data rate for P2010/P2020? I am afraid that write-leveling can NOT remove all internal MCK to MDQS skew from tDDKHMH. Can you please let me know how much internal skew will be removed after write-leveling? tDDKHMH value of +/-525ps for P2010 part is a conservative value in the HW spec. For DDR3 with write leveling enabled, this AC timing parameter would be a non-factor.

P2010/P2020 H/W spec describes that Max SYSCLK frequency is 100MHz. Generically when user inputs 100MHz clock, actual clock speed become more faster. I think P2010/P2020 has enough margin for faster SYSCLK as long as I use up to 100MHz oscillator. Is my understanding correct? Yes, your understanding is correct. As long as you use 100MHz oscillator it should be fine.