What is the integrated phase noise jitter requirement for SD_REF_CLK and SYSCLK for P2041?
We don't have the integrated phase noise jitter, the SYSCLK we defined the period jitter and phase noise. For SD_REF_CLK, we follow the PCIe industrial standard spec and it defined peak-to-peak jitters.
What is the PLL loop bandwidth of internal PLL in P2040 which uses 100MHz and 125MHz refclks from system?
The PLL loop bandwidth of internal PLL is >= 500 KHz. The PLL bandwidth varies with many factors including ref clock rate.
