P2040/P2041Hardware Specifications/Reference Manual Specific FAQs

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P2040/P2041Hardware Specifications/Reference Manual Specific FAQs

P2040/P2041Hardware Specifications/Reference Manual Specific FAQs

P2041 hardware spec recommends that pins EM2_MDC and EM2_MDIO must be pulled up to 1.2 V through a 180 Ω ± 1% resistor for EM2_MDC and a 330 Ω ± 1% resistor for EM2_MDIO. If these pins are not being used and there is no 1.2V on board, what should be done to these pins?

EM2_MDC can be left as floating. EM2_MDIO needs to be tied low to GND or through a 2–10 kΩ resistor to GND.

P2041 Hardware spec mentions that local bus address pins LA16 and LA17 must not be pulled down during power-on reset, while P204x RDB Schematics document mentions that LA17 and LA16 are pulled down optionally for CFG_SVR [1:0]. Can you please clarify?

Pin LA17 and LA16 are POR pins for CFG_SVR [1:0], and they have internal weak pull-up. To get correct SVR value for P2041, pin LA17 needs external pull low.

LA16 = 1 and LA17 = 1 for P2040. LA16 = 1 and LA17 = 0 for P2041.

Is IEEE 1588 supported on all 5 Ethernet ports or on only 4 ports for P2040? In the Reference Manual on page 37-3, the only restriction mentioned is that 1588 is not supported for SGMII mode when using 10/100Mbps. On page 38-1, first paragraph it is mentioned that, "The 1588 timer module interfaces to up to four 10/100/1000 or one 10G Ethernet MACs (P2041 only)." Can you please clarify?

IEEE 1588 is supported on all ethernet MACs in P2040. It is supported in below combinations:

P2040: The 1588 timer module interfaces to up to five 10/100/1000 Ethernet MACs, providing current time, alarm, and fiper support.

What are the DC specifications of IEEE1588 pins in P2040? i.e. Vih/Vil.

The DC specification of 1588 would be similar to Ethernet Management Interface DC spec. You can use the table 34 and table 35 for 1588 DC given in P2040 reference manual.

To which rail should the TEST_SEL pin be pulled up to disable cores two and three, the OVdd (3.3V) rail or the Vdd (1.0V) rail?

You can follow below steps to disable the two cores:

1. TEST_SEL pin must be pulled high (100 kΩ to 1 kΩ) to OVDD. 2. Disable Core2 and Core3 by setting core disable register, COREDISR[CD2] and COREDISR[CD3], to 1.

Also, do not tie VDD_CB to GND as it is tied to VDD_CA_PL now.

What is the consumption current of POVdd for P2040?

The maximum current per eFuse block is 25mA. Since we have 2 such block, maximum current is 50mA.

Note that except for programming period, POVDD must be grounded at all times (zero current).

Pins F24 and E23 are documented as emi2_mdio and emi2_mdc in the P2041 data sheet and as reserved in the P2040 data sheet. Can F24 (reserved on P2040, MDC on P2041) be left floating? Can E23 (reserved on P2040, MDIO on P2041) be tied low or pulled high to a voltage other than 1.2V? What is the recommended connection for these unused pins?

emi2_mdc can be left as floating, but emi2_mdio needs to be tied to GND or through a 2–10 kΩ resistor to GND.

For P2040, table 12 indicates that TSEC_1588_ALARM_OUT1/EC1_TXD0 should be tied low if not used. TSEC_1588_ALARM_OUT1/EC1_TXD0 is an output, does it need to be tied low or can it be left no connect?

TSEC_1588_ALARM_OUT1/EC1_TXD0 is an output, it can be left no connect.

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Last update:
‎08-06-2012 10:05 AM
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