Quick Guide on Booting i.MX95 with ND/LD Mode

EsaHuang

On i.MX95, OD, ND, and LD represent different system operating modes used to balance performance and power consumption. OD (OverDrive) mode targets the highest performance, allowing higher clock frequencies with a higher SoC supply voltage. ND (Nominal Drive) mode provides the standard operating point for normal performance and power efficiency. LD (Low Drive) mode is intended for lower-power operation, reducing voltage and limiting clock frequencies to save energy. In practice, switching between these modes involves coordinated changes of VDD_SOC, system clocks, and DDR operating frequency so that the device can move between high-performance and low-power states safely and efficiently.

Here is a table about the Maximum frequency of modules of different modes.

	OverDrive Mode	Nominal Mode	LowDrive Mode
VDD_SOC (typical)	0.9 V	0.85 V	0.8 V
VDD_ARM (typical)	0.9 V	0.85 V	0.8 V
A55 frequency	1800 MHz	1400 MHz	900 MHz
NPU frequency	1000 MHz	800 MHz	500 MHz
ISI frequency	667 MHz	500 MHz	333 MHz
GPU frequency	500 MHz	500 MHz	500 MHz
Display frequency	800 MHz	666 MHz	400 MHz
VPU frequency	666 MHz	500 MHz	333 MHz

To achieve the corresponding status in different modes, three actions needed to be taken

Change SoC driving mode in system manager
Set ddr rate in OEI image
Compile bootloader in mkimage

1.1 Change the SoC driving mode in system manager

1. First, clone the repository to your local machine and build the m33_image.bin. Refer to the README.md file in the repository for detailed build instructions and additional information.

git clone https://github.com/nxp-imx/imx-sm.git
export TOOLS=~/tools  # toolchain download link here, export your own path:
make config=mx95evk cfg
make config=mx95evk all

2.Here are the code changes for ND mode and LD mode in system manager

ND:

Diff --git a/boards/mcimx95evk/sm/brd_sm.c b/boards/mcimx95evk/sm/brd_sm.c
--- a/boards/mcimx95evk/sm/brd_sm.c
+++ b/boards/mcimx95evk/sm/brd_sm.c
@@ -104,7 +104,7 @@
BRD_SM_REC_VLD_MASK)

/* Performance parameters */
-#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_ODV /* Target perf level */
+#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_NOM /* Target perf level */

diff --git a/devices/MIMX95/sm/dev_sm_perf.c b/devices/MIMX95/sm/dev_sm_perf.c
index 8aafdce9..26d6da11 100644
--- a/devices/MIMX95/sm/dev_sm_perf.c
+++ b/devices/MIMX95/sm/dev_sm_perf.c
@@ -2704,7 +2704,8 @@ static void DEV_SM_PerfCfgInit(void)
     else
     {
         /* All other devices support PRK, LOW, NOM, ODV setpoints */
-        s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM - 1U;
+        s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM - 2U;
     }

     /* Check for LPDDR4X */

LD:

diff --git a/boards/mcimx95evk/sm/brd_sm.c b/boards/mcimx95evk/sm/brd_sm.c
--- a/boards/mcimx95evk/sm/brd_sm.c
+++ b/boards/mcimx95evk/sm/brd_sm.c
@@ -104,7 +104,7 @@
BRD_SM_REC_VLD_MASK)

/* Performance parameters */
-#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_ODV /* Target perf level */
+#define BOARD_PERF_LEVEL DEV_SM_PERF_LVL_LOW /* Target perf level */

diff --git a/devices/MIMX95/sm/dev_sm_perf.c b/devices/MIMX95/sm/dev_sm_perf.c
index 8aafdce9..26d6da11 100644
--- a/devices/MIMX95/sm/dev_sm_perf.c
+++ b/devices/MIMX95/sm/dev_sm_perf.c
@@ -2704,7 +2704,8 @@ static void DEV_SM_PerfCfgInit(void)
     else
     {
         /* All other devices support PRK, LOW, NOM, ODV setpoints */
-        s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM - 1U;
+        s_perfNumLevels[PS_VDD_ARM] = DEV_SM_NUM_PERF_LVL_ARM - 3U;
     }

     /* Check for LPDDR4X */

Compile the SM binary to generate build/mx95lp5/ddr/m33_image.bin, then copy it to imx-mkimage/iMX95/m33_image.bin.

1.2. Change the SoC driving mode in system manager

1.First, clone the repository to your local machine and build the m33-oei-ddr.bin. Refer to the README.md file in the repository for detailed build instructions and additional information.

git clone https://github.com/nxp-imx/imx-oei.git
export TOOLS=~/tools
make board=mx95lp5 oei=ddr DEBUG=1 r=B0

2. Please replace the a/boards/mx95lp5/ddr/ cMIMX95_LPDDR5_EVK_19X19_6400MTS_FW2024.09_timing.c file with a file corresponding to a different DDR data rate.

For ND mode, the file is lpddr5_4800_timing.c (See in attachment)

For LD mode, the file is lpddr5_3200_timing.c (See in attachment)

Compile the OEI binary to generate build/mx95lp5/ddr/m33_image.bin, then copy it to imx-mkimage/iMX95/m33_image.bin.

1.3. Compile bootloader in mkimage

1.Setup the imx-mkimage

mkdir imx-mkimage
cd imx-mkimage/
git clone https://github.com/nxp-imx/imx-mkimage.git
git checkout <branch_name>

2. Compile flash.bin

Refer to UG10163, section 4.5.13, to compile the files required by mkimage. Copy all the generated files to the imx-mkimage/iMX95 directory. Replace oei-m33-ddr.bin and m33_image.bin, then run the following command to generate flash.bin:

make SOC=iMX95 OEI=YES flash_all

The table describes the corresponding binaries:

	OEI image	System manager (M33_image)
OverDrive Mode	Oei-m33-ddr-6400.bin	M33_image_OD.bin
Nominal Mode	Oei-m33-ddr-4800.bin	M33_image_ND.bin
LowDrive Mode	Oei-m33-ddr-3200.bin	M33_image_LD.bin

3 .Flash the different flash.bin file to board with following command:

./uuu.exe –b emmc flash.bin

4. Open the BCU tool to check the VDD_SOC and VDD_ARM voltages. Then run the mhz command, and you will see that the current CPU frequency is being limited.