i.MX RT1170 crossover MCUs are part of the Edge Verse™ platform and are setting speed records at 1 GHz. This ground-breaking family combines superior computing power and multiple media capabilities with ease-of-use and real-time functionality. For reducing the overall system cost, RT117x didn't have embeded flash, need external Flash as program storage and XIP place, NXP and third party like IAR, KEIL and Segger all provide mature tool to make Nor Flash‘s programing with their own flashloader, can fulfillment most customer’s application requirement, but still some users need to customize the flash programing algorithm due to programing speed optimization and difference of the nor Flash from different vendor and, such as SFDP support, QE bit's position, default sector size, DDR/OPI/QPI feature, default 3 Bytes/4 Bytes mode and also operating sequence, but the default Flashloader is based on the ROM API, it's hard to debug and customize as there is no source code. This reference demo will use source code Flash operation API instead of ROM API. In addition, it also add two new useful feature, first one is current Flashloader framework can't support some nor flash which need pre-configuration, such as Cypress's S25HL01GT, its sector size is not unified, need to config additionally. This reference demo give some function interface to implement it with 3 bytes/4bytes command mode and DDR/SDR mode, it also improve the original framework by adding read-erase-write demonstration code, which can help user to verify their customized Flashloader without need to copy to IDE every time, improve the efficiency greatly. Second advantage is it can support download flow‘s log generation, by default there is no log info in overall download flow, hard to locate which step(get configure/init/erase/program/verify) the failure occur, this demo code add log function to record every detailed download step, by which users can optimize their download speed, it's helpful for mass production. Developers can also debug and customize depend on their own specific requirement and different nor Flash.

结合MPC5748G的Lifecycle机制，阐述如何使用Lifecycle机制来满足在开发阶段及最终消费阶段对各利益相关方的数据进行保护的需求，比如Tier1的IP(知识产权)、OEM的一些标定参数、车主的个人隐私等。并介绍Lifecycle在每个阶段所支持的主要安全特性及如何配置使用。

EEPROM selection guide for serial RCON boot. On S32G reference manual, we only ask customer to make sure I2C address of EEPROM is 0xA0, no others requirement. Actually, S32G only supports EEPROM with one 8-bit address byte. For high capacity EEPROM such as AT24C64D@8K bytes, which need two 8-bit word address bytes. Can’t be supported by S32G ROM.   AT24C64D.pdf         AT24C01 has been validated on S32G EVK board, which need one word address byte AT24C01.pdf   Thanks, Lambert

This document introduce how to do LPDDR4 DQ Swapping in S32G platform.

FAST BOOT FOR lx2160 IN adas •Objective To speed ​​​​up bringup of LX2 chip-based systems •Pain Points to Address The bringup time is much longer than 3s, which is very sensitive in ADAS systems or time-sensitive systems. •Value Proposition / Key Features The guide can help customers shorten uboot time from 5s to less than 1.5s, saving more than 70% bootup time. •Deliverables Demo based on LX2160ARDB board. Reference codes and patches. Guide for Fast boot document. Fast boot 广泛用于嵌入式设备，现以lx2160ardb板为例进行相关探索。 启动流程： 优化思路： 1.适当提高FSPI时钟速率 diff --git a/lx2160asi/flexspi_divisor_32.rcw b/lx2160asi/flexspi_divisor_32.rcw index 422139c..0f8d5c9 100644 --- a/lx2160asi/flexspi_divisor_32.rcw +++ b/lx2160asi/flexspi_divisor_32.rcw @@ -7,8 +7,10 @@ * Modify FlexSPICR1 register, to increase FlexSPI clock closer to 50MHz, * with divisor value as 32. * => 750 * 2 / 32 ==> 46.875MHz + *write 0x1e00900,0x00000013 + * 0f -12 =125M */ .pbi -write 0x1e00900,0x00000013 +write 0x1e00900,0x0f .end ​ 2.关键路径优化 固化spd参数 固化ddrc参数 BL33 裁剪 详细patch和测试结果参考附件。

  本文说明S32G  RDB2板Linux板级开发包BSP32 的ATF细节，以帮助客户了解S32G的ATF是如何运行的，以及如何修改到客户的新板上。   从BSP32开始，默认启动需要ATF支持，所以部分定制需要移动到ATF中，Uboot会简单很多。 请注意本文为培训和辅助文档，本文不是官方文档的替代，请一切以官方文档为准。   目录如下： 目录 1    S32G Linux文档说明... 2 2    创建S32G RDB2 Linux板级开发包编译环境... 3 2.1  创建yocto编译环境: 3 2.2  独立编译... 8 3    NXP ATF 原理... 13 3.1  AArch64 Exception Leve: 13 3.2  ATF原理... 14 3.3  ATF目录 结构... 16 3.4  ATF初始化流程... 25 3.5  NXP ATF的SCMI支持... 28 3.6  NXP ATF的PSCI支持... 32 3.7  NXP ATF OPTEE接口（未来增加）... 36 4    ATF 定制... 36 4.1  修改 DDR配置... 36 4.2  修改调试串口与IOMUX定制说明... 39 4.3  启动eMMC定制说明... 48 4.4  I2C与PMIC定制说明... 58

本文说明在S32G2 RDB2板上实现LLCE to PFE Demo的搭建过程。本Demo目前包括：  CANtoEth：CAN0发送，用硬件回环到 CAN1接收，然后通过PFE_EMAC1， 再通过RGMII接口发出。  CANtoEth：CAN0发送，用硬件回环到 CAN1接收，然后通过PFE_EMAC1， 再通过SGMII接口发出。  EthtoCAN：PC通过PFE_EMAC1的 RGMII发出，接收到CAN1，再硬件 回环到CAN0  CANtoCAN Logging to Eth: CAN0发 送，用硬件回环到CAN1接收，然后 通过PFE_EMAC1，再通过SGMII接 口发出,同时LLCE内部硬件把CAN1 再发送到CAN15_TX，再用硬件回环 到CAN14_RX 软件版本为 RTD3.0.0+LLCE1.0.3+PFE0.9.6/0.9.5。

This doc explain how to support a new QSPI nor for boot, SDK and Linux, Contents as follows: 目录 1 硬件设计 .................................................................... 2 2 所需工具和相关资料 .................................................. 5 3 ROM Code的启动流程 ............................................... 5 4 S32G QSPI NOR flash配置表头定制 ......................... 7 4.1 S32G QSPI NOR启动配置表信息 .......................... 7 4.2 目前支持的配置表头分析说明 ............................... 10 4.3 LUT构成与Flash write Data说明 ........................... 16 4.4 具体分析已有的配置表头的LUT与Flash write Data的 配置方法 ...................................................................... 22 4.5 支持一款新的QSPI NOR Flash示例1:Micron........ 28 4.6 支持一款新的QSPI NOR Flash示例2:Winbond .... 31 5 使用IVT打包配置头 .................................................. 33 6 使用IVT工具中的flash image工具烧写镜像到QSPI NOR 中 34 7 软件定制M7 ............................................................. 35 8 软件定制uboot ......................................................... 37 9 软件定制Linux Kernel .............................................. 40 9.1 支持美光8bit DDR 模式(未验证) .......................... 44 9.2 支持1bit SDR fast read 模式 ............................... 46 10 Debug过程中需要注意的几点 .................................. 49 10.1 启动时ROM Code读取QSPI NOR时钟仅有12Mhz左 右 49 10.2 比较大的镜像如果不加参数头，无法从QSPI-NOR上启 动 55   add a new doc for lauterbach driver: S32G How to Develop the QSPI-Nor Lauterbach Script 目录 1    背景和参考资料... 2 1.1  背景说明... 2 1.2  参考资料... 2 2    高速读开发流程... 3 2.1  时钟相关修改... 5 2.2  Lut配置说明... 6 2.3  QSPI NOR控制器配置... 12 2.4  QuadSPI_Write32BytesDOPI读函数分析... 15 2.5  增加AHB read寄存器配置... 17 2.6  测试结果... 18 3    高速写开发流程... 19 3.1  Erase lut分析及调用... 19 3.2  Write lut分析及调用... 21 3.3  测试结果... 22 3.4  Lauterbach烧写镜像脚本说明... 22

目录 1 S32G Linux文档说明 .................................................. 3 2 创建S32G RDB2 Linux板级开发包编译环境 .............. 4 2.1 创建yocto编译环境: ................................................. 4 2.2 独立编译 ................................................................. 9 3 FSL Uboot 定制 ........................................................ 14 3.1 FDT支持 ............................................................... 14 3.2 DM(driver model)支持 ........................................... 20 3.3 Uboot目录结构 ...................................................... 31 3.4 Uboot编译 ............................................................. 34 3.5 Uboot初始化流程 .................................................. 35 3.6 使能了ATF后对Uboot初始化流程的影响 ............... 40 4 Uboot 定制 ............................................................... 41 4.1 修改 DDR大小 ....................................................... 41 4.2 修改调试串口与IOMUX说明 .................................. 44 4.3 DM I2C与PMIC初始化 .......................................... 53 4.4 通用GPIO ............................................................. 59 4.5 启动eMMC定制 ..................................................... 69 4.6 Ethernet定制 ......................................................... 78 5 Uboot debug信息 ..................................................... 89 5.1 Print env ............................................................... 89 5.2 dm - Driver model low level access ...................... 92 5.3 fdt .......................................................................... 95 5.4 I2C测试 ................................................................. 95 5.5 芯片寄存器访问 ..................................................... 98 updated to V5

This doc explain how to use S32G design studio and SDK, contributed by Gary.Yuan [email protected].

This doc explain how to configure a new LPDDR4 and test it on S32G, contents as follows: 目录 1    硬件资源，文档及工具下载... 2 1.1    硬件资源... 2 1.2    内存配置测试相关的文档... 2 1.3    内存配置与压力测试工具. 3 2    内存设计要求... 3 3    LPDDR4基础... 3 3.1    基本知识... 3 3.2    Inline ECC.. 4 4    硬件连接... 6 5    S32G+LPDDR4内存配置与测试步骤... 8 5.1    配置LPDDR4初始化寄存器设置... 9 5.2    使用内存测试工具初始化PHY及生成DDRC配置Uboot源代码    11 5.3    生成DDRC配置ATF源代码(从BSP32开始) 14 5.4    测试内存... 18 5.5    其它尺寸的LPDDR4配置... 19 6    测试失败的DEBUG.. 24 7    内存参数应用到Uboot中... 25 8    内存参数应用到ATF中... 25 9    附录... 25 9.1    一个重要的DDR TOOL bug Fix. 25 9.2    Uboot DDR测试工具... 26 9.3    Kernel DDR测试工具... 27 9.4    附DDR tool测试项截图... 28   Contents 1    Hardware Materials, Docs and Tools Needed. 2 1.1    Hardware resource. 2 1.2    Related docs of memory configuration and test 2 1.3    Memory configuration and test tools. 3 2    Memory Hardware Design Requirement 3 3    LPDDR4 Basics. 3 3.1    Basic Knowledge. 3 3.2    Inline ECC.. 5 4    Hardware Design. 7 5    S32G+LPDDR4 Memory Configuration and Test Steps. 8 5.1    Configure LPDDR4 DDRC Register Settings. 9 5.2    Use the Memory Test Tool to Initialize the PHY and Generate the DDRC Configuration Uboot Source Code  12 5.3    Generate ddrc configuration ATF source code (starting from bsp32) 15 5.4    Memory Test 19 5.5    Other size LPDDR4 configurations. 20 6    Debug of the Fails of Test 25 7    Modify the DDRC register settings in Uboot 26 8    Modify the DDRC register settings in ATF. 26 9    Appendix. 26 9.1    A importance DDR TOOL bug Fix. 26 9.2    Uboot DDR Test Tools. 27 9.3    Kernel DDR Test Tool 28 9.4    Attached Screenshot of DDR Tool Test Items. 29

This doc explain  where is the design resource and what they are of S32G in Chinese,  Contents as follows: 目录 1 www.nxp.com 官网资源 ............................................. 2 1.1 www.nxp.com Documentation ................................ 4 1.2 www.nxp.com Tools&Software ............................. 10 2 Flexera资源 ............................................................. 18 2.1 Automotive HW-S32G Evaluation Board .............. 21 2.2 Automotive HW-S32G GoldBox ........................... 22 2.3 Automotive HW-S32G RDB2(RDB不再说明) ....... 22 2.4 Automotive SW-S32G2 Standard Software.......... 23 2.5 Automotive SW-S32G2 reference Software ......... 28 2.6 Automotive SW-S32G2 Tools .............................. 30 3 Docstore资源 ........................................................... 31

功能需求 RT117X系列MCU在汽车和工业类产品中有广泛应用，有很多客户对LIN通讯有需求，RT1176有12路独立的LPUART接口，最大支持的波特率能支持到20M，而且每一路都支持Break发送和中断接收，可以用来配合定时器实现LIN的主机和从机通讯。但是目前RT117X的EVK板没有放置LIN的收发器，SDK也没有相关LIN的示例代码和LIN协议栈支持，所以本示例目的是移植KW36工程中的LIN 2.1版本的代码到RT1176 EVK板子上，在硬件上通过跳线将LIN Master主节点和 Slave从节点的LPUART TX/RX线连接到FRDM-KW36板载的LIN收发器TJA1027上，分别实现LIN 2.1版本协议栈在Master和Slave节点的通讯功能验证，同时还需支持Auto Baud Rate自动波特率调整。为客户做二次开发或者移植用户自己的LINstack提供底层驱动，提高开发效率。 代码包软件   RT1176 LIN Master节点代码：RT1170_LIN_Porting_Demo_Master.7z RT1176 LIN Slave节点代码(支持自动波特率😞 RT1170_LIN_Porting_Demo_Slave_with_Auto_Baud_Rate.7z 配置FRDM-KW36板载LIN 收发器的代码: KW36_LIN_PHY_Board_Init.7z 硬件Setup   MIMXRT1170-EVK： 2pcs，分别用作LIN Master节点和Slave节点。 FRDM-KW36：2pcs， 分别用作Master节点的收发器，和 Slave节点的收发器 下图是系统连接，2块RT1170 EVK板分别和2块FRDM-KW36板通过Arduino接口连接在一起，然后将两块KW36之间的LIN收发器通过 J13 连接在一起，需要使用外部12V adapter为FRDM-KW36供电，否则板上的LIN收发器无法工作。特别强调的是，如果需要使能自动波特率检测的话，还需要将Slave节点RT1176 Arduino接口的J9-Pin2引脚连接到RT1176 Arduino接口的J9-Pin12引脚，作为Timer 脉冲捕捉的输入，即可完成系统硬件的setup。   软件Setup：   在以上硬件连接完成后，按照如下步骤下载对应软件： - Step1: 下载KW36_LIN_PHY_Board_Init.7z代码到两块FRDM-KW36板子上；  该代码中主要实现两个功能：第1个拉高板子的PTC5引脚，唤醒LIN收发器TJA1027。第2个将PTA18引脚配置成disable高阻状态。如果该引脚作为GPIO输出或者LPUART TX功能，会导致LIN slave回应数据出错(bit位丢失或者错误)。究其原因猜测应该是短路导致，当这个引脚作为GPIO输出或者LPUART TX功能，内部会有上拉，当RX1176 TX引脚输出Low时，由于电路上没有串联电阻(板子上使用的0Ω)，会导致引脚上出现大电流。尤其是第2个点，花费了很多时间去查这个问题，从波形去看，是有数据输出的，但只是数据不对，很具有迷惑性。当然如果客户是自己打的板子，板子上已经有LIN收发器就不需要这一步，直接跳到Step2即可。 - Step2: 下载RT1170_LIN_Porting_Demo_Master.7z代码到作为Master节点的IMRT1176-EVK板； - Step3: 下载RT1170_LIN_Porting_Demo_Slave_with_Auto_Baud_Rate.7z代码到作为Slave节点的IMRT1176-EVK板，如果需要使能自动波特率调整，需要配置宏linUserConfigSlave.autobaudEnable = true; 代码中默认是打开的。 实验结果   打开两个IMRT1176-EVK板串口，波特率配置115200，单击RT1176 Master节点上的按键SW7，便可以启动Master节点开始发送数据，通讯波形和串口打印信息如下两张图所示。   代码移植的几个难点   1. LIN通讯协议栈的调度流程的理解，包括Wakeup段，Break段，Sync段，PID段，Data段的状态切换和跳转，每个段的超时监测和错误处理，其核心思想有两个：一个在于LIN的RX引脚要不断去monitor TX引脚的状态，然后去切换状态机，具体调度的流程在后文会详细介绍，这里不展开。第二个是准确获取在每个段的定时器时间，尤其是超时超过一个overflow周期的情况，需要对timerGetTimeIntervalCallback0函数有理解。 2. 自动波特率调整功能的支持，该功能的原理是测量SYNC段的8个脉冲的脉宽，如果每个脉宽差异在2%范围内，再根据脉冲宽度去判断对应的波特率。在原来KW36的代码中是使用TPM的Overflow中断来作为计时，Edge中断来触发，而RT1176没有TPM，只能使用Qtimer (Qtimer功能上要更强于TPM)，但是不巧的是Qtimer不支持Overflow中断(参见芯片ERRATA 050194)，所以只能使用compare中断来实现类似的功能，而原有的计时定时计算都是基于overflow的，因此就需要对定时器部分的代码做大范围的更改。 应用中考虑到timerGetTimeIntervalCallback0函数在自动波特率调整时和超时监测处理时的一致性，最好使用同一个Timer的同一个channel，这就需要这个Timer既支持普通的定时中断模式，又支持input capture功能。对于TPM来说，是无法实现的因为两次在寄存器配置上时互斥的, 参见下图。幸运的是Qtimer支持这个feature，只是需要根据SDK代码做些配置 前面提到，需要QTimer支持input capture功能, 触发信号是LPUART_RX引脚的信号，需要硬件loop到Qtimer支持的硬件引脚上，对于KW36来说，只需要把这两个物理引脚连接在一起即可，但对RT1176来说, 只有这一步还不行，还需要对XBAR进行配置，将Qtimer的TIMER 1的触发引脚(合计有4个物理引脚)Link到QTIMER对应的Channel上，因为RT1176有4个QTimer，每个Qtimer有4个通道，标称的Qtimer trigger pin有4个，那具体哪个pin触发哪个QTimer的哪个通道，是需要配置的。如果客户没有使用过XBAR配置起来有难度，还好MCUXpresso config tool支持配置，可以简便的完成配置。示例代码和触发关系如下，如果实际硬件使用的物理引脚有区别，需要对应修改。 RT的XBAR功能非常强大，或许可以不使用外部的物理连线，直接将Qtimer的出发引脚的信号直接在内部Loop到LPUART_RX引脚，这样就更加灵活，此处只提供一个思路，不再进一步延伸。 IOMUXC_GPR->GPR15 = ((IOMUXC_GPR->GPR15 & (~(IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)))/*Mask bits to zero which are setting*/ | IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(0x00U) /*QTIMER4 TMR1 input select: 0x00U*/ | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(0x00U) /*QTIMER4 TMR2 input select: 0x00U*/ ); 4. 在状态机切换和超时以及错误处理过程中，经常会看到两种模式Sleep模式和Idle模式，区别是什么呢？ LIN_LPUART_GoToSleepMode: 函数会关闭Break中断，RX接收中断，帧错误中断，保留RX边沿 中断; LIN_LPUART_GotoIdleState 函数会打开Break中断，RX接收中断，帧错误中断，关闭RX边沿中 断; 实际通讯波形   Master作为Subscribe角色时，发送Header，由Slave发送Respone Master作为PUBLIC角色时，同时发送Header，以及Respone 按照调度表依次发送LI0_lin_configuration_RAM数组定义的PID数据 static uint8_t LI0_lin_configuration_RAM[LI0_LIN_SIZE_OF_CFG]= {0x00, 0x30, 0x33, 0x36, 0x2D, 0x3C, 0x3D ,0xFF}; Qtimer准确读取wake up信号的脉冲宽度 Slave使能Auto baud rate后读取到的每个脉冲宽度数据 免责声明： THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND *ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, *INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUTNOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, ORPROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY,WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE)

Introduction Background There is not an official data for PCIe latency and performance, while some customers pay attention to and request these data. This paper utilizes Lmbench lat_mem_rd tool and DPDK qdma_demo to test the PCIe latency and performance separately. Requirement 1) Plug Advantech iNIC (LX2160A) into LX2160ARDB. 2) Configure EP ATU outbound window at console. 3) Apply the patch to lmbench-3.0-a9, and recompile lmbench tool. 4) There is qdma_demo in iNIC kernel rootfs by default. Test Environment     PCIe Latency Overview   Direction Description Latency(ns) PCIe(Gen3 x8) – DDR read from EP to RC 900 PCIe – PCIe – DDR Read from EP to EP (through CCN-508) 1550 PCIe – PCIe – DDR Read from EP to EP (through HSIO NOC) 1500 Setup 1) LX2160ARDB 2) iNIC – PCIe EP Gen3 x8 with LX2160A 3) Test App running at iNIC: Lmbench lat_mem_rd   # ./lat_mem_rd_pcie -P 1 -t 1m   PCIe Performance Overview    Direction Throughput (Gbps) PCIe EP to EP 50   Setup 1) LX2160ARDB 2) iNIC – PCIe EP Gen3 x8 with LX2160A 3) Test App : qdma_demo running at iNIC   $./qdma_demo -c 0x8001 -- --pci_addr=0x924fa00000 --packet_size=1024 --test_case=mem_to_pci Peer to Peer On LX2 Rev. 2      Products   Product Category NXP Part Number URL MPU LX2160A https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A LSDK software Layerscape Software Development Kit https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/layerscape-software-development-kit:LAYERSCAPE-SDK   Tools    NXP Development Board URL LX2160ARDB https://www.nxp.com/design/qoriq-developer-resources/layerscape-lx2160a-reference-design-board:LX2160A-RDB Advantech ESP2120 Card      

        S32G just support serial download a M7 image to run by internal rom codes, our S32G DS IDE have a flash tools to use this feature to burn the image to external device. So current image burn method will divide into 2 step: 1: burn a uboot into the external device by S32G DS flash tools. 2: reboot the codes with uboot and run with network to burn the linux image into external device.      which need two working place on manufacture line, and customer wish to have a one time on-line tools, which means we need use serial port to boot uboot directly but S32G rom codes do not support it.       We have a reference tools of S32V but which IP difference is big between on S32V and S32G, So we can not reuse it and have to develop a new one.       The development working include: 序号 开发工作 说明 开发者 1 开发 根据S32G的serial boot协议要求，开发PC端的串口工具来下载M7镜像 John.Li 2 开发 根据自定义协议要求，开发PC端的串口工具来下载A核Bootloader到SRAM中 John.Li 3 开发 根据自定义协议要求，开发M7镜像的串口接收与Checksum逻辑 John.Li 4 开发 修改M7镜像支持串口0 John.Li 5 开发 开发实现M7镜像的串口单字节同步收发函数 John.Li 6 开发 开发实现A53启动功能 John.Li 7 调试与Debug 调试解决串口接收乱码问题(Serial boot rom codes仍然在回送消息串口) John.Li 8 调试与Debug 提供 解决A核启动串口halt思路(Serial boot rom codes仍然占用串口) John.Li 9 调试与Debug 优化M7镜像，缩小大小 Tony.Zhang 10 调试与Debug 根据M7镜像和A核 Uboot在SRAM中的内存分配要求，重排M7镜像位置，避免冲突 Tony.Zhang 11 调试与Debug 在M7中初始化SRAM空间 Tony.Zhang 12 调试与Debug 在M7中设置SRAM可执行空间 Tony.Zhang 13 调试与Debug 调试解决由于cache没有及时回写导致的下载镜像错误的问题 Tony.Zhang 14 调试与Debug 集成，调优与文档 John.Li   Pls check the attachment for the doc/codes/binary release which include:    Release      |->M7: Linflexd_Uart_Ip_Example_S32G274A_M7: S32DS M7工程。      |->PC: s32gSerialBoot_Csharp: PC端的Visual Studio的C#的串口工具工程。      |->Test:      |    |-> 115200_bootloader.bin: S32DS M7工程编译出来的bin文件，波特率为115200      |    |-> 921600_bootloader.bin: S32DS M7工程编译出来的bin文件，波特率为921600      |    |->load_uboot.bat: 运行工具的批处理文件，运行成功后打开串口可以看到Uboot执行，默认使用的波特率是115299         |    |->readme.txt:其它测试命令 |    |->s32gSerialBoot.exe:编译出来的PC端串口工具 |    |->u-boot.bin: BSP29默认编译出来的u-boot.bin.      Product Category NXP Part Number URL Auto MPU     S32G274     https://www.nxp.com/s32g    

引言 FRDM-KW36包含带有32 kHz晶体振荡器的RTC模块。此模块为以极低功耗模式运行的MCU生成32 kHz时钟源。该振荡器包括一组用作CLOAD的可编程电容器。改变这些电容器的值可以改变振荡器提供的频率。 此可配置电容的范围为0 pF（禁用电容器组）至30 pF，步长为2 pF。 这些值是通过组合启用的电容器获得的。可用值为2 pF，4 pF，8 pF和16 pF。可以完成这四个数值的任意组合。如果可以使用外部电容器，建议禁用这些内部电容器（清除RTC控制寄存器SFR中的SC2P，SC4P，SCS8和SC16位）。 要调整振荡器提供的频率，必须首先能够测量该频率。使用频率计数器将是非常好的，因为它提供了比示波器更精确的测量。您还需要输出振荡器频率。要输出振荡器频率，以任意一个蓝牙演示应用程序为例，您应该执行以下操作： 调整频率示例 本示例将利用Connectivity Software Stack中的心率传感器演示（freertos版本），并假定开发人员具有从SDK到IDE导入或打开项目的知识。 1.从SDK中打开或克隆“心率传感器”项目。 2.在工作区的board文件夹中找到board.c和board.h文件。 3.如下图所示在board.h文件中声明一个void函数。该函数将RTC管脚复用设置为输出到PTB3并能够测量频率。 4. 如下所示在board.c文件中开发BOARD_EnableRtcClkOut函数。 5. 代码如下： 6. 在BOARD_BootClockRUN（board.c文件）之后立即在hardware_init函数中调用BOARD_EnableRtcClkOut函数。 7. 在工作区的board文件夹中找到clock_config.c文件。 8. 在文件顶部添加以下定义。 9. 在BOARD_BootClockRUN函数内部（也在clock_config.c文件中）搜索对函数的CLOCK_CONFIG_EnableRtcOsc调用，然后通过上述任意定义来编辑变量。 10. 最后，在项目源文件夹中的“ preinclude.h”文件中禁用低功耗选项和LED支持： 此时，您可以在PTB3中进行测量，并使用频率计数器进行频率调整。每次对电路板进行编程时，都需要执行POR以获得正确的测量。下表是从FRDM-KW36板版本B获得的，可用作调整频率的参考。 请注意，电容不仅由启用的内部电容组成，还包括封装，内部走线，芯片焊盘和PCB走线中的寄生电容。因此，尽管下面给出的参考测量值应接近实际值，但您还应该在电路板上进行测量，以确保频率是专门针对您的电路板和布局进行调整的。 Labels：KW   KW35 | 36 kinetis kw36a

这篇文章通过覆盖与GFSK （通用频移键控）通信并行的 低功耗蓝牙 多节点连接，提供了混 合应用程序（ W ireless UART + GFSK Advertising ）的示例。这是 SDK 的另一个示例，其中我 们定义了 混合应用程序，用于与 GFSK 通信并行进行蓝牙 LE 广告和扫描。 Products Product Category NXP Part Number URL MCU KW36/35/34 https://www.nxp.com/products/wireless/bluetooth-low-energy/kw36-35-34-arm-cortex-m0-pluskinetis-kw36-35-34-bluetooth-low-energy-32-bit-mcus-nxp:KW36-35 MCU KW39/38/37 https://www.nxp.com/products/wireless/bluetooth-low-energy/kw39-38-37-32-bit-bluetooth-5-0-long-range-mcus-with-can-fd-and-lin-bus-options-arm-cortex-m0-plus-core:KW39-38-37   Tools NXP Development Board URL FRDM-KW36 Freedom Development Kit https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/frdm-kw36-freedom-development-kit-for-kinetis-kw36-35-34-mcus:FRDM-KW36 FRDM-KW38 Freedom Development Kit https://www.nxp.com/design/designs/freedom-development-kit-for-kw39-38-37-mcus:FRDM-KW38   SDK SDK Version URL MCUXpresso SDK Builder https://mcuxpresso.nxp.com/en/welcome

Overview The S12ZVH-REF-V1 is a reference design engineered for being a design base for starting an instrument cluster project, also it helps to reducing Automotive Cluster development time and maximizing engineering resources. Based on the 16-bit S12 MagniV® S12ZVH mixed-signal microcontrollers, the S12ZVH-REF-V1 provides a production-looking design with impressive integration. The S12ZVH-REF-V1 reference design is not only provided as a hardware reference but also as a software and mechanical design. Block Diagram   Products Product Features S12ZVH MagniV Mixed-signal MCU  16-bit S12 MagniV® S12ZVH mixed-signal microcontrollers for instrument cluster.   Features Interfaces   LIN physical transceiver and connector CAN connector interfaced with MCUs CAN physical transceiver Components 1 x custom 160 segment LCD 1 x low-power piezoelectric speaker 4 x stepper motors 49 x LEDs used as telltales and backlights 6 x user buttons 2 x potentiometers S12ZVH The S12ZVH-REF-V1 does not include on-board programming/debugging circuitry; it requires an external programmer compatible with the BDM protocol. Files S12ZVH-REF-V1 Mechanical and Assembly files  S12ZVH-REF-V1 Reference Design Software (CW10.5) 

Overview   The RDS12VR is a solution engineered for window lift, power windows, and sun roof systems. Developed in partnership with Tongji University and based on the 16-bit S12 MagniV® S12VR mixed-signal microcontrollers, the RDS12VR offers control by multiple LIN salve nodes or LIN master node, through the easy-to-control Graphics User Interface (GUI). The RDS12VR reduces unnecessary external components, lowers the total bill of material (BoM), improves system quality, and saves space in automotive applications through a smaller PCB. The RDS12VR solution includes hardware for real door/window in-vehicle applications, as well as software including anti-pinch algorithms and low-level S12VR drivers for reducing time to market. Block Diagram   Products Product Features S12VR  16-bit S12 MagniV® S12VR mixed-signal microcontrollers, efficient and scalable relay driven DC motor control solution   Features Features   Window manual/automatic up/down, automatic up/down with stop function Anti-pinch in both manual/automatic mode, anti-pinch region and force can be adjusted Stuck detection out of anti-pinch region, motor overload protection Soft stop when window is close to the top/bottom Self learning, calibration by updating the window/motor parameters stored in EEPROM Use hall sensor as well as current sense to judge anti-pinch in algorithm Power   Fault diagnosis, indicating low voltage, over voltage/current/temperature etc. Low power mode (leveraging S12VR low power mode) to reduce power consumption GUI Easy-to-control GUI, set the parameters and get the status Window lift can be controlled either by multiple LIN salve nodes or LIN master node, through GUI Functional Safety Able to comply with relevant content in US Federal Motor Vehicle Safety FMVSS No. 118 standard Document DRM160, Window Lift and Relay Based DC Motor Control Reference Design Using the S12VR Microcontrollers     

  Overview NXP solutions enable AD/DC chargers in hybrid electric vehicles (HEV). The AD/DC charger interfaces with the battery management system to ensure a proper charge of electricity of the cells until it fulfills high-voltage (HV) requirements. Our comprehensive portfolio provides the critical building blocks for high-performance, efficient and safe pawer management control system for electric traction motors.   Use Cases This solution can be applied and various sectors of the industry, specially in the automotive field. NXP solutions enable Hybrid and Electric Vehicles applications as: Converters and Chargers Stop/Start Systems Power inverters   Block Diagram Products Category MCU Product URL S32K144EVB: S32K144 Evaluation Board  Product Description The S32K144EVB is a low-cost evaluation and development board for general purpose automotive applications.   Category Safety SBC Product URL 1 FS6500: Grade 1 and Grade 0 Safety Power System Basis Chip with CAN Flexible Data Transceiver  Product Description The NXP® FS6500 system basis chip (SBC) provides power to MCUs and optimizes energy consumption through DC/DC switching regulators, linear regulators, and ultra-low-power saving modes.   Category RTC Product URL PCA85073A: Automotive tiny Real-Time Clock/Calendar with alarm function and I2C-bus  Product Description The PCA85073A is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption.   Category Serial Interface Product URL  MC33660: ISO K Line Serial Link Interface  Product Description The NXP® MC33660 is a serial link bus interface device designed to provide bi-directional half-duplex communication interfacing in automotive diagnostic applications.