PN5190-NTAG X DNA High Speed Communication Demo: This article describes important feature of these two chips when interacting with each other at contactless interface: Passthrough demonstrator at high bit rates for ISO/IEC14443-A between PN5190 and NTAG X DNA Scope of demonstrator: ▪ Demonstrating a unique feature of NXP Semiconductors. High bit rates for ISO14443 communication (up to 848 kbps) between a PN5190 reader IC and an NTAG X DNA when connected to MCXA153 host MCU, when simulating the transmission of a dummy file as big as 101 kbytes. ▪ Through MCUXpresso console, the user can configure the contactless bit rate: 106 kbps 212 kbps 424 kbps or 848 kbps The amount of data is fixed in this demo. ▪ transmission mode is implemented from NFC reader library at K82 MCU built in the PNEV5190BP evaluation kit. On the other side, NTAG X DNA + Level shifter (represented by evaluation kit NTAG-X-DNA-EVAL) is connected to a Freedom Board, equipped with MCXA153 - FRDM-MCXA153). ▪ The PN5190 prints on the MCUXpresso console (debug mode) the outcome of the transaction and average baud rate achieved. ▪ In order to handle full file transmission from K82 to MCXA153 (MCU <-> MCU communication), we are using NTAG X DNA GPIO wires as well as proper settings on the NTAG X DNA <-> MCXA153 side and hard coded timeout on the PN5190 + MCU side. For more details, please open attached file PN5190_NTAGXDNA_MCXA153_DualInterface_HBR_Demo_SetupInstructions_Q32025.pdf. Required hardware and software enablement: Hardware ▪ PNEV5190BP Development Board ▪ FRDM-MCXA153 Development Board ▪ NTAG X DNA Development Board ▪ 2 x USB micro cables (for PNEV5190BP dev. br., one for DC power, other for Jlink debug on MCUxpresso IDE) ▪ 1 x USB-C cable (for FRDM-MCXA153 dev. br., only for DC power) Software ▪ MCUxpresso project (firmware Source Code) for PNEV5190BP is attached to this article, containing keywork pn5190: pn5190-ntagxdna-highspeed-demo1.zip. Instructions will be given in from future release of NFC Reader Library public v07.14.00 (NxpNfcRdLib_PN5190_v07.14.00_Pub.zip). ▪ SDK_2.x_FRDM-K82F is already included in bundle mentioned above. ▪ Firmware Source Code for FRDM-MCXA153 is attached to this article, containing keyword MCXA153: MCXA153.zip ▪ MCUXpresso IDE recent version, for instance v24.12.148 or above. Demonstrator bring up: Hardware assembly for FRDM-MCXA153: • Connect NTAG X DNA to level shifter (see Fig. 1) • Connect bundle NTAG X DNA+ level shifter bundle to flat cable (contained in demokit box) to FRDM-MCXA153 according to Fig. 2. • Make sure each wire is connected to proper position in Arduino socket: - black wire IO2 goes to J1-14 - white wire IO1 goes to J1-16 - gray wire SCL goes to J2-20 - violet wire SDA goes to J2-18 - blue wire GND goes to J3-14 - green wire VCC goes to J3-8 • Connect FRDM-MCXA153 via J15 (MCU-Link) to your computer (Debug Link Input), for the first time that you have to flash binary in it. Then after storing binary, you may just connect USB-C cable from a power supply to J6 port (named Ext-debugger). • No additional power source is needed. Hardware assembly for PNEV5190B: • Connect two USB micro cables to PNEV5190B board for power, flashing firmware and UART connection (see Fig. 3): • microUSB on J7 is necessary for DC power. Check that jumper J9 is in the position USB dc supply • microUSB on J20 is the Jlink debug port, and it will be connected to your Windows computer, where MCUxpresso has been installed. • Red LED indicates power is enabled • Green LED debugging/UART status Alternatively, if you have a DC power supply (voltage above 7 V), you may change Jumper J9 to Ext power supply, and avoid using second microUSB cable. Software loading on FRDM-MCXA153: 1. Create a new workspace for MCXA153 MCUxpresso example: 2. Make sure you have installed MCXA153 SDK: - install MCXA153 SDK which can be downloaded from: https://mcuxpresso.nxp.com/  3. Unzip "MCXA153.zip" file in local C: directory, with reasonable path length. 4. Import existing projects from file system, into MCUXpresso IDE: 5. Select proper root directory (keyword is MCXA153): 6. Click "Finish" 7. If you get this warning, simply click "OK": 8. Highlight project, click "build", and check that there are no errors: Finished building target: MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf Performing post-build steps arm-none-eabi-size "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf"; # arm-none-eabi-objcopy -v -O binary "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf" "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin" ; # checksum -p MCXA153 -d "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin";    text        data         bss         dec         hex     filename   23524          20        3684       27228        6a5c      MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf 16:27:26 Build Finished. 0 errors, 0 warnings. (took 5s.787ms) 9. Now, flash the binary into MCXA153 MCU using GUI Flash tool; select suitable  MCUxpresso probe (CMSIS-DAP). Make sure USB-c cable is connected to J15 in Freedom board (MCU-link port for flashing FW). 10. Select binary file *.axf as indicated below: It may happen that your MCXA153 has outdated FW on CMSIS-DAP, but you can continue, it will make no harm; click then Ok to flash. 11. After flashing, reboot your board. Following LEDs should be on: - D15 RGB led should be "white" lit. - D7 should be blinking "red" - D8 and D4 should be "green" lit. D15 will blink "white" only during file transmission. You may disconnect USB-c from J15 (the one used with MCUxpresso for flah and connect it to J8. Then, plug the other cable tip to any USB  5 volt battery charger. Now your Freedom board FRDM-MCXA153 is ready to receive data from PNEV5190 board, once project will be imported too in MCUxpresso. Software loading on PNEV5190BP: 1. Unzip *.zip file in directory with reasonable path length. 2. Import existing projects from file system 3. Select Example 12 "NfcrdlibEx12_NTAGXDNA" 4. Uncheck the choice "copy projects into workspace" 5. Install SDK_2.x_FRDM-K82F if not yet done. Such SDK is included in project file tree: • ...Examples\Platform\SDK_2.x_FRDM-K82F • This specific SDK can be obtained from https://mcuxpresso.nxp.com/ by selecting following K82F tab related "PN5180" : • FRDM-K82F-PN5180 (MK82FN256xxx15) • SDK 2.0 is no longer officially available, but SDK 2.2 and newer are backward compatible and recommended by NXP • Build project and check that there are no errors ("warnings" are allowed). • Start Debug session to see available bitrate options on the console. Hardware combination of PNEV5190B and NTAG X DNA connected to FRDM-MCXA153: Under MCUXpresso: 1. Click "Debug" icon on quick access left panel. Accept agreement in case of J-Link tool: 2. Click on icon "Run" on top side of MCUxpresso, and observe the following on "Console" tab: [MCUXpresso Semihosting Telnet console for 'NfcrdlibEx12_NTAGXDNA_mcux JLink DebugFRDMK82F' started on port 59973 @ 127.0.0.1] SEGGER J-Link GDB Server V8.12a - Terminal output channel *** NTAG X DNA Example *** Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : Menu options when two boards have NFC antennas facing each other: There are 5 options in console menu as soon as you "Run" the debug. 1 - options from 1 until and including 3 are related to crypto functionality (symmetric and asymmetric) and are out of the scope of this article. 2 - Then option 5 is used for the first time that you are configuring your NTAG X DNA product. It will set registers and GPIO properly for High bit rate transfer. Once you have run option 5, then go to option 4: 3 - Four options of bitrate are available for transfer a fixed amount of data from host (K82) to NTAG X DNA MCU (MCXA153) using PN5190 as tunnel: Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : Demonstration flow: Once one of these option is selected, reader is ready to detect a tag. ▪ When tag is detected, reader configures selected bitrate and starts data exchange. ▪ Blinking RGB LED D15 indicates transfer ongoing and the console shows a progress. Here are some results of transaction at the different bit rates and data sizes offered by this demonstrator: 1 - 106 Kbps - Baud rate 7.6 kBytes/s - elapsed time: 13.99 s Type A Tag is discovered. ***** Perform Transfer sequence ******* Select Application Successful Select File Successful Data transferring NFC -> NTAG X DNA -> Microcontroller... Amount of data exchanged 101200 Bytes, Baudrate (total) = 7.6 kB/s, Time = 13.99 s Please Remove the Card   After removing the card, K82 firmware starts again prompting for a new selection, in the previous menu. First select 4 again and then chose again another new baud rate: 2 - 212 Kbps - Baud rate 10.51 kBytes/s - elapsed time: 9.39 s 3 - 424 Kbps - Baud rate 13.92 kBytes/s - elapsed time: 7.90 s 4 - 848 Kbps - Baud rate 16.60 kBytes/s - elapse time: 5.95 s   Using Example 12 of NFC Reader Library v.07.14.00 to prepare High Speed demo on PNEV5190BP and NTAG X DNA: 1. Go to https://nxp.com web site and type "NFC Reader Library" in Search tab. Follow the instructions until you get to this screenshot: 2. Start by downloading NFC Reader library V.07.14.00 from NXP website; agree with Terms and Conditions. Then download the bundle to your local C: drive: 3. Click on “down arrow” to download version 07.14.00. Once zip file is received, unzip previous bundle to a local drive directory.   4. Start a new workspace, then choose "Import from Existing Projects into Workspace": 5. De-select all useless Examples and keep only example 12; please including all other essential items; click "Finish": 6. If you find this error, it means you need to install K82F SDK: 7. Click install, then MCUxpresso SDKs pages will open. Select K82F from Processor tab: Click “Install” button; after installation is completed, you will get a screen showing all installed sdk's. Afterwards you may get the prompt "Make SDK persistent"; just click ok. 8. Highlight project NfcrdlibEx12_NTAGXDNA_mcux and click build; check if there are errors: Finished building target: NfcrdlibEx12_NTAGXDNA_mcux.axf Performing post-build steps arm-none-eabi-size "NfcrdlibEx12_NTAGXDNA_mcux.axf" ; arm-none-eabi-objcopy -O binary "NfcrdlibEx12_NTAGXDNA_mcux.axf" "NfcrdlibEx12_NTAGXDNA_mcux.bin" ; #checksum -p MK82FN256xxx15 -d "NfcrdlibEx12_NTAGXDNA_mcux.bin"    text        data         bss         dec         hex     filename  222400          92       86816     309308       4b83c      NfcrdlibEx12_NTAGXDNA_mcux.axf 17:32:59 Build Finished. 0 errors, 3 warnings. (took 33s.718ms) 9. Now, check in MCUxpresso the tab Windows > Preferences > Run/Debug. Untick the box related to General Options Build (if required) before launching; it will save you much time! Then, click button “Apply and Close”. 10. Using this Example 12 as it is given by NXP in this library, when you will debug it, you will realize that there are only 3 Menu options related to NTAG X DNA cryptography (and no high speed options). In order to “unlock” the high-speed demo option, please do the following. 11. Go to Quick Settings → Defined Symbols and open it in a new window: Now add after last symbol, the following line: "PH_EX12_ENABLE_DUALINTERFACE_HBR", by clicking on “add button” ("+" shown in green) on top right side of above window; add it manually then click OK two times. Now, build Ex12 again and check that there are no errors. 12. Debug Example 12, then press Run button and check if Console has 5 options in its Menu: Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator     with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder     with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 13. Let's focus on the last two options: 4 – perform HBR (high bit rate) transfer, and 5 – Configure your NTAG X DNA for HBR. 14. If this is the first time you are using this NTAG X DNA connected to MCXA153, then choose option 5 so that PN5190 will write proper configuration data to NTAG X DNA next to it. For this reason, turn on NTAG X DNA connected to FRDM-MCXA153 board (after powering it up with a simple 5V-USB source), and place NTAG X DNA antenna over PNEV5190BP board antenna (connected to MCUxpresso), as in picture shown above. Enter your option : 5 Ready to detect Type A Tag is discovered.       Select NDEF Application Successful       Authenticate Application Successful       SetConfig Successful       StdDataFile with File ID 0xE106 already exists. Please Remove the Card 15. Remove NTAG X DNA antenna from PN5190 antenna, until you get back to initial menu. Then, choose option 4 on previous menu: 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 4  Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : 16. Now, choose the lowest speed "1"; check final result: Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 5.72 kB/s, Time = 17.25 s Please Remove the Card 17. Separate both antennas, and then, choose option "2"; check final result: Enter your option : 2 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller… Amount of data exchanged 101200 Bytes, Baudrate (total) = 10.49 kB/s, Time = 9.41 s 18. Separate both antennas, and then, choose option "3"; check final result: Enter your option : 3 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 13.89 kB/s, Time = 7.11 s Please Remove the Card 19. Separate both antennas, and then, choose option "4"; check final result:  Enter your option : 4 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 16.57 kB/s, Time = 5.96 s Please Remove the Card Conclusions: This demonstrator HW & SW can show that high speed interaction can be achieved between PN5190 (NFC Front end) and NTAG X DNA (NFC connected tag), making use of available commands described in its product support package (https://www.nxp.com/products/NTAG-X-DNA). Disclaimer:All SW available here is aimed only for evaluation purposes and NXP disclaims any direct or indirect liability damages, since referred SW bundles are not yet official part of PN5190/NTAG X DNA standard product support packages currently available at nxp.com.  

RF power regulation is a critical factor in the development of NFC devices, as it directly influences performance, reliability, and compliance with industry standards. There are three main reasons for this:  If the PN7642 VUP current exceeds the limit given by the product Data sheet, the PN7642 can be damaged. If too high RF power is radiated from the antenna, there exists a risk for NFC Cards. Too high RF power might lead to exceeding a given RF limit (NFC Forum, ISO, EMVCo). NXP provides comprehensive documentation on Dynamic Power Control for the PN7642 and PN5190. Designers are expected to adhere to these guidelines, especially when aiming for compliance with standards such as EMVCo. PN5190 Dynamic Power Control Quick Calibration and TxShaping Demo Automatic DPC Calibration for PN7642 and PN5190 However, if the user's design is intended for infrastructure applications, such as a smart lock. At a minimum, Dynamic Power Control (DPC) should be enabled to serve as a current limiter. The evaluation can be done with the help of NFC Cockpit.  1// Start DPC Calibration  "Press" Start DPC Calibration  "Press" Load protocol  Make sure that the DPC is "Enabled" 2// Adjust current reduction table  Set all entries to "0" Write into EEPROM   3// Set the "Target" current Use approx. the same current as "TxLDO Vales"  Save to EEPROM   4// Check the power regulation  Start DPC Calibration  Place a card or any metal object in the antenna's proximity  Observe VDDPA and "TxLDO" current  The current should stay around the given target  The VDDPA will drop once the antenna is loaded  5// Set a minimum VDDPA in DPC  In the case that the current is still too high, a user can define a minimum VDDPA that is used for the DPC regulation. By default, this value is set to 2.2V. The user can decrease it up to 1.5V.  In that case, NXP also recommends disabling the RDOn control.  Note: The User has to consider the "DPC_TXLDO_MAX_DROPOUT" parameter, which defines the maximum voltage drop on TXLDO. By default, it is set to 3.6 V. That means if the user wants to use the minimum VDDPA 1.5 V, then the maximum TXLDO input shall not exceed 5.1 V. This feature protects the TXLDO from overheating.    Once the evaluation is done, the customer shall program the following EEPROM entries in their application. For more info, see PN7642 Product Data sheet.  DPC_CONFIG (Address: 0x0068) -> example: enabled -> 0x01 DPC_TARGET_CURRENT (Address: 0x0069) -> example: 229 mA -> 0xE5 DPC_TXLDO_MAX_DROPOUT (Addresses: 0x0073 - 0x0074) -> example: 3.6 V -> 0x10,0x0E DPC_TXLDOVDDPALow (Address: 0x006F) -> example: 1.5 V -> 0x00 DPC_HYSTERESIS_LOADING (Address: 0x006B) -> example: 20 mA -> 0x14 DPC_HYSTERESIS_UNLOADING (Address: 0x006E) -> example: 10 mA - 0x0A DPC lookup table entries (Addresses: 0x007D - 0x0125) -> example: for current limitation only -> all 0x00 If a user does not want to use a maximum range of VDDPA during DPC (5.7V), e.g., their system uses a 3.3V supply domain. Then, the maximum VDDPA in DPC can be limited by the following EEPROM settings:  TXLDO_VDDPA_MAX_RDR (Address: 0x0007)-> example: 3.0 V -> 0x0F Note: TXLDO has approx. 0.3V voltage drop. Always set this parameter 0.3V lower. Once this is done, the user has to check the "TxLDO" current and adjust the target current accordingly. In this case, to approximately 150 mA. If you don´t change it, the DPC starts to limit the power around 229 mA, as has been set in a previous step. 

The PN7642 includes a USB interface, which allows USB communication with the PC.  Once the PN7642 USB communication is established, the NFC Cockpit tool can be used for RF debugging.  Note: This also requires flashing the NFC Cockpit application with the help of the mass storage mode or SWD interface.  Basically, the user has to connect a USB cable/Connector to the following PN7642 pins.  USB Signal  PN7642 Pin  5V  USB_VBUS Data - ATX_D Data + ATX_C GND GND   See an example below. This is a very basic connection (for evaluation or debugging only) where the USB cable is directly connected to the PN7642 pads.  This situation may arise during debugging on customer hardware where the USB interface is not yet implemented on the PCB. But a user wants to debug with the help of NFC Cockpit.    Please note that the proper USB interface might require special layout rules, such as impedance, overvoltage protection, etc.. For more info, see the PN7642 EVK reference schematic or USB PCB design guide. 

This might be convenient if the user wants to use NFC Cockpit on their device.  See the photo of PNEV5190BP EVK with the instructions.          1. Place R5 and R7, keep R6 open    2. Place R20, keep R19 open Note: This step depends on the voltage domain used in the external hardware. If R19 is placed -> 1.8V domain, if R20 is placed -> 3.3V domain.    3. Remove VBAT, VBAT_PWR, and VUP jumpers to disconnect the "internal" PN5190 located on the EVK    4. Connect the following SPI lines to external PN5190 (e.g., customer HW) SPI_CLK SPI_MOSI SPI_MISO SPI_CS NFC_IRQ GND Note: It is also necessary to disconnect the external PN5190 from the customer MCU. 5. Connect VEN to the external PN5190  NFC_VEN   Now, the external PN5190 HW should communitate with the MCU located in PNEV5190BP, and the NFC Cockpit can be used. The user should see that the blue LED is on. If the red LED is blinking, there is an issue, and the user should check the connections/supply. 

LPCD (Low Power Card Detection) works on the principle that the I and Q values are extracted from the RF signal captured on the RX pins. These values are then compared with the I and Q data obtained using LPCD calibration. If the difference is greater than the chosen I and Q threshold, the load is detected and the IC wakes up.  1// LPCD Way of working  Run LPCD Calibration  It is recommended to use an external power supply to supply the EVK board. If the USB supply is used, the value can fluctuate because of the transition effects.  Run "Single LPCD" and check the performance  Adjust the I and Q thresholds  Low value -> Better detection range, more false wake-ups  High value -> Worse detection range, fewer false wake-ups  The number of samples, RSSI, and VDDPA parameters typically remain at their default values.  2// Auto LPCD  When the "Auto LPCD" is used, the LPCD algorithm always performs LPCD Calibration before entering the LPCD. 3//Semi-autonomous LPCD mode (PN5190 only)   The user can evaluate the I and Q values behaviour under loaded/unloaded conditions. Based on that, the LPCD threshold can be properly selected.  Use the same "Register" RSSI Target and Hysteresis as for "EEPROM" Calibrate LPCD Run "Endless I/Q read"  Check how the I and Q values change With no card/object in the antenna proximity  with a NFC card/object in the antenna proximity

This document show the detail steps of following the Personalization example in AN12196. Tool : Pegoda3 and RFIDDiscover.    

A user can evaluate the current consumption of PN7642 in low power modes with the help of the PN7642 Evaluation Board (OM27642) and:  MCUXpresso SKD example (LPCD)  NFC Cockpit or MCUXpresso SKD example (ULPCD) NXP defines the current consumption in ULPCD/LPCD as VBAT current + VDDIO current for the LPCD/ULPCD cycle time of 330 ms. Make sure that DC/DC is disabled.  Where:  VBAT current = VBAT_Current + VBATPWR_Current + VUP_Current See the snapshot from the PN7642 Datasheet below:    See where to measure the currents on PN7642 EVK: J63 and J64 are used for enabling/disabling the LEDs that are connected to PN7642 GPIOs. They must be disabled for VDDIO current measurement.  A modification of R69 and R70 is necessary to perform the current measurement on VDDIO in LPCD mode.   1. ULPCD current consumption evaluation For the ULPCD evaluation, the NFC Cockpit or SDK example can be used. In this article, we will focus on evaluation using the NFC Cockpit.  See the used ULPCD configuration:    Note: The current should be measured as an average over, e.g., 10 seconds.  The ULPCD current can be evaluated separately, as shown in the following chapters  2.1 VBAT Current measurement 2.2 VBATPWR Current measurement 2.3 VUP Current measurement  2.4 VDDIO Current measurement  This might be helpful to understand the contribution of each current in ULPCD.  The overall average current can also be measured directly, as shown in  2.5 Overall ULPCD current measurement    2.1 VBAT Current measurement    In this case, the VBAT current is approximately 13,7 μA. 2.2 VBATPWR Current measurement   In this case, the VBATPWR current is approximately 2,1 μA. 2.3 VUP Current measurement    In this case, the VUP current is approximately 5,5 μA. Note: This current depends on the ULPCD VDPPA settings + Antenna Impedance tuning and RF_ON time  2.4 VDDIO Current measurement  Note: Before VDDIO measurement, place jumpers J63 and J64 on PN7642 EVK. This will disable LEDs that are connected to PN7642 GPIOs.    In this case, the VDDIO current is approximately 3,7 μA.  Then the overall current comsumption in ULPCD is I_VBAT+I_VBATPWR+I_VUP + I_VDDIO= 13,7 + 2,1 + 5,5 + 3,7 μA = 25 μA 2.5 Overall ULPCD current measurement  To measure all currents together, a user can create a measurement fixture as shown below:  Real setup :  Then the overall results look as follows:   As can be seen, the directly measured ULPCD current consumption is around 24 μA. 2. LPCD current consumption evaluation The user has to import the example (pnev7642fama_nfc_low_power_mode_Pub) from the PN7642 SDK.  Before building it, the following change in the code has to be made:  -> Comment line 84   A user can adjust the LPCD cycle time as shown below:   1.1 VBAT Current measurement    In this case, the VBAT current is approximately 123 μA. 1.2 VBATPWR current measurement  In this case, the VBAT_PWR current is approximately 91,8 μA. 1.3 VUP Current measurement  In this case, the VBAT_PWR current is approximately 32,8 μA.  Note: This current depends on the LPCD VDPPA settings + Antenna Impedance tuning  1.4 VDDIO Current measurement Note: Before VDDIO measurement, place jumpers J63 and J64 on PN7642 EVK. This will disable LEDs that are connected to PN7642 GPIOs.  The VDDIO current measurement requires the following steps:  Run the "pnev7642fama_nfc_low_power_mode_Pub" example  Once the example is running, disconnect the debugger (J-link, LPC-Link...) from J21 (NFC Debug connector)    Remove R70  Populate a 10K resistor on the R69 position (it disables the SWD interface) Once the measurement is done, change it back to the default state (R70=0R, R69=Open). Note: It is recommended to prepare the board with the option to easily populate or remove R70 and R69 when the LPCD example is running. E.g., with the help of jumpers/pin headers as shown below.   Only then will the correct VDDIO be measured on PN7642 EVK.  See the VDDIO current measurement below:    In this case, the VDDIO current is approximately 5,48 μA.  Then the overall current comsumption in LPCD is I_VBAT + I_VDDIO= (123 + 91,8 + 32,8 + 5,48) = 253,08 μA Note: For this measurement, the NFC Cockpit is not suitable because the IC does not go into standby mode between LPCD RF pings. Meaning LPCD works normally, but a user can measure higher current consumption. Used Ampere meter -> Power Profiler Kit II Measurement has been performed with FW 2.6  Board supply (jumpers J1, J2 and J4) -> 3.3V Please note that this measurement is indication only! 

Step 1:  Disable the DCDC in settings (Valid for PNEV5190B and OM27642EVK) Write 0x21 into EEPROM PWR_CONFIG (address: 0x0000) This disables the DCDC. & selects that the VUP must be supplied with the same supply voltage as VBAT = VBATPWR. Do not enable RF afterwards, before the hardware is modified properly! Enabling the RF without supplying the VUP might kill the PN5190/PN7642! Step 2: Supply VUP = VBATPWR  Connect jumper J13 positions: 1-2: This supplies the VUP with VBATPWR = 3.3V PN5190 EVK: Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.    PN7642 EVK:  The OM27642EVK does not require any jumper settings (DC-DC is not used by default), the User must only disable DC-DC in EEPROM (address 0x0000, value 0x21) Then you can turn-on RF and perform ULPCD   Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.  Also, R8 shall be placed   

Introduction NTAG5 offers a powerful energy harvesting feature (up to 30mW). One useful application can be charging the supercapacitor which then might be used as the supply of customer MCU, Sensor, etc.   See the typical schematic below:  C1 and C1P are used for the impedance tuning. The antenna is typically tuned at 13.56 MHz-14MHz.  R1 is used to limit the charging current of the supercapacitor. Its value depends on the selected VOUT voltage, keep in mind that the maximum output current is 12.5 mA.  E.g. VOUT=2.4V, Icharging=10mA -> R1=240 Ohm Keep in mind, that if the charging current is too high and/or the amount of the received magnetic field is not high enough, the VOUT may drop.  D1 should be a low-drop diode e.g. RB520CS30L Used super cap: CPX3225A752D Antenna size  Generally, it is best to attempt to match the tag and the reader antenna geometries for maximum efficiency. A significant difference between the reader and tag antenna dimensions result in bad communication and energy harvesting performance because of the small coupling factor. As smartphone NFC antennas can have different dimensions. It might be challenging to design one NFC Tag antenna that will deliver the best performance for multiple smartphones.  The phone's NFC Antenna dimensions are typically between approximately 25 mm vs 20 mm (NFC Forum Poller Class 6) & 50 mm vs 30 mm (NFC Forum Poller Class 3). Note: But this might be different e.g., iPhones  So customers can consider the following form factors of NFC antennas for their Energy harvesting NTAG5 Link design:  For bigger designs (NFC Forum Listener Class 3):    For circle NFC Antenna ->Outer diameter is approx. 44 mm    For smaller designs (NFC Forum Listener Class 6):  For circle NFC Antenna ->Outer diameter is approx. 25 mm     Tomas Parizek  Customer Application Support 

How to set the RF Settings can be found in -> https://www.nxp.com/docs/en/application-note/AN13218.pdf The list of the default values + values which shall not be changed is available in the attachment.  Tomas Parizek  Customer Application Support 

  NXP offers FW update code as part of the SW6705.   All PN7160 FW versions including ".c" files are available on PN7160 Github.    PN7160 is typically delivered with the initial FW 12.50.05. To ensure full reliable functionality, it is highly recommended to update the FW on 12.50.09 (or latest). The FW update might be also helpful if you need to restore the default EEPROM settings.  The FW source data are inside the sFWudpate folder.  phDnldNfc_UpdateSeq.c -> FW Version 12.50.05 phDnldNfc_UpdateSeq_12_50_09.c -> FW Version 12.50.09 The phDnldNfc_UpdateSeq.c is executed, which means what is inside of this "C" file is pushed to the PN7160 EEPROM.  So, if you want to update from 12.50.05 to 12.50.09. You need to copy content from phDnldNfc_UpdateSeq_12_50_09.c to The phDnldNfc_UpdateSeq.c.  Also, make sure that the content in phDnldNfc_UpdateSeq_12_50_09.c is commended.   Once that's done, you can debug the code.  Then you can check the progress in "Terminal"    Tomas Parizek  Customer Application Support 

The PN5180 offers a low-power card detection (LPCD) feature, which allows to power down the reader for a certain period of time to safe the energy. After this time the reader must become active again to poll for the cards. If no card has been detected, the reader can go back to the power down state. PN5180 LPCD cycle time includes standby time and VBAT time. In a normal case, standby time is 200ms (user can define it),   standby current is 15uA, VBATON current is 7500uA, FieldON current: 200mA.  Average current is about 200uA, it depends on your settings and application.   This article describes how to configure PN5180 LPCD using NXP Cockpit Tool and using NXP NFC Reader library.   1  PN5190 LPCD Overview PN5180 LPCD operates in two modes: auto calibration mode and self-calibration mode. Auto calibration mode:  everything done automatically Self-calibration mode:   calibration must be done manually before starting the LPCD.   1.1  Auto Calibration Mode ( 00b) The LPCD calibration is done automatically when the LPCD is started, using the gear and threshold as defined in the EEPROM. This mode always uses the same gear for the LPCD, and is the fast and easiest way to start the LPCD.  It is recommended to choose a gear, which always keeps the ITVDD and field strength limits, so normally, the highest gear number. Auto calibration mode is most commonly used, it is a standard use case. Below parameters need to be configured correctly in EEPROM   LPCD_REFERENCE_VALUE       LPCD_REFVAL_GPO_CONTROL      LPCD_THRESHHOLD  ( 0x37) LPCD wakes up, if current AGC during “ping” > AGC Reference + LPCD_THRESHOLD or< AGC Reference -LPCD_THRESHOLD Minimum LPCD_THRESHOLD = 03…08 (very sensitive) Maximum LPCD_THRESHOLD = 40 … 50 (very robust)    LPCD_FIELD_ON_TIME  (0x36) RF on time in 8µs, excluding the fix time .   Fix time = 62µs 01 => RF on = 70µs 02 => RF on = 78µs 03 => RF on = 86µs 10 => RF on = 190µs   1.2  Self Calibration Mode (01b) The LPCD calibration must be manually triggered, with reading or writing into the AGCREF_CONFIG register.   Reading from this register - without prior writing - starts an LPCD calibration. The calibration is executed using the gear which is resulting from the actual DPC setting under the actual antenna detuning condition. AGC_GEAR is used in the LPCD self-calibration.   Reading from this register - without prior writing - delivers in addition to the AGC_GEAR value the AGC_VALUE. The AGC_VALUE is used in the LPCD self-calibration. Writing to this register: Writing data to this register is required before starting the LPCD in Self-calibration mode. Either the previously read AGC_GEAR or a user-defined gear can be chosen. The previously read AGC_VALUE has to be written in any case. Writing data to this register defines the values for AGC_GEAR without taking the actual detuning condition into account. The value of AGC_GEAR to perform an LPCD calibration which derives the AGC_VALUE. This AGC_VALUE and the AGC_GEAR are used in the LPCD self-calibration.   Self-calibration mode always requires a Read AGC_REF_CONFIG, followed by a write AGC_REF_CONFIG, using the previously read AGC_VALUE.   The LPCD calibration can be done in two different options: Option 1:  Read AGC_REF_CONFIG register:  This command executes a standard RF Field on. So depending on the load condition the DPC adjusts the output power. The final gear is take as gear for the LPCD.  This option guarantees that the maximum output power is taken for the LPCD.   Option 2: Write AGC_REF_CONFIG register: This command executes a LPCD calibration ping with the gear number, as defined in the AGC_REF_CONFIG, bit 10:13. This option allows a flexible use of any of the defined gears for the LPCD.   PN5180 LPCD self-calibrate is executed, using Gear -> AGC_REF_CONFIG (Register) Threshold -> LPCD_THRESHOLD (EEPROM) RF on time-> LPCD_FIELD_ON_TIME (EEPROM)   2  How to configure PN5180 LPCD with Cockpit The NFC Cockpit allows the configuration and test of the low power card detection of the PN5180 as shown in below picture. The LPCD parameter, which are stored in the EEPROM, can be changed and the LPCD can be started. The LPCD tab allows to directly define and write the related EEPROM addresses:   LPCD Gear #: Defines the gear number, which is used for the LPCD in auto calibration mode, stored in addr. 0x34, bit 0:3 Threshold Value: Defines the threshold window, As soon as the AGC value during the LPCD ping exceeds the AGC reference value + threshold window, the IRQ will be raised and the PN5180 wakes up. Field On Time:  Defines the ping length Standby time :  This value defines the time between two pings in ms. FieldOn Current: This value is ITVDD under the loading condition, when RF field is on with the used gear. This value does not have any influence on the LPCD execution, but simply is used to estimate the overall  average current consumption. This current estimation is calculated, when the LPCD is started.         3   How to configure PN5180 LPCD with NXP NFC reader library. The LPCD works in two phases: First the standby phase is controlled by the wake-up counter (timing defined in the instruction), which defines the duration of the standby of the PN5180. Second phase is the detection-phase. The RF field is switched on for a defined time (EEPROM configuration) and then the AGC value is compared to a reference value.   Below is the flow chart for PN5180 LPCD          

DISCLAIMER APPLICABLE TO THIS DOCUMENT CONTENTS:   PN5190-NTAG 5 boost High Speed Communication Demo This article describes the unique feature of these two chips when interacting with each other at contactless interface: Passthrough demonstrator at high bit rates for ISO 15693 between PN5190 and NTAG5 Boost. Scope of demonstrator: ▪ Demonstrating a unique feature of NXP Semiconductors. High bit rates for ISO15693 communication (212 kbps) between a PN5190 reader IC and an NTAG5 boost connected to LPC55S69 host MCU, when implementing passthrough mode using the SRAM of the NTAG 5 boost. ▪ Through MCUXpresso console, the user can configure the contactless bit rate (26.4kbps or 212kbps options) as well as the amount of data to exchange using passthrough mode. ▪ Passthrough mode is implemented from NFC reader to LPC side only. ▪ The PN5190 prints on the MCUXpresso console the outcome of the transaction and baud rate achieved. ▪ In order to handle passthrough communication, we are using GPIO interrupt handlers on the NTAG 5 boost + LPC55S69 side and hard coded timeout on the PN5190 + MCU side. Required hardware and software material: Hardware ▪ PNEV5190BP development board ▪ LPCXpresso55S69 Development Board ▪ OM2NTA5332 - NTAG5 boost development kit ▪ 3 x USB micro cables Software ▪ Firmware Source Code for PN5190 is attached to this article, containing keywork pn5190: HIGHSPEED_PN5190_NTAG5boost1.zip ▪ SDK_2.x_FRDM-K82F is already included in bundle mentioned above. ▪ Firmware Source Code for LPCXpresso55S69 is attached to this article, containing keyword lpc55s69: NTAG5boost_LPC55S69.zip ▪ MCUXpresso IDE recent version (v24.12.148 or newer) Demonstrator bring up: Hardware assembly for LPCXpresso55S69: • Connect NTAG5 Boost board to LPCXpresso55S69 • Make sure SW6 is on position 2-3 to enable 5V power on tag side (it will also work at 3.3V but maybe with less readrange). • Connect LPCXpresso55S69 board to your computer (Debug Link Input). • No additional power source is needed. Hardware assembly for PNEV5190BP: • Connect two USB micro cables to PNEV5190B board for power and flashing firmware via UART connection (alternatively, you may change jumper J9 to position 2-3 and connect an external power supply, Vin > 7 Volts) • Red LED indicates power is enabled • Green LED debugging/UART status Software loading on LPC55S69: Import “lpcxpresso55s69_ntag5_passthrough_nolib” project (included in NTAG5boost_LPC55S69.zip) into MCUXpresso IDE. • Install SDK_2_12_0_LPCXpresso55S69. This SDK can be downloaded from • https://www.nxp.com/security/login?service=https%3A%2F%2Fmcuxpresso.nxp.com%2Flogin%2F  • Build project and flash a binary file using GUI Flash Tool. After flashing, reboot your board. Blue LED must be enabled which means tag is waiting for field to be detected. Under MCUXpresso: 1. Import project from file system 2. Select lpcxpresso55s69 project 3. Uncheck copy projects into workspace Software loading on PNEV5190B: • Unzip the “HIGHSPEED_PN5190_NTAG5boost1.zip” in a folder. • Import all projects inside “HIGHSPEED_PN5190_NTAG5boost1” project to MCUXpresso IDE • Install SDK_2.x_FRDM-K82F. Such SDK is included in project file tree: • nxp-connected-tags-pn5190\Platform\SDK_2.x_FRDM-K82F • Build project and flash a binary file using GUI Flash Tool. After flashing, reboot your board. Blue LED must be enabled which means reader is waiting for NTAG5 to be detected. • Start Debug session to see available bitrate options on the console. Under MCUXpresso: 1. Import project from file system 2. Select all the projects 3. Uncheck copy projects into workspace LED User Interface Specifications (same for LPCXpresso55S69 an PNEV5190B) • Steady blue - waiting for Tag - discovery loop, • Blinking green - passthrough transfer ongoing • Steady green - all data transferred successfully. • Steady red - error - tag lost during transfer. Menu options when two boards have NFC antennas facing each other: Two options of bitrate are available for transfer amount of data from host to NTAG5 Boost: ▪  standard 26.4 kbps or ▪  highest bit rate 212 kbps It is possible to configure amount of data to be exchanged between PN5190 and NTAG 5 boost (check option 3, and then choose among following file dimensions): ▪1KByte ▪2KBytes ▪10KBytes ▪512KBytes Demonstration flow: Once one of these options is selected, reader is ready to detect a tag. ▪ When tag is detected, reader configures selected bitrate and starts data exchange. ▪ Blinking green LED indicates transfer ongoing and the console shows a progress. Here are some results of transaction at the different bit rates and data sizes offered by this demonstrator: Data Size (Bytes) Selected bitrate (kbps) Result Bitrate (kbps) Transfer time (ms) 1024 26.4 2.8 357 1024 212 12.35 81 2048 26.4 2.8 714 2048 212 12.42 161 10240 26.4 2.7 3569 10240 212 12.41 806 512000 26.4 2.8 177739 512000 212 12.63 39576   High speed demo user manual can be also find attached to this article: 22-10-11 NXP - Connected Tags demonstrator User Manual.pdf Conclusions: This demonstrator HW & SW can show that high speed interaction can be achieved between PN5190 (NFC Front end) and NTAG 5 boost, making use of available commands described in product support package. Disclaimer: All SW available here is aimed only for evaluation purposes and NXP disclaims any direct or indirect liability damages, since referred SW bundles are not official part of PN5190/NTAG 5 boost standard product support packages available in nxp.com.  

AN13189 provides guidelines for the integration of PN7160 NXP NCI-based NFC controller to an Android platform from software perspective. But some developers found some compile issues when integrating PN7160 NFC package into Android 11.   This article describes how to fix the build error when you integrating PN7160 NXP NCI-based NFC controller to Android 11 system.  You need to follow the AN13189 (PN7160 Android porting guide ) first.  After you run the installation script install_NFC.sh, the following modification should be added to the source code. 1) Open package/apps/Nfc/nci/jni/Android.bp Add  "-DNXP_EXTNS=TRUE",   2 )  open system/nfc/src/Android.bp Add   "-DNXP_EXTNS=TRUE",     3 )   open packages/apps/Nfc/src/com/android/nfc/NfcService.java And add this: between isNfcSecureEnabled and setNfcSecure methods:             @Override         public IBinder getNfcAdapterVendorInterface(String vendor) {             if(vendor.equalsIgnoreCase("nxp")){                     return (IBinder) mNfcAdapter;             } else {                    return null;             }         }     Next, follow AN13189, complete the following steps in section 4.2. Then you can build the package successfully.  Thanks  @andraz_skupek .      

Using an alternative clock source to set up PN7462's contact interface clock , so that we have more options of the clock frequency.

The code is based on the application note https://www.nxp.com.cn/docs/en/application-note/AN12657.pdf. It mostly shows how to communicate between LPC1769 and RC663 via SPI based on board CLEV6630B without library and which Register have to be set to send a REQA (NTAG21x).

Demo for Originality Signature Verification(AN11350)

--The document consists of the following: Step 1. Connections And Firmware Version Step 2. Updating FW On PC Windows 10 Step 3. Updating FW On VMplayer16.0 + Ubuntu 20.04 Step 4. Updating FW On i.MX8MN-EVK With Embedded L5.4.70_2.3.0 BSP Step 5. Confirming whether update is successful using cockpit4.8 --About Cockpit There are several different versions of cockpit, and each version can only recognize the same version of firmware. --Reference Materials 1.https://community.nxp.com/t5/NFC/Mounting-the-PN7462AU-in-the-USB-downloader-mode-under-Linux/m-p/800939 2.https://community.nxp.com/t5/NFC/PN7462-updating-EEPROM-on-linux/m-p/739808/highlight/true#M3144       NXP CAS-TIC team Weidong Sun 04-15-2021  

     This document mainly describes how to use NanoNVA tool to do antenna tuning on OM29263ADK with CLEV663B/PN5180B board. Please refer to the application note AN12810(https://www.nxp.com/docs/en/application-note/AN12810.pdf) about the NanoVNA tool. And please refer the user manual UM11098 (https://www.nxp.com/docs/en/user-guide/UM11098.pdf) about OM29263ADK. After setting NanoVNA tool with reference to the above documents. Firstly, take the small antenna of OM29263ADK with CLEV663B as an example. The small antenna can be directly connected and used on the CLEV6630B。the antenna board can be directly connected to the CLEV6630B without any additional modification, after the original antenna had been removed (cut off).   The result of the antenna tuning with NanoVNA tool as the below:   Second, take the small antenna of OM29263ADK with PN5180B board as an example. Follow the UM11098 steps as the below: (a) the EMC filter cut off frequency must be adjusted, and (b) the DPC and related features should be disabled, since the antenna is asymmetrically tuned and the DPC is not used. (a) The original antenna uses a symmetrical tuning, which uses an EMC filter with L0 = 470nH and C0 = 253pF (220pF + 33pF). The inductor as well as the first part of the capacitance (220pF) are assembled on the main board. To operate the OM29263ADK antenna, the C0 (220pF) on the PNEV5180B must be replaced by a 68pF.   (b) The DPC and its related features should be disabled to operate an asymmetrical antenna.   If can’t get the card information please refer to the AN11740’s related steps to achieve a good sensitivity of RxP/RxN path. The result of the antenna tuning with NanoVNA tool as the below:   The whole process of the small antennas tuning of OM29263ADK with CLEV66B/PN5180 with NanoVNA is completed. PS: It is the similar with the steps for the large antennas tuning of OM29263ADK with CLEV66B/PN5180 with NanoVNA.  

Please kindly refer to the attachment for details.   Hope that helps,