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ST7701 drivers Hello I'm trying to communicate with a ST7701 display controller. Are some examples available? Can anyone share if possible? I'm using an i.MX RT1170 board. In the SDK examples I found the drivers for the HX8394, RM68191 and RM68200 display controllers. I would like to find something similar for ST7701. Can anyone help me please? Thank you and kind regards, Francesco Solito Re: ST7701 drivers Hi @SolitoFrancesco, At the moment, we don't have any driver support in our SDKs for the ST7701 display controller. The integration with this controller would have to be done manually. It is important to adjust the resolution values, synchronization signals and clock frequencies of the LCDIF module to allow compatibility with the display controller. If using the EVK, you can use the SDK drivers and adjust the values of the following functions: BOARD_InitLcdifClock() BOARD_InitMipiDsiClock() BOARD_SetMipiDsiConfig() These functions along with the macros for the synchronization values and are all referenced on the "display_support.c" file, which will be the main file to focus on when adjusting the support for your display controller.   Also make sure to look into the following application note, as it goes into a lot more detail about how the setup for an LCD display works and other useful considerations: i.MX RT eLCDIF RGB Mode Use Case (nxp.com)    BR, Edwin. Re: ST7701 drivers Good morning I modified the files you mentioned, following the indications that I received from the display manufacturer and from the driver manufacturer. I'm able to write and read into the driver registers through MIPI. I can see the differential MIPI waveforms with oscilloscope (also after the "configuration" phase), but I'm still not able to see anything on the display. I'm using the demo example from NXP SDK called "mipi_dsi_compiance_test". Can you please try to help more? Thank you and kind regards, Francesco Solito Re: ST7701 drivers Hi @SolitoFrancesco, Have you been able to debug your code while running? Do you see any error message being printed? And what data patterns do you see on the data line? Do these patterns coincide with the expected ones described on the readme.md file? BR, Edwin. Re: ST7701 drivers Hello, I have the same situation (same driver and resolution, and the base is a test example that worked on the devboard). The controller is configured, and I can also read the statuses (without any errors), and the data on the DSI lines is present, but the screen displays nothing. Changing the videoMode in dsi_dpi_config from kDSI_DpiBurst to other modes also has no effect. It looks like the screen isn't accepting the video stream?  Re: ST7701 drivers Hello. The example project works correctly with the display DEMO_PANEL_RK055MHD091. Then I switched to the panel that I have to use in my final application. It has different resolution (480x800) and so I adapted the defines. Then I changed the drivers (fsl .h and .c files) and I'm able to communicate with my display. I can write and readback the registers. But after the configuration of the display, when the example project starts sending the image buffer, I can see the MIPI waveforms on the oscilloscope, but nothing on the display. Consider that the display is not broken, because I tried to turn on all the pixels through the dedicated command and I can see the screen completely white. What I don't understand is if the problem is in the configuration of the display or in something else that I have to adapt in the example project. I contacted the display manufacturer and the controller manufacturer, but I need as much help as possible from all sides. Is it possible to get the fsl drivers for the controller that is mounted in my display? It is a Sitronix ST7701. Please let me know. Thank you and kind regards, Francesco Re: ST7701 drivers Hello Rino I'm making a comparison between my settings and yours (at the end I'll upload here). In the meanwhile, what I noticed is that I'm using a ST7701, instead you are probably using a ST7701S (with S suffix). I think they are similar but I'm not sure. The thing that I noticed is that the display now works even if I don't make any initialization at all. It starts "slowly" and with low britghteness, but it works. Then, if I only sends the settings from 0xE0 to 0xEF (that aren't documented in the ST7701 datasheet), the display start up very fast and with the correct colors. It seems that all the other settings are not necessary (it sounds strange). Let's keep in touch. I'll share the comparison when I'm finished. Thank you very much again. Kind regards, Francesco Re: ST7701 drivers Hello Francesco,  I managed to get the display working. In the DisplayTFT_SetMipiDsiConfig function, add the line: dsiConfig.enableNonContinuousHsClk = true; for example, after these lines: DSI_GetDefaultConfig(&dsiConfig); dsiConfig.numLanes = DISPLAY_MIPI_DSI_LANE_NUM; dsiConfig.autoInsertEoTp = true; Assuming you have the display IC configured correctly (if necessary, I can share the configuration for my screen) and the display clock (my settings are around 26MHz). Best regards, Chris Re: ST7701 drivers Hello Rino Thank you very much for your suggestion. It seems to work also in my application. Great. I probably need to better setup something, but now I can see the image on the screen. Please if possible share your configuration, so I can compare with mine to better refine it. If I see something different I'll tell you here. Thank you again. Where did you came up the the enableNonContinuousHsClk setting? Kind regards, Francesco Re: ST7701 drivers Hello,  the file was created based on other drivers in the SDK. You can still change the delays to shorter ones. This morning, I confirmed the configuration sequence and made a few changes as recommended by the display manufacturer, but there was no further improvement, so I started taking a closer look at the DSI configuration itself. I know the clocks were fine, and so was the video mode (burst mode), so the only options left were those for the DSI itself. Familiarizing myself with (and other parts in docs): https://docs.nxp.com/bundle/AN13573/page/topics/continuous_vs_non-continuous_clock.html BR, Chris  Re: ST7701 drivers Hello Rino As promised, please find in attachment the settings comparison between yours and mine. I didn't go in details, but if me or you will find something interesting in the differences, please let's continue to write here. Kind regards, Francesco Re: ST7701 drivers Hello Francesco, Sorry for the delay. I looked through your comparison and noticed a lot of differences, partly due to the screens themselves (we have a glass/touch/screen sandwich, and there was a configuration fix for that – or at least that's what the supplier explained 🙂 ). Some settings, like power control, aren't required for startup, but for quality improvement (contrast/gamma settings). And what's funny is that the whole "Sunlight Readable Enhancement" thing, I think they called it, is required, regardless of whether we're running it or not. Based on this data, it automatically sets optimal parameters. If they're incorrect or missing (default values), it takes a while to automatically set them -> hence the slow startup, as you've noticed. The documentation itself can be quite irritating, many of the commands are undocumented, and without them, it's often impossible to fully start the screen. This isn't just with this model, I've encountered this with several other Sitronix models. Kind regards, Chris
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如何禁用 QSPI 1 上的 MGC 访问控制? 我正在努力使用自定义驱动程序让 QSPI 在 S32E2 评估板上运行。我正在使用 JTAG 加载代码并耗尽内存,因为我们正在从 EMMC 启动切换到从 QSPI 启动。评估板将 QSPI 闪存连接到 QSPI1 B。我在写入某些寄存器(主要是 SFAR)时遇到了问题。SFAR 似乎受 MGC 保护,因此我想通过清除第 31 位(GVLD)来禁用访问控制。 但是,根据参考手册,只能由总线主机 0x1F 访问 MGC,这是 HSE 核心。看起来 QPSI0 有一种以 HSE_QSPI0_DAT0 为形式的旁路机制,它允许更改可以访问 QSPI0 上这些寄存器的总线主机,但我一直找不到 QSPI1 的等效机制。 谁能帮帮我? Re: How do you disable MGC access control on QSPI 1? 你好,@AdamH_work、 感谢您联系恩智浦技术支持。关于您的问题,我需要一些时间来寻找访问您提到的寄存器的正确方法。 现在,我建议你看看我们在 S32ZE RTD 2.0.1 中提供的 qspi_ip_example_s32z2xx_r52 或 memacc_example_s32e2xx_r52 示例项目,尽管它使用了 RTD,但它可以让你了解在 S32Z/E 系列中使用 QSP I 所需的步骤。 谢谢! Re: How do you disable MGC access control on QSPI 1? 你好,@AdamH_work、 对不起,我的回复晚了。 另请查看第 65.1.6 节 QuadsPi_0 与网络安全寄存器之间的相互作用中的表格 [第 3349 页,S32Z2 参考手册,第 5 修订版,2025-01-28],第 121.2.1. 5 节 QuadsPi_0 数据 0(HSE_QSPI 0_DAT0)[第 6674 页]。在表的第一行中,它说明了如何配置可以访问MGC寄存器的主ID,具体取决于HSE_QSPI0_DAT0的值 。 请告诉我您是否解决了这个问题 Re: How do you disable MGC access control on QSPI 1? 我已经看到了这部分内容,但它似乎只涉及 QuadSPI 0,而我正试图在 QuadSPI 1 上实现这一点。 在此期间,我想出了如何对 MDAD 和 FRAD 寄存器进行编程,以允许所有访问通过,而且 SFAR 似乎在我启动 IP 命令时被填入,但现在它卡在忙状态,所以我可能不需要禁用 MGC 中的所有功能。 Re: How do you disable MGC access control on QSPI 1? 你好,@AdamH_work、 很抱歉造成您的困惑。现在,我的理解是,你们克服了最初的问题,对吗? 要检查发送 IP 命令的最佳流程,请查看示例项目MemAcc_Example_S32E2XX_R52,特别是请查看函数Qspi_Ip_StatusType Qspi_Ip_IpCommand(),以及静态 Qspi_Ip_StatusType Qspi_Ip_InitReset ()和Qspi_Ip_StatusType Qspi_Ip_RunCommand ()如何调用该函数。 如果您有更多问题,请告诉我。 Re: How do you disable MGC access control on QSPI 1? 在设置 MDAD/FRAD 和 LUT 编程后,我现在可以启动 IP 命令了。 作为闪存通信的第一步,我正在尝试在我的 S32E288-975EVB 评估板上读取美光 MT25QL256ABA8E12 的串行闪存发现参数。我已经在插槽 8 中设置了以下 LUT 序列: CMD PAD1 0x5A ADDR PAD1 24 DUMMY PAD1 8 读取 PAD1 16 停止 PAD1 0 似乎是启动了序列,但又陷入了无限繁忙状态。 SFAR 设置为 0x100000000(配置的起始地址),IPCR 设置为 0x08000008(插槽 8,8 字节)。我将 BUFXCR 寄存器设置所有大小均为 0,缓冲区 3 除外,我已经为所有主服务器设置了缓冲区 3(值 0x80004000)。星期五,我能够用示波器探测CS0/D0/D1引脚,我看到启动IP命令时CS处于钳位状态,但从未取消过钳位。命令和地址似乎已发送,随后是哑周期,然后 D1 进入活动状态,响应数据。 但是,它似乎从未完成读取,只是不停地将数据时钟输入,D1 上显示出重复模式,因为(我猜测)闪存芯片在其 SFDP 缓冲区中循环往复。 当我暂停执行时,我看到了这个: 我不知道是什么原因导致读取无法完成。 我阅读了数据手册中有关 QSPI 读取的部分,但没有找到任何可以解释这种行为的内容。 我尝试降低时钟(从比特时序来看,最初似乎在 100MHz 左右,但后来我在 CGM 中添加了一个 /10 分频器,它减慢了 D1 的比特模式,但没有改变繁忙的行为)。 Re: How do you disable MGC access control on QSPI 1? 你好,@AdamH_work、 根据我在内存数据表中看到的信息,SFDP (0x5A) 并非 "正常 "操作,它要求控制器故意停止通信流: 这也可以解释为什么读取的信息总是不完整。在我看来,QSPI 外围设备是正常工作的,至少它在通信,所以目前的问题可能是操作类型。您能否尝试更简单的操作?例如,您可以在我提到的示例中找到以下 LUT 序列、 MemCfg_0_SPI3ByteAddress_paInitOperations_0和 MemCfg_0_SPI3ByteAddress_paLutOperations_0在Qspi_Ip_Cfg.c 中、关于初始化操作,请查看 Qspi_Ip.c 中的 Qspi_Ip_InitOperation()。 如果您能执行另一项操作,并显示出不同的行为,请告诉我 谢谢! Re: How do you disable MGC access control on QSPI 1? 问题最终出在我没有正确设置 DLL 上。 我按照 S32DS 示例完成了 DLL 旁路模式初始化序列,并在我的代码中重新实现了它,现在它能正确完成读取操作。 下一个挑战是写入操作,但这个问题可以标记为已解决。
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IMX8M PLUS LPDDR4 2G compatibility We try to implement an ISSI IS43LQ32512A-046BLI 2GB RAM. After Calibration the RAM fails during the  memcpy SSN armv8_x32 test with 2000MHz configured. If I configure the RAM to 1500MHz it pass all the tests. Has anybody implement this LPDDR4 RAM? Is it in general compatible with IMX8M PLUS? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  Are you using DDR config tool run the Calibration? If yes,. please share your configuration page and fail log file. B.R Re: IMX8M PLUS LPDDR4 2G compatibility The IS43LQ32512A-046BLI (ISSI 2GB LPDDR4X SDRAM) is generally compatible with the NXP i.MX 8M Plus processor, as long as it adheres to JEDEC standards for LPDDR4/LPDDR4X memory. However, your issue with the memcpy SSN armv8_x32 test failing at 2000MHz (but passing at 1500MHz) is not uncommon and likely stems from configuration, board design, or calibration challenges rather than fundamental incompatibility. Compatibility Confirmation The i.MX 8M Plus supports LPDDR4/LPDDR4X memory up to 4266 MT/s (2133MHz clock), and the IS43LQ32512A-046BLI operates at up to 2133MHz (4266 MT/s data rate), which aligns with NXP's specifications. NXP's community forums confirm that similar ISSI LPDDR4X parts (e.g., IS46LQ32512A-046BLA2, which is an automotive variant of your model) are compatible with the i.MX 8M Plus, provided they follow JEDEC specs. Users have successfully implemented them without issues when properly configured. Potential Reasons for Your Test Failure at 2000MHz Based on similar reports in NXP and embedded forums: Timing/Configuration Mismatch: The i.MX 8M Plus DDR controller requires precise timing parameters (e.g., CAS latency, tRCD, tRP) from the RAM's SPD/ datasheet. At 2000MHz, your calibration might not fully optimize for the ISSI part's specs (e.g., CL=32, RL=14 at higher speeds). Lowering to 1500MHz reduces stress and passes, but this indicates suboptimal tuning. Board Design Issues: Signal integrity problems like trace length mismatch, impedance errors, or insufficient power decoupling can cause failures at higher speeds. Check for reflections or noise on DQ/DQS lines using an oscilloscope. Calibration Limitations: The i.MX 8M Plus uses NXP's DDR Tool for calibration. If your script or settings are based on Micron/ Samsung references (common in EVKs), they may not match ISSI's characteristics. Re-run calibration with ISSI-specific parameters. Power/Temperature: At 2000MHz, higher current draw could cause voltage droop or overheating, failing memcpy tests (which stress sequential reads/writes). Has Anyone Implemented This RAM? Yes, there are documented implementations: In NXP community threads, users have integrated similar ISSI LPDDR4X (e.g., IS46LQ series) on custom i.MX 8M Plus boards for industrial applications, achieving stable operation up to 2133MHz after fine-tuning. Embedded Linux/BSP developers report success with ISSI parts in Yocto-based builds, but often with custom DDR init scripts to handle the 512M x 32 organization (16Gbit density). Recommendations to Fix Your Issue Verify Datasheet Alignment: Download the ISSI datasheet (IS43/46LQ32512A series) and compare timing params with NXP's i.MX 8M Plus RM (Reference Manual, Section 13.5 DDR Controller). Key specs for your RAM: 2133MHz max clock, LVSTL interface, 1G x 16 organization (dual-channel x32 total). Re-Run Calibration: Use NXP's DDR Test Tool or SCFW DDR Config Tool with ISSI-specific stress tests. Start at 1600MHz, gradually increase to 2000MHz while monitoring eye diagrams. If using U-Boot/Linux, update the device tree (.dtb) with correct timings (e.g., mx8mp-ddrc-devfreq.dtsi). Board-Level Checks: Ensure VDDQ = 1.1V, VDD2 = 0.6V, with clean decoupling (capacitors close to pins). Use a signal integrity simulator (e.g., HyperLynx) to verify traces. Test with lower temperatures or better cooling to rule out thermal throttling. If Still Fails: Contact NXP support via their community or ticket system — provide your calibration logs and board schematics. Consider switching to validated RAM like Micron MT53E512M32D2NP (NXP EVK default) for comparison. Overall, the RAM is compatible, but your 2000MHz failure is likely a setup issue. If you share more details (e.g., calibration logs or board schematic snippets), I can help troubleshoot further! I suggest contacting +8526583 (7594) via the messaging app; obtain the EOL document from him and then make a recommendation. He can help you Re: IMX8M PLUS LPDDR4 2G compatibility On the used board we have sucsesslully runing 3GB (MT53E768M32D2ZW-046 WTC) and 4GB (MT53E1G32D2FW-046 AAT:B) Micron LPDDR4 on 2000MHz. Re: IMX8M PLUS LPDDR4 2G compatibility Thanks for your support. In Attachments i send you the configuration .xls and the test log. Re: IMX8M PLUS LPDDR4 2G compatibility Hello @pengyong_zhang , Same result with the config Tool V 13.1. Maybe our configuration is wrong for the IS43LQ32512A-046BLI? Can you provide the correct configuration (*.ds file)? Our hardware desing is a 1:1 copy of the eval board regarding the LPDDR4 interface.  Kind Regards Tobias Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye Please use the below link download our DDR Config Tool and run the ddr test wIth configure 2GB dram.  https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX B.R Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  Please use below setting run the DDR test. B.R Re: IMX8M PLUS LPDDR4 2G compatibility Thanks for your Config Exaple. Its the same I already tryed with this RAM and still get the error. Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  It's strange. Please share your DDR Config Tool v25.12 fail log B.R Re: IMX8M PLUS LPDDR4 2G compatibility hHi @pengyong_zhang  for stresstest we use the Mscale DDR Tool 3.31. I will do it with the other config tool Re: IMX8M PLUS LPDDR4 2G compatibility Hello @pengyong_zhang , here is the log of the stresstest. We have the same Problem wirth an 4GB ISSI IS43LQ32K01S2A-046BLI.  Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  Did you run the stress test with our DDR Config Tool? From your log file, it seems not from the Config Tool output. Also use out latest tool version v25.12. B.R Re: IMX8M PLUS LPDDR4 2G compatibility Hello @pengyong_zhang , I run the tes in the config tool and and its passed. So it seems to be a tool problem with the MSCALER tool. Many thanks for your great support!
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eIQ and MCUXpresso SDK 26.03 with VSCode There are some items to be aware of when using eIQ projects in VSCode with MCUXpresso SDK 26.03 Debugger hangs when debugging eIQ examples on i.MX RT700 in VSCode There are two work-arounds available: 1) Use a JLink to debug the project instead of the default CMSIS-DAP interface. To do this: Install LinkServer Put a jumper on JP20 on the i.MX RT700 EVK, Update the MCULink firmware to use JLink by running C:\NXP\LinkServer_25.12.83\MCU-LINK_installer\scripts\program_JLINK.cmd Take off the jumper on JP20.  2) Alternatively update the linker file in the eIQ project:  Open the MIMXRT798Sxxxx_cm33_core0_flash.ld linker file in Repository->mcusdk->examples->_boards->mimxrt700evk->eiq_examples->tflm_label_image->cm33_core0->gcc  (use the path based on the eIQ project name that you are trying to use) In that linker file go to line 198 to 203 and replace the .ncache section with the code below:   .npu_ncache (NOLOAD) :   {       KEEP(*(.npu_ncache_data))       KEEP(*(.npu_ncache_data*))   } > m_ncache   ASSERT(. < 0x20580000, "Error: .npu_ncache cannot go beyond SRAM P18")   .ncache (NOLOAD) :   {     *(NonCacheable)     . = ALIGN(4);     __noncachedata_end__ = .;     /* define a global symbol at ncache data end */   } > m_ncache i.MX RT700 eIQ HiFi4 and HiFi1 projects cannot be imported or compiled in VSCode or command line GCC. In VSCode use the "Repository" import option. To compile the projects you must install Xtensa Xplorer, the RT700 license, and RT700 NewLib DSP Configuration file. Then add the following environmental variables: XCC_DIR=/ /XtDevTools/install/tools/RI-2023.11-win32/XtensaTools XTENSA_CORE=rt700_hifi4_RI23_11_nlib The project can then be compiled with command-line GCC with: west build -p always --sysbuild examples/eiq_examples/tflm_cifar10_hifi4/cm --toolchain armgcc --config flash_debug -b mimxrt700evk -Dcore_id=cm33_core0 Note that if using HiFi1 projects then XTENSA_CORE should be set to rt700_hifi1_RI23_11_nlib Also an additional compile option called -mlongcalls needs to be used to avoid issues when adding additional operators the ops list. Inside \mcuxsdk\examples\_boards\mimxrt700evk\eiq_examples\tflm_cifar10_hifi4\hifi4 edit the reconfig.cmake file in the mcux_add_xtensa_configuration options: mcux_add_xtensa_configuration( CC "-DXOS_CLOCK_FREQ=237500000 -std=c99 -mlongcalls" CX "-stdlib=libc++ \ -mlongcalls \ -std=c++17" ) A warning message comes up in eIQ Neutron SDK 3.1.2 If using eIQ Neutron SDK 3.1.2 then the follow warning will appear on the serial terminal during the model initialization: Unable to save model handle, call neutronModelUnprepare() when done This warning is not relevant for Neutron C devices like RT700 and MCX N and can be ignored as it does not impact inference time or accuracy. It will be fixed in the next eIQ Neutron SDK release. Some eIQ files that are commonly modified are shared among all eIQ examples For example, the Neutron libraries are shared among all eIQ examples. This can cause version compatibility issues with the default eIQ examples if the eIQ Neutron libraries are updated with eIQ Neutron SDK. This is because the eIQ projects in MCUXPresso SDK were converted using Neutron Converter 3.0.0 and the Neutron libraries in the SDK are shared among all eIQ projects.  To work around this, either revert the Neutron libraries back to version 3.0.0 or else download a separate repository to use the default eIQ examples. 
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s32k3 eMIOS IMP 模式 你好、 我目前正试图在 s32k3 微型计算机上使用 eMIOS IPM 模式读取输入信号频率。在等待状态寄存器告诉我它已捕获测量值后,我先读取 A 寄存器,然后读取 B 寄存器,并对两种情况(正常情况和溢出情况)执行周期计算。但是,计算结果给出的是"High Time" 或"Low time" ,而不是信号的周期。看来IPM模式给我的是高/低占空比,而不是周期。有什么好办法解决这个问题吗?我已确认控制寄存器使用了正确的模式。 谢谢! Re: s32k3 eMIOS IMP Mode @VaneB你好, ,我也遇到了类似的问题,你能分享一下我如何配置 EMIOS 来测量频率吗? Re: s32k3 eMIOS IMP Mode 你好@jfranklin 如果可能的话,能否与我们分享一下您的配置? Re: s32k3 eMIOS IMP Mode 你好,这是我们自己的软件。我们的目标是不使用提供的图形界面。基本上,我只是想读取频率输入的周期。尽管 IPM 模式应该只在上升沿或下降沿更新,但它似乎在上升沿和下降沿都更新。 Re: s32k3 eMIOS IMP Mode 你好@jfranklin 您使用的是 RTD 控制器还是定制软件?能否提供有关您申请的更多信息? BR、VaneB
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ICODE SLI tag returns a 64 01 error for a write_single_block command I'm using a Windows 11 laptop and and ACS ACR1552 reader.  I'm using the ACS Script Tool (v5.02) to send APDUs to a NXP ICODE SLI tag. I'm creating a transparent session, setting the protocol to 15693/Layer3, and then using transparent exchange encapsulation to the send the APDUs to the tag. GET_SYSTEM_INFO and READ_SINGLE_BLOCK seems to work OK. WRITE_SINGLE_BLOCK returns a "64 01" error but does appear to actually write the data. I have not been able to find any info on the meaning or cause of this 64 01 response. Can anyone shed some light on this? Here's the sequence of APDUs I'm working with. APDU #4 reads block 0 data as 11 22 33 44 APDU #5 writes block 0 data to 12 34 56 78  -  yet gets a 64 01 error APDU #6 reads block 0 data as 12 34 56 78  -  which shows the previous write actually worked? ; (1) establish transparent session < FF C2 00 00 02 81 00 00 > C0 03 00 90 00 90 00 ; (2) transparent exchange - switch protocol to SwitchProtocolRf::ISO15693 SwitchProtocolLayer::PART3 < FF C2 00 02 04 8F 02 02 03 > C0 03 00 90 00 8F 01 00 90 00 ; (3) get sys info < FF C2 00 01 04 95 02 02 2B 00 > C0 03 00 90 00 92 01 00 96 02 00 00 97 0F 00 0F 2E 98 5C 8A 00 01 04 E0 00 00 1B 03 01 90 00 ; (4) read user block 0 with security status < FF C2 00 01 05 95 03 42 20 00 00 > C0 03 00 90 00 92 01 00 96 02 00 00 97 06 00 00 00 11 22 33 90 00 ; (5) write block 0 with 12 34 56 78 < FF C2 00 01 09 95 07 02 21 00 12 34 56 78 00 > C0 03 01 64 01 90 00 ; (6) read user block 0 with security status < FF C2 00 01 05 95 03 42 20 00 00 > C0 03 00 90 00 92 01 00 96 02 00 00 97 06 00 00 12 34 56 78 90 00 ; (7) end transparent session < FF C2 00 00 02 82 00 00 > C0 03 00 90 00 90 00 Re: ICODE SLI tag returns a 64 01 error for a write_single_block command I had this exact same issue reading/writing icode SLIX/SLIX2 tags, the writes were working but giving the 64 01 timeout.  I was able to solve the problem by adjusting the timeout for the command by including the timer option within the same transaction as the write. Example: Write "00 01 02 03" to block 0 > ff c2 00 01 10 5f 46 04 40 42 0f 00 95 07 02 21 00 00 01 02 03 00 Transparent command Size of command (0x10 = 16 bytes to follow) Timeout command Command To Device As can be seen, the response is now correct. This command is basically the same as shown in the original poster's question, with the addition of the green section, which is, per the docs setting a 1sec timeout (which is probably way excessive). 5f 46 = Timer Data Object 04 = Length 40 42 0f 00 = 1,000,000 (microseconds, LSB first), i.e. 000f4240h = 1,000,000 Probably too late to be useful for the original poster, but maybe this will save someone else the 2-3 hours it cost me. Re: ICODE SLI tag returns a 64 01 error for a write_single_block command Thanks  @jimmychan.  Yes I’ve seen that list of error codes and descriptions, including the 6401.     I’m trying to understand what can cause that error given the APDU sequence I included in my original post.      Do you know reasons the tag wouldn’t respond to a write single block command to user memory?  An example I’ve thought  about is possibly the write operation takes longer than the reader is waiting for.  I’ve experimented with trying to configure the reader to wait longer but so far I haven’t been able to get this to resolve the issue.  Also, I don’t see any reference to this in the SLI or DNA spec sheets so I doubtful this is the issue.     Again, any help in understanding why the tag wouldn’t respond would be much appreciated.    Thanks - Drew Re: ICODE SLI tag returns a 64 01 error for a write_single_block command You could check the reference manual REF-ACR1552U-Series-1.06.pdf. page 43. Re: ICODE SLI tag returns a 64 01 error for a write_single_block command Hi @jimmychan - I have read the documentation for the reader, that's how I got the command syntax I'm using. As far as I can tell I have the command syntax correct. Are you saying the 6401 error is coming from the reader? Do you have any specific area of the documentation that I should look into? I appreciate your help. Drew Re: ICODE SLI tag returns a 64 01 error for a write_single_block command Please read the document of the reader. ACR1552U - USB NFC Reader IV | ACS
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Getting Started with FRDM-A-S32K312 Using Model-Based Design Toolbox (MBDT) Table of Contents 1. Introduction 2. Requirements 2.1 Software Required 2.2 Hardware Required 3. NXP Account Login 4. Installation 4.1 PEmicro Driver Installation 4.2 FreeMASTER Installation 4.3 MATLAB® Installation 4.4 MATLAB® Add-Ons Installation 4.5 MBDT for S32K3 v1.8.0 Installation 5. Running a Demo from the MBDT Examples for S32K3 6. Running a Motor Control Demo using MBDT 7. Conclusion 1. Introduction This article aims to help new users prepare and install the necessary software and hardware to use the FRDM Automotive S32K312 with the latest  Model-Based Design Toolbox for S32K3 version 1.8.0. Note: These steps can also be followed with any NXP Evaluation Board from the supported list referenced in the toolbox documentation. S32K312MINI‑EVB Renamed to FRDM‑A‑S32K312: Now part of the FRDM Automotive Ecosystem under its new name, the board keeps the same hardware and adds full ecosystem compatibility for flexible, scalable development.     2. Requirements   2.1 Software Required MATLAB® R2023b or later, with the following Add-ons: AUTOSAR Blockset Embedded Coder Support Package for ARM Cortex-M Processors Motor Control Blockset NXP_Support_Package_S32K3 Stateflow NXP Model-Based Design Toolbox for S32K3 version 1.8.0 FreeMASTER Run-Time Debugging Tool PEmicro Hardware Interface Drivers   2.2 Hardware Required FRDM-A-S32K312 Development Board MCSPTE1AK344 Motor Control Kit, which includes: Sunrise motor  DEVKIT-MOTORGD  12V power supply USB Type-C cable   3. NXP Account Login Open Software Licensing: Support, make sure you are logged into your NXP Account, and select: Click on My NXP Account. Select Software Licensing and Support. Then click on View accounts: These steps will ensure that you are properly authenticated with your NXP Account before proceeding with step 4.5 MBDT for S32K3 v1.8.0 Installation. Keep the page open for the login to persist.   4. Installation Note: Before proceeding, make sure you have full access to your PC or Laptop. Some installers require local admin rights. Contact your IT department to assist you with installation. 4.1 PEmicro Driver Installation After downloading the PEmicro Hardware Interface Drivers: Open the installer package and select the default Destination Folder: Click on Install and then wait for it to finish successfully. Connect the USB cable to your PC and the FRDM Automotive S32K312 board: Open Device Manager to check OpenSDA and the COM port number. OpenSDA - CDC Serial Port → note this COM port number: Note: The COM port number may differ on your system.   4.2 FreeMASTER Installation Download the  FreeMASTER Run-Time Debugging Tool: Open the installer FMASTERSW32.exe Click Next, then select all available products: Use the default installation path: C:\NXP\FreeMASTER 3.2 Wait for the installation to complete.   4.3 MATLAB® Installation First, check whether MATLAB® R2023b or later is already installed. If so, you can skip this section. For this tutorial, MATLAB® R2025b is downloaded from MathWorks®: Download the matlab_R2025b_Windows.exe (246 MB) file. A MathWorks® Account login is required. After signing in, select the installation directory; the default is C:\Program Files\MATLAB\R2025b For minimum requirements, install the following products: MATLAB® Simulink® AUTOSAR Blockset Embedded Coder MATLAB® Coder Motor Control Blockset Simulink® Coder Stateflow By default, Select All is enabled during install: Wait for the installation to finish. After installation, open MATLAB® and change the default Add-ons path to a shorter path such as C:\MathWorks .   4.4 MATLAB® Add-Ons Installation Open Add-On Explorer and install: Embedded Coder Support Package for ARM Cortex-M Processors NXP Support Package for S32K3 (NXP_Support_Package_S32K3)   4.5 MBDT for S32K3 v1.8.0 Installation After installing the support package, run the following command in MATLAB®: sp_s32k3.nxp.setup(); Select version 1.8.0; the installer will check prerequisites: If any toolboxes are missing, install them before continuing. Click Download to proceed. The Download button opens the Software Terms and Conditions dialog; if the page is not loading properly, follow the steps in 3. NXP Account Login. After reading, click I Agree. Download the SW32_MBDT_S32K3_1.8.0_D2512.mltbx file (approx. 1.6 GB): Once the download completes, browse to the location of the SW32_MBDT_S32K3_1.8.0_D2512.zip file: Click Install to proceed and accept the license agreement. After a few minutes, the dialog will display: Installation successfully completed! Click Next. Select an option such as Open S32K3 Root Folder. MATLAB®'s current folder will change to the root of the toolbox. Click Finish to close the installer. The current folder in MATLAB® is now C:\MathWorks\Toolboxes\NXP_MBDToolbox_S32K3 :   5. Running a Demo from the MBDT Examples for S32K3 Navigate to C:\MathWorks\Toolboxes\NXP_MBDToolbox_S32K3\S32K3_Examples\demos\s32k3xx_uart_leds_s32ct Open the model s32k3xx_uart_leds_s32ct.mdl . Click on Hardware Settings: Go to Hardware Board Settings → Hardware → Select Configuration Project Template: For the FRDM-A-S32K312 select Custom: S32K312MINI-EVB S32 Config Tool. A Warning Dialog will appear; click OK. Wait for the configuration update to complete. Click on Apply and close the Configuration Parameters window. Press Build, Deploy & Start (CTRL+B) to generate the code: After the build completes successfully, the executable is downloaded to the board. Open a terminal application and connect to the board's COM port at 115200 baud: Pressing r, g, or b on the keyboard toggles the corresponding RGB LED on the board.   6. Running a Motor Control Demo using MBDT Navigate to C:\MathWorks\Toolboxes\NXP_MBDToolbox_S32K3\S32K3_Examples\mc\PMSM Open the folder s32k312_mc_pmsm_2sh_s32ct : Open the model s32k312_mc_pmsm_2sh_s32ct.mdl : Press Build, Deploy & Start (CTRL+B) to generate the code. After the executable file is downloaded to the board: Disconnect the FRDM-A-S32K312 board from the PC. Insert the DEVKIT-MOTORGD on top of the FRDM-A-S32K312, ensuring proper pin alignment. Plug in the 12V power supply to the DEVKIT-MOTORGD. Reconnect the USB Type-C cable to the FRDM-A-S32K312.  The RGB LED and User Buttons are on the top side, the Reset Button is on the left side, while the 12V power, Motor Phases, and USB Type-C are on the right side.    Open FreeMASTER s32k312_mc_pmsm_2sh_s32ct.pmpx : Press GO to connect at 115200 baud. In the App Control tab, press On and set Speed Required to 1000 RPM: Apply a small mechanical load to the motor (friction force to the motor shaft) and observe the iABC currents. Here is a short video with the steps above explained: (function() { var wrapper = document.getElementById('lia-vid-6397308123112w960h540r525'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos)   7. Conclusion These steps conclude the Getting Started with FRDM Automotive S32K312 using the Model-Based Design Toolbox guide. For more details, refer to: s32k312_mc_pmsm_2sh_s32ct_example_readme.html The corresponding example_readme.html for the selected model. Thank you for your time, Stefan V.
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S32K148锁死 S32K148 MCU用J-LINK错刷Flash,再用J-LINK链接发生如下错误,JLINK unsecured已没用,怎么解决? Connecting ... - Connecting via USB to probe/ programmer device 0 - Probe/ Programmer firmware: J-Link V9 compiled Dec 13 2022 11:14:50 - Probe/ Programmer S/N: 25994751 - Device "S32K148" selected. - Target interface speed: 50 kHz (Fixed) - VTarget = 3.301V - ConfigTargetSettings() start - ConfigTargetSettings() end - Took 305us - InitTarget() start - SWD selected. Executing JTAG -> SWD switching sequence. - Protection bytes in flash at addr. 0x400 - 0x40F indicate that readout protection is set. For debugger connection the device needs to be unsecured. Note: Unsecuring will trigger a mass erase of the internal flash. - Executing default behavior previously saved in the registry. - Device will be unsecured now. - Timeout while unsecuring device. Erase never stops. - InitTarget() end - Took 2.17s - Found SW-DP with ID 0x2BA01477 - DPv0 detected - CoreSight SoC-400 or earlier - Scanning AP map to find all available APs - AP[2]: Stopped AP scan as end of AP map has been reached - AP[0]: AHB-AP (IDR: 0x24770011, ADDR: 0x00000000) - AP[1]: JTAG-AP (IDR: 0x001C0000, ADDR: 0x01000000) - Iterating through AP map to find AHB-AP to use - AP[0]: Skipped. Could not read CPUID register - AP[1]: Skipped. Not an AHB-AP - Attach to CPU failed. Executing connect under reset. Re: S32K148锁死 Hi@dongkuili 首先不见得保证能恢复,因为加密段被你写入了错误持续值,可能并不支持mass erase擦除 可以阅读该文档6. S32K1xx系列MCU芯片锁死(lockup)现象 https://mp.weixin.qq.com/s?__biz=MzI0MDk0ODcxMw==&mid=2247485716&idx=1&sn=979631aa2385a4e3c7651ee75ee252b4&chksm=e9124d92de65c484f1cfec7de451958cfd5cf818c46a4f71a7d3dd8a522af229c5a18aad58ff&scene=21#wechat_redirect Re: S32K148锁死 Hi@dongkuili 这和你使用什么软件没关系,按照文章中说的,直接去测试reset管脚的波形来判断是否可能被恢复,不能的话就不要再浪费你的时间了。 Re: S32K148锁死 谢谢回复 仔细看了链接文档和芯片手册,多次尝试还是无法通过mass erase恢复,想用S32FlashTool_v2.3.4,但不支持S32K148,有支持S32K148的S32FlashTool吗?
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S32 Design Studio debug watch register? How  to watch the register change or not, in S32 Design Studio? Re: S32 Design Studio debug watch register? Hello, my S32DS Peripheral Registers  why is the right-click option grayed out in my interface Re: S32 Design Studio debug watch register? Thank your very much. Re: S32 Design Studio debug watch register? Hello, Which S32 Design Studio are you using and which version? What NXP device are you developing your application for? The answer to your question may vary some depending on the answers to these questions. Also, we have many HOWTO articles for each of our S32 Design Studio editions. Please check the articles posted to this community as the topics covered may help to answer your questions. Best Regards, Mike Re: S32 Design Studio debug watch register?  Can you tell me how to download the program to MCU  with  S32 Design Studio ,    and  how to make sure download is successful ? Thanks. Re: S32 Design Studio debug watch register? Hello, To setup the watch register, first start a debug session, then go to the Peripherals view and right-click on the desired register and select 'Watch Registers(s)'. Next, go to the Watch registers view and see the values change within the register as you step through the code. Best Regards, Mike
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S32K148 locked up S32K148 MCU use J-LINK to brush flash by mistake, then use J-LINK link to get the following error, JLINK unsecured is useless, how to solve it? Connecting ... - Connecting via USB to probe/ programmer device 0 - Probe/ Programmer firmware: J-Link V9 compiled Dec 13 2022 11:14:50 - Probe/ Programmer S/N: 25994751 - Device "S32K148 " selected. - Target interface speed: 50 kHz (Fixed) - VTarget = 3.301V - ConfigTargetSettings() start - ConfigTargetSettings() end - Took 305us - InitTarget() start - SWD selected. Executing JTAG - > SWD switching sequence. - Protection bytes in flash at addr. 0x400 - 0x40F indicate that readout protection is set. For debugger connection the device needs to be unsecured. Note: Unsecuring will trigger a mass erase of the internal flash. - Executing default behavior previously saved in the registry. - Device will be unsecured now. - Timeout while unsecuring device. Erase never stops. - InitTarget() end - Took 2.17s - Found SW-DP with ID 0x2BA01477 - DPv0 detected - CoreSight SoC-400 or earlier - Scanning AP map to find all available APs - AP[2]: Stopped AP scan as end of AP map has been reached - AP[0]: AHB-AP (IDR: 0x24770011, ADDR: 0x00000000) - AP[1]: JTAG-AP (IDR: 0x001C0000, ADDR: 0x01000000) - Iterating through AP map to find AHB-AP to use - AP[0]: Skipped. Could not read CPUID register - AP[1]: Skipped. not an AHB-AP - Attach to CPU failed. Executing connect under reset. Re: S32K148锁死 Hi@dongkuili First of all, there is no guarantee that it will be recovered, because the encrypted segment you wrote the wrong persistence value to may not support mass erase erasure. You can read the document 6. S32K1xx series MCU chip lockup (lockup) phenomenon https://mp.weixin.qq.com/s?__biz=MzI0MDk0ODcxMw== &mid=2247485716 &idx=1 &sn=979631aa2385a4e3c7651ee75ee252b4 &chksm= e9124d92de65c484f1cfec7de451958cfd5cf818c46a4f71a7d3dd8a522af229c5a18aad58ff &scene=21#wechat_redirect Re: S32K148锁死 Thanks for the reply. I read the linked documents and the chip manual carefully, and I still can't recover by mass erase after several attempts. I want to use S32FlashTool_v2.3.4, but it doesn't support S32K148, is there any S32FlashTool that supports S32K148? Re: S32K148锁死 Hi@dongkuili It has nothing to do with what software you are using, follow what the article says and go straight to testing the waveform of the RESET pin to determine if it might be recovered, if not then don't waste your time.
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用于非 PSA 操作的 MbedTLS3 和 CAAM 驱动程序 亲爱的各位 我们根据 mbedTLS 2 的弃用说明,更新了 mbedTLS3。我们发现恩智浦有两个 mbedTLS 存储库。 (ver 2.x deprecated) https://github.com/nxp-mcuxpresso/mbedtls (ver 3.x) https://github.com/NXP/nxp_mbedtls 我们通过阅读 sdk 使用的 yaml 文件找到了它 - 我们想知道,如果我们选择 ver 3x,而不使用 PSA API,是否会降低性能? 版本 2 通过 port/ksdk 提供了一组替代函数,可用于将加密操作委托给 CAAM 驱动程序,如 ksdk_mbedtls: https://github.com/nxp-mcuxpresso/mbedtls/blob/release/25.06.00/port/ksdk/ksdk_mbedtls.c 我们通过 fsl_caam 使用原始 CAAM 驱动程序进行 aes256 加密,我们想使用 mbedtls 来生成一对 ecdsa 密钥。我们的目标是拥有 mbedTLS3 并将所有可能的工作委托给 CAAM 硬件 ——如果有人知道应用笔记/端口已经完成,或者知道如何设计这样的指南,那就太好了。 感谢您的支持 🙂 Re: MbedTLS3 and CAAM driver for Non-PSA operations 还有一个小信息,我们正在使用 imxrt1176 并在其上安装了 FreeRTOS,我们是否正确读取了 mbedtls_ksdk.c 中的端口? 672 - 674 https://github.com/nxp-mcuxpresso/mbedtls/blob/release/25.06.00/port/ksdk/ksdk_mbedtls.c #endif /* MBEDTLS_THREADING_C */ if (ctx->mode == MBEDTLS_DES_ENCRYPT) { status = CAAM_DES_EncryptEcb(CAAM_INSTANCE,&s_caamHandle, input, output, 8, key); 这个端口使用阻塞操作吗?这样,其他 FreeRTOS 线程就会被阻断 - 我们发现在 mbedtls 的 freertos 示例中使用了这个端口,所以这对我们来说是个惊喜 Re: MbedTLS3 and CAAM driver for Non-PSA operations 您好, SDK 中似乎有 mbedtls 和 mebedtls 3.x,如下所示,还有 CAAM(加密加速和保障模块)示例。 https://mcuxpresso.nxp.com/mcuxsdk/latest/html/examples/driver_examples/caam/readme.html https://mcuxpresso.nxp.com/mcuxsdk/latest/html/examples/mbedtls3x_examples/index.html https://mcuxpresso.nxp.com/mcuxsdk/latest/html/examples/mbedtls_examples/index.html 是的,这是一个阻塞操作。
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基于 RT1170 通过 USB DFU 更新固件 基于 RT1170 通过 USB DFU 更新固件 基于 RT1170 通过 USB DFU 更新固件 开发环境 准备dfu-util 准备dfu-util 的步骤 运行演示 使用 SDK 中的预建固件 使用自定义固件 无需借助外部编程工具即可在现场执行微控制器 (MCU) 固件升级是一项必要的功能。 对于支持 USB 设备控制器的 MCU,USB 设备固件更新 (DFU) 类提供了一种解决方案。USB_DFU 引导加载程序只需要一台 PC 和一根 USB 电缆。 RT系列也提供了此功能。以 RT1170 为例,SDK 中 USB 类下提供了一个 DFU 项目。该项目基于 MCUXpresso IDE。通过运行 SDK 中的 dev_dfu_freertos_cm7 项目,RT1170 将被枚举为 dfu 设备,并且在通过另一根 USB 电缆将其连接到主机 PC 后,用户可以使用“dfu-util”实用程序将固件下载到该设备。 开发环境 软件环境: SDK版本:2.15.000 IDE: MCUXpresso IDE 演示项目: dev_dfu_freertos_cm7 主机软件: dfu-util 下载链接: dfu-util 对于 Windows 64 位:下载dfu-util-0.9-win64.zip   硬件环境: 主板:RT1170-EVKB   Preparing dfu-util dfu-util用于将固件下载到 DFU 设备,但它不会将 CRC32 添加到固件中。由于 SDK 中的 DFU demo 会验证 CRC32,以确保写入 Flash 的固件没有位错误,因此需要修改dfu-util源代码。 准备dfu-util 的步骤 安装依赖项 sudo apt-get build-dep libusb-1.0-0 dfu-util sudo apt-get 安装 gcc-mingw-w64-x86-64 下载dfu-util和libusb源代码 git克隆https://git.code.sf.net/p/dfu-util/dfu-util git 克隆https://github.com/libusb/libusb.git 修改源代码中的 CRC 代码 修改dfu_file.c中的dfu_store_file函数,将CRC32添加到Firmware后缀。 /* 如果有后缀,则写入 */ 如果(写入后缀){ uint8_t dfusuffix[DFU_SUFFIX_LENGTH]; dfusuffix[0] = 文件->bcdDevice & 0xff; dfusuffix[1] = 文件->bcdDevice >> 8; dfusuffix[2] = 文件->idProduct & 0xff; dfusuffix[3] = 文件->idProduct >> 8; dfusuffix[4] = 文件->idVendor & 0xff; dfusuffix[5] = 文件->idVendor >> 8; dfusuffix[6] = 文件->bcdDFU & 0xff; dfusuffix[7] = 文件->bcdDFU >> 8; dfusuffix[8] = 'U'; dfusuffix[9] = 'F'; dfusuffix[10] = 'D'; dfusuffix[11] = DFU_SUFFIX_LENGTH; /*crc = dfu_file_write_crc(f, crc, dfusuffix, DFU_SUFFIX_LENGTH - 4);*/ dfusuffix[12] = crc; dfusuffix[13] = crc >> 8; dfusuffix[14] = crc >> 16; dfusuffix[15] = crc >> 24; crc = dfu_file_write_crc(f,crc,dfusuffix + 12, 4); }   构建libusb mkdir -p构建 cd libusb-1.0.24 ./autogen.sh PKG_CONFIG_PATH=$PWD/../build/lib/pkgconfig./configure --host=x86_64-w64-mingw32 --prefix=$PWD/../build 制作 进行安装 光盘 .. Build dfu-util cd dfu-util-0.11 ./autogen.sh PKG_CONFIG_PATH=$PWD/../build/lib/pkgconfig./configure --host=x86_64-w64-mingw32 --prefix=$PWD/../build 制作 进行安装 光盘 .. 完成这些步骤后,新构建的工具将位于/build/bin文件夹中。 打开 Windows 的 cmd。使用新的dfu-suffix.exe运行以下命令,CRC32 将添加到固件中。 dfu-suffix.1 exe -a你的固件 运行演示 使用 SDK 中的预建固件 SDK 提供了一个预编译的固件二进制文件 ( dev_hid_mouse_bm.bin ),其中已包含 CRC32 校验码。请按以下步骤操作: 使用 MCUXpresso IDE 将dev_dfu_freertos_cm7演示刷入 EVKB 板。   通过 USB 将开发板连接到主机 PC。 在 USB 设备描述符中,我们找到供应商 ID 和产品 ID:   运行以下命令下载固件: dfu-util.exe -d <你的视频:进程号> -D <你的固件> 下载后,DFU 演示将验证 CRC32 并在 RAM 中执行新的固件。该设备将被枚举为 USB 鼠标,在屏幕上以矩形图案移动。 使用自定义固件 使用自定义固件时,请确保图像加载到正确的地址(例如,0x10000)。如果偏移量不正确,即使 CRC 校验通过,DFU 演示也将无法加载固件。 构建和加载自定义固件: 将hello_world_cm7项目导入 MCUXpresso IDE。 在托管链接器脚本设置中,启用“将应用程序链接到 RAM”。 调整内存设置以匹配 DFU 项目要求,确保 ITCM 是第一个 RAM 区域。 构建项目并生成二进制文件。 使用修改后的dfu-util工具将 CRC32 附加到二进制文件并将其下载到开发板。验证自定义固件是否正确执行。 CRC 添加: 新固件加载成功: 中文版及演示版请见此链接: https://www.nxpic.org.cn/module/forum/forum.php?mod=viewthread&tid=803149&fromuid=3253523 动手实践培训
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Hello NPU! Running a TFLite model on i.MX 9 The following is a guide on training a simple model in Pytorch and Tensorflow and deploying it on an application using the i.MX93 Ethos-65 Neural Processing Unit (NPU). After following this guide you will accomplish: Training a simple CNN on the MNIST dataset Convert the model to tflite, quantize it and compile it for the i.MX93 NPU (Ethos-65). Run a simple application where a digit can be drawn and identified by our model. Prerequisites To follow this guide you will need: Yocto image, GTKMM3 support is needed for the C++ example, for the python example a pre-built image can be used. An i.MX93 board Running Python example The application implementation is provided in both Python and C++, if using the python application, pre-built full image can be used instead, simply copy the python scripts to the target and execute as follows: # Running quantized example on the CPU ./run.py -m cnn_tf_quant.tflite # Running example on the Ethos NPU ./run.py -m cnn_tf_quant_vela.tflite -d /usr/lib/liblitert_ethosu_delegate.so Pre-built models are provided in the attachment however steps and scripts used to train and generate the models are also included (see below). Building image with GTKMM3 support (C++ example only) The GUI application used for demonstration has been written in GTKMM3 (C++ wrapper of the GTK library) therefore an image with GTKMM3 support is needed, luckily there is already a recipe we can use to easily integrate this into our yocto image. To build the image simply follow the instructions in the Yocto User's guide, as of the time of this writing the latest BSP is 6.12.49_2.2.0 so we will use that. Once you have setup all the requirements in your host and installed repo, you can setup your build enviroment as follows: repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-walnascar -m imx-6.12.49-2.2.0.xml repo sync Depending on your target you can now setup your build directory, we will use wayland graphics with X11 support, and the iMX93 Freedom board as example: DISTRO=fsl-imx-xwayland MACHINE=imx93-11x11-lpddr4x-frdm source imx-setup-release.sh -b 93-frdm-xwayland Simply select the MACHINE configuration that matches your board. Now we're almost ready to start the build, we still need to add GTKMM3 support to our image, simply modify your local.conf file under conf/local.conf and add the following: IMAGE_INSTALL:append = " gtkmm3" Make sure the space in front of gtkmm3 is there to avoid issues on the build. Since the build is very resource intensive out of memory issues can arise during the build, to limit the amount of concurrent recipes attempted to build at once it is recommended to add the following as well: BB_NUMBER_THREADS="8" PARALLEL_MAKE="-j8" BB_PRESSURE_MAX_CPU ?= "50000" BB_PRESSURE_MAX_IO ?= "100000" BB_PRESSURE_MAX_MEMORY ?= "25000" After this your local.conf should look similar to this:  NOTE: Make sure to have plenty of storage available on your machine since the build requires upwards of 500GB to complete. The build can now start, if you want to build the GTKMM application from source it is required to have an available SDK create it as follows: bitbake imx-image-full -c populate_sdk And to create the image simply do: bitbake imx-image-full We require the full image since it contains all the Tensorflow Lite libraries and different examples. After the build completes the toolchain can be installed and the image flashed onto the board. To install the toolchain: ./tmp/deploy/sdk/fsl-imx-xwayland-glibc-x86_64-imx-image-full-armv8a-imx93-11x11-lpddr4x-frdm-toolchain-6.12-walnascar.sh And afterwards every time you want to use the toolchain: source /opt/fsl-imx-xwayland/6.12-walnascar-full-gtkmm3/environment-setup-armv8a-poky-linux To flash the image to an SD card: zstdcat imx-image-full-imx93-11x11-lpddr4x-frdm.rootfs.wic.zst | sudo dd of=/dev/mmcblk0 bs=1M conv=fsync And now you are ready to build the application, train some models and deploy them. Building the GTKMM3 application (C++) The source for the application can be found here, a prebuilt binary is also provided and attached here.  The application contains a drawing area where one can simply draw a digit with the mouse or touch display, and two buttons one to clear the drawing area and one to trigger the execution of the model and predict the digit. To build from scratch CMake is required, as well as a toolchain with support for GTKMM3 (see above), the following steps can be followed to build the project: sudo apt install cmake git clone https://github.com/ManRod2982/drawing_window_imx cd drawing_window_imx/drawing_window_cpp/ source /opt/fsl-imx-xwayland/6.12-walnascar-full-gtkmm3/environment-setup-armv8a-poky-linux cmake -B build -DCMAKE_TOOLCHAIN_FILE=$OECORE_NATIVE_SYSROOT/usr/share/cmake/OEToolchainConfig.cmake cmake --build build After this a binary called window will be created under the build directory, now it can be simply copied to the target SD card. If using linux the filesystem will be mounted, so you can simply copy the binary to the root directory: sudo cp build/window /media/user/root/root/ SCP can also be used if a connection to the board is already established: scp build/window [email protected]:/root And after this on the target the application can be started as follows: ./window -m model_path [optional] -d delegate_path [optional] -v Three parameters are accepted by the application: Path to the model: -m or --model_path [Optional] Path to the delegate if any: -d or --delegate_path, if none is provided the model will be attempted to be run on the CPU using the XNN delegate [Optional] Verbosity flag, if present the model will output more information Now we need a model to run. Training a simple CNN model Looking at the Machine Learning User's guide for this release. The following is the support for the different frameworks with respect to the available compute engines in each device: Tensorflow Lite and LiteRT (latest release of Tensorflow Lite and the only one moving forward) are the frameworks that are widely supported for most compute engines in the i.MX9 family, this guide will use Tensorflow lite since the example uses C++ and the current release of LiteRT only supports Python, however the interface and process it's pretty much the same. Setting up the environment The example repository contains different python scripts used to train the models and convert them to the tflite format. In order to follow the next steps a python3 installation is necessary. It is recommended to setup a virtual environment: python3 -m venv myenv source myenv/bin/activate pip install -r requirements.txt This will install all the required packages for both Tensorflow and Pytorch. Training a model with Tensorflow Tensorflow allows an straightforward path to quantize and convert the model to Tensorflow Lite, our Convolutional Neural Network (CNN) architecture looks as follows: model = tf.keras.models.Sequential([ tf.keras.layers.Input(batch_shape=(1, 28, 28, 1)), tf.keras.layers.Conv2D(16, 5, padding='same', activation='relu'), tf.keras.layers.Conv2D(32, 3, activation='relu'), tf.keras.layers.Dropout(0.2), tf.keras.layers.MaxPool2D(2, strides=(2,2)), tf.keras.layers.Flatten(), tf.keras.layers.Dense(100, activation='relu'), tf.keras.layers.Dropout(0.2), tf.keras.layers.Dense(10, activation='softmax') ]) We can train the model by running the script train_tf.py, it takes around 2min to train on a normal laptop and achieves 99.05% accuracy on the test dataset. For details on the framework please refer to the official Tensorflow documentation. After running the script we can visualize our model using the eIQ toolkit model visualizer or the Netron.app: The i.MX93 features an ARM Ethos-65 NPU which requires the weights, biases and inputs to be integers and our current model uses float32, therefore we need to quantize the model, to achieve this we can run tf2quant_tflite.py which will quantize the model and convert it to tflite: Which we can now see takes integer inputs and outputs, the weights and biases have also been quantized and we can easily see the difference in size of the files: The quantized model is 555kB whereas the float32 model is 2.2MB, since float32 requires 4 bytes to store each weight and bias, whereas the quantized model requires only one byte. You now have a model than can be used on the target, however as it is right now it will be run on the CPU using the XNN delegate, to run the model simply do: ./window -m cnn_tf_quant.tflite We can now compile our quantized model for the ARM Ethos NPU. The eIQ toolkit will be used. Open the model through the model tool: Navigate to the folder with your quantized model, cnn_tf_quant.tflite in this case and open it, you should be able to visualize the model, now we can click on the options menu to select convert: We select the i.MX93 converter, we will prompted to select the destination folder as well: After selecting the destination folder if all goes well the conversion finalizes and we should be able to visualize the model optimized to be run on the Ethos, any operations not supported by the NPU will be shown and carried out by the CPU, in the case of this simple example all the operations are carried out by the NPU: And we can now run the model on the target as follows: ./window -m cnn_tf_quant_vela.tflite -d /usr/lib/libethosu_delegate.so Training a model with Pytorch The repository contains a sample model using Convolutional Neural Networks to train on the MNIST data set, the model structure is as follows: NeuralNetwork( (cnn): Sequential( (0): Conv2d(1, 16, kernel_size=(5, 5), stride=(1, 1), padding=(2, 2)) (1): ReLU() (2): Conv2d(16, 32, kernel_size=(3, 3), stride=(1, 1)) (3): ReLU() (4): Dropout(p=0.2, inplace=False) (5): MaxPool2d(kernel_size=2, stride=2, padding=0, dilation=1, ceil_mode=False) (6): Flatten(start_dim=1, end_dim=-1) (7): Linear(in_features=5408, out_features=100, bias=True) (8): ReLU() (9): Dropout(p=0.2, inplace=False) (10): Linear(in_features=100, out_features=10, bias=True) ) ) Pytorch models can be easily converted to Tensorflow lite (without quantization) to be run on the CPU, as well as the Open Neural Network Exchange  model (ONNX) however Executorch has recently been released, which is an inference model for pytorch models on embedded devices, support for it is currently in the works. The Pytorch model is defined under pytorch_model.py: #!/usr/bin/env python3 import torch from torch import nn # Define model class NeuralNetwork(nn.Module): def __init__(self): super().__init__() self.cnn = nn.Sequential( # Input 28x28x1, after padding 32x32x1, output 28x28x16 nn.Conv2d(in_channels=1, out_channels=16, kernel_size=5, padding=2), nn.ReLU(), # Input 28x28x16, output 26x26x32 nn.Conv2d(in_channels=16, out_channels=32, kernel_size=3), nn.ReLU(), nn.Dropout(p=0.2), # Input 26x26x32, output 13x13x32 nn.MaxPool2d(kernel_size=2, stride=2), nn.Flatten(), nn.Linear(13*13*32, 100), nn.ReLU(), nn.Dropout(p=0.2), nn.Linear(100, 10) ) def forward(self, x): logits = self.cnn(x) return logits  And the training is carried out by executing train_pytorch.py, the training achieves 99.3% accuracy on the test dataset and it takes around 7 min to complete on a normal laptop. For details on the framework itself and the training process refer to the official pytorch documentation. The pytorch model is then saved under pytorch_model.pth however pytorch does not save the graph information only the weights and biases, if we visualize the saved model on netron or the eIQ toolkit model visualizer we can observe the disconnected weight and biases: To better visualize our model we can simply convert it to the ONNX format by using the script pytorch2onnx.py, and now we can visualize the graph of our model on Neutron: NOTE: ONNX might also provide a way to quantize and convert the quantized model to tflite however in my tests of onnx-tf the tool seemed to be out of sync with the latest Tensorflow framewok, it was easier to create a similar model on Tensorflow and then quantize and export. We can now export our model to tflite, since the model is not quantized it will be run on the CPU (XNN delegate), to export it we run pytorch2tflite.py and we can now visualize the exported model: And we can run this model on the target as follows: ./window -m pytorch_cnn.tflite Deploying and running the model We now have an application where we can draw the digits, a model capable of detecting those digits, but our application needs to be able to execute that model and get the results, this is our next step. In order to be able to run the model on the target we need to: Load the model Create a tflite interpreter Load external delegates if any Allocate the tensors C++ example A minimal example is provided here, however it doesn't include the loading of the external delegate, which we will need in order to be able to run our model on the NPU. The required headers are the following: #include "tensorflow/lite/delegates/external/external_delegate.h" #include "tensorflow/lite/interpreter.h" #include "tensorflow/lite/interpreter_builder.h" #include "tensorflow/lite/kernels/register.h" #include "tensorflow/lite/model_builder.h" We can now load our model as follows using the TFLite API: std::unique_ptr<:flatbuffermodel> model = tflite::FlatBufferModel::BuildFromFile(model_path); An interpreter needs to be created now, for this an operation resolver is needed as well as our model: tflite::ops::builtin::BuiltinOpResolver resolver; std::unique_ptr<:interpreter> interpreter; tflite::InterpreterBuilder(*model, resolver)(&interpreter);  If a delegate is required we now need to create it and update our execution graph so that the interpreter knows to call the delegate on the supported operations: // Create external delegate option and pass the delegate library TfLiteExternalDelegateOptions external_delegate_options = TfLiteExternalDelegateOptionsDefault(delegate_path); // Create the External Delegate. This will load the delegate. TfLiteDelegate *external_delegate = TfLiteExternalDelegateCreate(&external_delegate_options); // Add External Delegate into TFLite Interpreter to automatically delegate nodes. if (interpreter->ModifyGraphWithDelegate(external_delegate) != kTfLiteOk) { std::cerr << "Failed to add delegate" << std::endl; } We can now allocate the tensors for our model: // Allocate tensors for the model if (interpreter->AllocateTensors() != kTfLiteOk) { std::cerr << "Failed to allocate tensors" << std::endl; } And at this point we are ready to run the inference using our model! The last step is to fill the input buffers with our data, invoke the interpreter and retrieve the results from the output buffer, in the following example with a float model: // Fill input buffers // Note: The buffer of the input tensor with index `i` of type T can // be accessed with `T* input = interpreter->typed_input_tensor (i);` float *input_tensor = interpreter->typed_input_tensor (0); std::memcpy(input_tensor, input.data(), input.size() * sizeof(float)); // Run inference if (interpreter->Invoke() != kTfLiteOk) { std::cerr << "Failed to invoke Interpreter!" << std::endl; return {}; } // Read output buffers // Note: The buffer of the output tensor with index `i` of type T can // be accessed with `T* output = interpreter->typed_output_tensor (i);` float *output_tensor = interpreter->typed_output_tensor (0); std::memcpy(output, output_tensor, output.size() * sizeof(float)); In our example application the interpreter creating and inference calling is wrapped in a class called NnModel, it's implementation can be seen on the repository but it can handle both the float models and int8 models without any modification. The class is instantiated inside the main routine and the inference is called every time the predict button is clicked. // Create model with parsed parameters NnModel nn(model_path, delegate_path, verbose); void Window::on_predict_clicked() { // Save screen to file std::cout << "Predict clicked!" << std::endl; // Call inference on NnModel depending on the type // the model expects int number; auto data_type = nn_.get_dtype(); switch (data_type) { case kTfLiteFloat32: { std::vector drawing = mouse_drawing.export_to_vector (28, 28, 255.0); std::vector output_vec_f = nn_.infer (drawing); number = get_max_index (output_vec_f); break; } case kTfLiteInt8: { std::vector drawing = mouse_drawing.export_to_vector (28, 28, 255.0); std::vector output_vec_int = nn_.infer (drawing); number = get_max_index (output_vec_int); break; } default: std::cerr << "Cannot handle input type: " << std::to_string(data_type) << std::endl; break; } std::string display = "You drew a: " + std::to_string(number); std::cout << display << std::endl; text_view.set_text(display); } Python example The process for creating an interpreter in Python is pretty similar, we still need to load a delegate if any is used and load the model as well as allocate the tensors. In this example LiteRT is used instead however the API remains the same, the only change needed is where the interpreted is imported from. The following minimal code can be used to load the model and any external delegates: from ai_edge_litert.interpreter import Interpreter # Create interpreter if delegate_path is not None: # attempt to load external delegate if provided (platform specific) try: from ai_edge_litert.interpreter import load_delegate delegate = load_delegate(delegate_path) self.interpreter = Interpreter(model_path=model_path, experimental_delegates=[delegate]) except Exception as e: raise RuntimeError(f"Failed to load delegate: {e}") else: self.interpreter = Interpreter(model_path=model_path) self.interpreter.allocate_tensors() We now have an interpreter we can use, we just need to fill the input tensors, invoke the interpreter and retrieve the output tensors with the results from our model: # Set input input_details = self.interpreter.get_input_details()[0] self.interpreter.set_tensor(input_details['index'], input_data) # Run inference self.interpreter.invoke() # Get results out_details = self.interpreter.get_output_details()[0] output_data = self.interpreter.get_tensor(out_details['index']) These steps are contained in a wrapper class under nn_model.py.  Benchmarking the models A prebuilt benchmarking tool is provided in the release it generates random inputs and measures the time it takes to run the inference on the model, the following are the results running the different models on the i.MX93: ./benchmaark_model --graph=model --num_threads=num_cores   CPU 1 core CPU 2 cores NPU pytorch_cnn.tflite 1559.61 us 1023.22 us NA cnn_tf_quant.tflite 585.37 us 379.69 us NA cnn_tf_quant_vela.tflite NA NA 221.84 us This is of course a toy example but it can be observed how running on the dedicated hardware provides a significant improvement on inference speed. The following is a guide on training a simple model in Pytorch and Tensorflow and deploying it on an application using the i.MX93 Ethos-65 Neural Processing Unit (NPU) and the i.MX95 eIQ Neutron NPU.
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i.MX8MP 添加 HD3SS3220 Type-C 导致 LAN 唤醒失败 我正在开发 6.12.34 内核并修改内核设备树 imx8mp-evk.dts。 nxp-imx/imx-Manifest:i.MX 版本清单 (imx-linux-wal nascar) 当按如下方式在设备树中添加 hd3s3220 type-c 控制器时,WOL 失败了。 /{ connector { compatible = "usb-c-connector"; label = "USB-C"; data-role = "dual"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hs_ep: endpoint { remote-endpoint = <&usb3_hs_ep>; }; }; port@1 { reg = <1>; ss_ep: endpoint { remote-endpoint = <&hd3ss3220_in_ep>; }; }; }; }; }; &iomux { pinctrl_hd3ss3220: hd3ss3220grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x140 >; }; }; &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; hd3ss3220@67 { compatible = "ti,hd3ss3220"; reg = <0x67>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hd3ss3220>; interrupt-parent = <&gpio5>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hd3ss3220_in_ep: endpoint { remote-endpoint = <&ss_ep>; }; }; port@1 { reg = <1>; hd3ss3220_out_ep: endpoint { remote-endpoint = <&usb3_role_switch>; }; }; }; }; }; &usb_dwc3_1 { dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; usb-role-switch; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb3_hs_ep: endpoint { remote-endpoint = <&hs_ep>; }; }; port@1 { reg = <1>; usb3_role_switch: endpoint { remote-endpoint = <&hd3ss3220_out_ep>; }; }; }; }; 调用挂起命令后,WOL 功能失败。 根据我的检查,唤醒功能是受支持的 root@imx8mpevk:~# ethtool -s eth0 wol g root@imx8mpevk:~# ethtool eth0 Settings for eth0: Supported ports: [ TP MII ] Supported link modes: 10baseT/Full 100baseT/Full 1000baseT/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: Yes Supported FEC modes: Not reported Advertised link modes: 10baseT/Full 100baseT/Full 1000baseT/Full Advertised pause frame use: Symmetric Receive-only Advertised auto-negotiation: Yes Advertised FEC modes: Not reported Link partner advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Full Link partner advertised pause frame use: Symmetric Link partner advertised auto-negotiation: Yes Link partner advertised FEC modes: Not reported Speed: 1000Mb/s Duplex: Full Auto-negotiation: on master-slave cfg: preferred slave master-slave status: slave Port: Twisted Pair PHYAD: 1 Transceiver: external MDI-X: Unknown Supports Wake-on: ug Wake-on: g Current message level: 0x0000003f (63) drv probe link timer ifdown ifup Link detected: yes root@imx8mpevk:~# dmesg | grep -i wake [ 3.148381] imx-dwmac 30bf0000.ethernet: Wake-Up On Lan supported [ 13.933830] stmmac: wakeup enable root@imx8mpevk:~# cat /sys/class/net/eth0/device/power/wakeup enabled 但是 6.6.52 内核(imx-linux- scarthgap)上同样的设备树设置效果很好!! 谁能帮帮我? i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Re: i.MX8MP adding HD3SS3220 Type-C cause Wake on LAN failed 你好, 请尝试在 dts 中使用IRQ_TYPE_EDGE_FALLING。 致敬, Zhiming Re: i.MX8MP adding HD3SS3220 Type-C cause Wake on LAN failed 虽然将中断信号改为"IRQ_TYPE_EDGE_FALLING" ,但唤醒功能仍然不起作用。 目前,通过以下设置,唤醒功能运行良好。 / { connector { compatible = "usb-c-connector"; label = "USB-C"; data-role = "dual"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hs_ep: endpoint { remote-endpoint = <&usb3_hs_ep>; }; }; port@1 { reg = <1>; ss_ep: endpoint { remote-endpoint = <&hd3ss3220_in_ep>; }; }; }; }; }; &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; hd3ss3220@67 { compatible = "ti,hd3ss3220"; reg = <0x67>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hd3ss3220>; interrupt-parent = <&gpio5>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; wakeup-source; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hd3ss3220_in_ep: endpoint { remote-endpoint = <&ss_ep>; }; }; port@1 { reg = <1>; hd3ss3220_out_ep: endpoint { remote-endpoint = <&usb3_role_switch>; }; }; }; }; }; &iomux { pinctrl_hd3ss3220: hd3ss3220grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x140 // USB_SW_INTn (AH20) >; }; }; &usb3_phy1 { fsl,phy-tx-preemp-amp-tune-microamp = <1800>; fsl,phy-tx-vref-tune-percent = <116>; status = "okay"; }; &usb3_1 { status = "okay"; }; &usb_dwc3_1 { dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; usb-role-switch; role-switch-default-mode = "host"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb3_hs_ep: endpoint { remote-endpoint = <&hs_ep>; }; }; port@1 { reg = <1>; usb3_role_switch: endpoint { remote-endpoint = <&hd3ss3220_out_ep>; }; }; }; }; 但如你所见,连接器的状态被设置为"disabled" ,这是为什么呢? 删除这一行后,唤醒功能就失效了。 Re: i.MX8MP adding HD3SS3220 Type-C cause Wake on LAN failed 嗨 @AlanWen 我个人认为,这个问题可能与内核通用元器件的升级有关,不应归因于 i.MX 相关的驱动程序。由于我没有相同的硬件平台,所以无法准确找出问题所在。 致敬, Zhiming Re: i.MX8MP adding HD3SS3220 Type-C cause Wake on LAN failed 但在 6.6.52 内核版本中,使用相同的设置,在没有连接器状态行的情况下,唤醒功能也能正常工作。 如下所示: / { connector { compatible = "usb-c-connector"; label = "USB-C"; data-role = "dual"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hs_ep: endpoint { remote-endpoint = <&usb3_hs_ep>; }; }; port@1 { reg = <1>; ss_ep: endpoint { remote-endpoint = <&hd3ss3220_in_ep>; }; }; }; }; }; &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; hd3ss3220@67 { compatible = "ti,hd3ss3220"; reg = <0x67>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hd3ss3220>; interrupt-parent = <&gpio5>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; wakeup-source; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hd3ss3220_in_ep: endpoint { remote-endpoint = <&ss_ep>; }; }; port@1 { reg = <1>; hd3ss3220_out_ep: endpoint { remote-endpoint = <&usb3_role_switch>; }; }; }; }; }; &iomux { pinctrl_hd3ss3220: hd3ss3220grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x140 // USB_SW_INTn (AH20) >; }; }; &usb3_phy1 { fsl,phy-tx-preemp-amp-tune-microamp = <1800>; fsl,phy-tx-vref-tune-percent = <116>; status = "okay"; }; &usb3_1 { status = "okay"; }; &usb_dwc3_1 { dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; usb-role-switch; role-switch-default-mode = "host"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb3_hs_ep: endpoint { remote-endpoint = <&hs_ep>; }; }; port@1 { reg = <1>; usb3_role_switch: endpoint { remote-endpoint = <&hd3ss3220_out_ep>; }; }; }; };
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LS1046ARDB DDR 校准 作为一个教程项目,我尝试在 ls1046ardb 板上使用 CodeWarrior 工具用上市并通过 DDR 校准。 我创建了一个 QoriQ 配置项目->LS1046A->DDR 内存控制器控制器配置。 成功读取 mta18adf2g72az-3g2r1 模块的 SPD。之后我用上市了 " Centering the clock 测试 "。 第一阶段顺利通过: #################### Result for: wrlvl_searcher ###### Run 1 ###################################### 测试结果:[ ============================================================ 已更新:WRLVL_CNTL = 0x86550605,WRLVL_CNTL_2 = 0x00000000,WRLVL_CNTL_3 = 0x00000000,SDRAM_CLK_CNTL = 0x02800000 ============================================================ Updated:WRLVL_CNTL = 0x86550608, WRLVL_CNTL_2 = 0x0A0B0C0F, WRLVL_CNTL_3 = 0x100A0B0D, SDRAM_CLK_CNTL = 0x02800000 ============================================================ Updated:WRLVL_CNTL = 0x86550608, WRLVL_CNTL_2 = 0x0A0B0C0F, WRLVL_CNTL_3 = 0x1012130D, SDRAM_CLK_CNTL = 0x02800000 <> 呃......捕获寄存器: 0xE20、0x00000000 0xE24、0x00000000 0xE28、0x00000000 0xE40、0x00000000 0xE44、0x00000000 0xE48、0x0000001D 0xE4C、0x00000000 0xE50、0x00000000 0xE54、0x00000000 0xE58、0x000000000 0xE58、0x 00010000 转储: 0xF00, 0x00000000 0xF04, 0x00000002 0xF08, 0x0000000A 0xF0C, 0x14000C20 0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000 0xF20、0x00000000 0xF24, 0x3B003E00 0xF28, 0x41004200 0xF2C, 0x4A004D00 0xF30, 0x4E005100 0xF34, 0x45007000 0xF38, 0x00000000 0xF3C, 0x00000000 0xF40、0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0xD4000000 0xF50, 0x11001400 0xF54, 0x16001800 0xF58, 0x1F002100 0xF5C, 0x24002700 0xF60、0x1A000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000 0xF70, 0x0060007B 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000 0xF80、0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000 0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x2A002B00 0xFA0、0x2D002C00 0xFA4, 0x2E002D00 0xFA8, 0x2A002E00 0xFAC, 0x2D000000 0xFB0, 0x00000003 0xFB4, 0x1E1B1A1C 0xFB8, 0x1D1B1C1A 0xFBC, 0x1E1C1B1D 0xFC0、0x1D1C1D1A 0xFC4, 0x1E1C1D1E 0xFC8, 0x1B1D1E1C 0xFCC, 0x1E1C1B1D 0xFD0, 0x1C1A1D1B 0xFD4, 0x1F1D1C1E 0xFD8, 0x1D1E1D1B 0xFDC, 0x1E1E1B1E 0xFE0、0x1D1F1D1C 0xFE4, 0x1E1C1A1D 0xFE8, 0x1D1D1C19 0xFEC, 0x1F1E1D20 0xFF0, 0x1D1E1F1D 0xFF4, 0x1E1D1B1E 0xFF8, 0x1D1E1E1C 0xFFC, 0x1F000000 数据: 0x00000008 0x0000000a 0x0000000b 0x0000000c 0x0000000f 0x00000010 0x00000012 0x00000013 0x0000000d ] 但下一阶段(clk_adj)失败: #################### Result for: wrc ###### Run 1 ################################################# 测试结果:[ < > {{DDR initialization failed: D_INIT was not cleared by hardware!}} 呃......捕获寄存器: 0xE20、0x00000000 0xE24、0x00000000 0xE28、0x00000000 0xE40、0x00000080 0xE44、0x00000000 0xE48、0x0000001D 0xE4C、0x00000000 0xE50、0x00000000 0xE54、0x00000000 0xE58、0x 00010000 转储: 0xF00, 0x00000000 0xF04, 0x00002100 0xF08, 0x0000000A 0xF0C, 0x14000C20 0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000 0xF20、0x00000000 0xF24, 0x10101010 0xF28, 0x10101010 0xF2C, 0x10101010 0xF30, 0x10101010 0xF34, 0x10104000 0xF38, 0x00000000 0xF3C, 0x00000000 0xF40、0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0x11000000 0xF50, 0x00000000 0xF54, 0x00000000 0xF58, 0x00000000 0xF5C, 0x00000000 0xF60、0x00000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000 0xF70, 0x0060007B 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000 0xF80、0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000 0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x00000000 0xFA0、0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000 0xFB0, 0x00000000 0xFB4, 0x00000000 0xFB8, 0x00000000 0xFBC, 0x00000000 0xFC0、0x00000000 0xFC4, 0x00000000 0xFC8, 0x00000000 0xFCC, 0x00000000 0xFD0, 0x00000000 0xFD4, 0x00000000 0xFD8, 0x00000000 0xFDC, 0x00000000 0xFE0, 0x00000000 0xFE4, 0x00000000 0xFE8, 0x00000000 0xFEC, 0x00000000 0xFF0, 0x00000000 0xFF4, 0x00000000 0xFF8, 0x00000000 0xFFC, 0x00000000 ] 假设校准是在全新的、完全组装的参考 ls1046ardb 板上进行的,而不是在定制主板上进行的,那可能有什么问题。 Re: ls1046ardb ddr calibration 你好 能否分享问题的截图? Re: ls1046ardb ddr calibration 我创建了一个新的 DDR 配置项目。将 SYSCLOCK 更改为 100 Mhz。 之后,我阅读了模块的 SPD。已成功读取 SPD。 CodeWarrior 所描述的 DDR 的 DQ 映射: 之后我启动校准。第一阶段顺利通过: 下一阶段(时钟调整)失败: 在失败阶段的日志中,我 起初我以为 DQ 映射出错了,但现在看来映射是正确的,否则第一阶段也会失败。 对这种情况有什么建议吗? Re: ls1046ardb ddr calibration 您的板能够使用预编译映像在主机上启动和打印 u-boot 日志吗?还请您分享一下日志。 Re: ls1046ardb ddr calibration 不幸的是,我现在无法提供来自 uboot 的日志(在纽约假期之后是可能的),但我可以说 Uboot 和 Linux 一切都很好 —— 它们在我的 ls1046ardb 上启动和运行得非常完美。唯一的问题是 DDR 校准过程失败。 Re: ls1046ardb ddr calibration 日安 继续进行 ls1046ardb 失败的 DDR 校准。 这是成功的 uboot 日志: 这是 linux 启动日志: 可以看出,Uboot和Linux的正常启动。我认为这意味着硬件和 DDR 模块一切正常,但 DDR 校准过程仍在上述相同步骤中失败。 Re: ls1046ardb ddr calibration 板按预期启动,因此 ddr 已正确校准,问题可能与使用该工具时的测试配置错误有关。 Re: ls1046ardb ddr calibration 日安奥斯瓦格 请说明测试配置中可能存在哪些错误? 让我展示一下我在做什么: 我的 CodeWarrior 版本 1) 首先我创建一个 DDR 配置项目并从 RDB 板读取 SPD 数据: 2) 成功读取 SPD 后,我将项目默认系统时钟从 66.7 Mhz 改为 100 Mhz 3) 在这里,我们可以看到完整的项目设置:   4) 测试设置: 5) 之后,我开始测试: 第一次测试成功通过。 下一次测试(CLK_ADJ)失败,结果如下: 那么问题出在哪里呢? Re: ls1046ardb ddr calibration 使用适用于 Windows 的 CodeWarrior 开发工作室可以解决这个问题。Windows 版本要比 Linux 下的二手垃圾喷气机好用得多。
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关于 S32K314 上 "Adc_Sar_Ip_DoCalibration "函数初始化失败的问题 使用的微控制器是 S32K314,使用的 SDK 版本是 5.0.0 ADC 时钟源频率为 160MHz,使用 " 元器件 " 组件。 我想在初始化后对 ADC 执行自校准,但功能反馈全部失败。 错误位置已在此处找到,这不是超时问题。 我想知道解决方案是什么,ADC 自校准失败的原因可能是什么? Re: Regarding the issue of failed initialization of the “Adc_Sar_Ip_DoCalibration” function on S32K3 在自校准失败的情况下,采样值会变小并偶尔波动。这种现象是否与自校准失败相对应?而当电压值小于某一特定值(如 0.5V 左右)时,采样值为 4 或 5(满刻度为 16383)。
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imx95 电源模式 我正在开发一款运行 Linux 6.12(基于 Yocto)的自定义 i.MX95 板。我遇到了与 USB3 主机控制器有关的挂起到内存(深度睡眠)故障。当执行 echo mem> /sys/power/state 时,系统会中止 xhci-hcd 的挂起:WARN: xHC CMD_RUN 超时,紧接着 PM: failed to suspend async: error -110.启用 USB 主机模式时,即使没有活动的 USB 流量,问题也会持续出现。我使用的是由 GPIO 控制的固定 5V VBUS 稳压器,USB3 控制器、PHY、时钟和功率域在 DTS(附后)中定义。我的要求是在低电源模式下完全关闭 USB VBUS 的电源,同时允许系统成功进入深度睡眠。我附上了完整的暂停/恢复 dmesg 日志和与 USB 相关的相关 DTS 节点以供参考。我希望得到指导,了解在 i.MX95 上避免 xHCI 挂起超时所需的正确 DTS 和/或驱动程序处理方法。 Re: imx95 low power mode 您能否向我们分享详细步骤,以便我们在 EVK 板上复现它?谢谢 Re: imx95 low power mode 在自定义板中我使用 fusb302 但未作为 usb3.0 启用,我们将其用作 usb2.0。 但在进入深度睡眠时(echo mem> /sys/power/state ),xhci-hcd 驱动程序出现错误。 测试设置: • SoC:i.MX95 • 操作系统:Yocto Linux(内核 6.x、电路板支持包) • USB 模式:主机(xHCI、USB3)• 连接设备:USB 闪存盘(大容量存储) 正常启动板。 将 USB 存储设备连接到 USB3 主机端口。 使用 lsusb 验证枚举并确认设备可访问。 使用以下命令进入电源模式: echo mem > /sys/power/state 在此步骤本身之后它会显示错误。 使用配置的唤醒源(电源按钮/ GPIO)恢复系统。 恢复后,观察到 USB 设备是: 未检测到,或 在 dmesg 中显示 xHCI / DWC3 相关错误,或 需要重新插入 USB 才能重新工作。 ERROR LOGS : echo mem> /sys/power/state [ 117.057281] PM: suspend entry (deep) [ 117.066009] Filesystems sync:0.005 seconds [ 117.071209] Freezing user space processes [ 117.076800] Freezing user space processes completed (elapsed 0.001 seconds) [ 117.083781] OOM killer disabled. [117.087011] 冻结剩余的可冻结任务 [117.132725] 冻结剩余已完成的可冻结任务(已经 0.041 秒) [117.140164] printk:暂停主机(使用 no_console_suspend 调试) [117.156868] sd 0:0:0:0:0:[sda] 同步 SCSI 缓存 [117.267552] xhci52-hcd xhci-hcd.2.auto:警告:xHC CMD_RUN 超时 [117.267611] xhci-hcd xhci-hcd.2.auto:PM:dpm_run_callback ():platform_pm_suspend 返回 -110 [117.267631] xhci-hcd xhci-hcd.2.auto:无法暂停异步:-110 [117.267702] 下午:一些 设备无法挂起,或者检测到提前唤醒事件 [117.268017] hub 1-0:1.0:hub_ext_port_status 失败(错误 = -108) [117.268044] USB usb1-port1:无法禁用(错误 = -108)[117.516365] 下午:恢复设备花了 0.248 秒 [117.570639] OOM 杀手已启用。 [ 117.573777] 重新启动任务......完成。 [ 117.575261] sd 0:0:0:0: [sda] 测试单元就绪失败:Result: hostbyte=0x01 driverbyte=DRIVER_OK [ 117.578423] random: crng reseeded on system resumption [ 117.587117] sda: detected capacity change from 120164352 to 0 [ 117.598136] PM: suspend exit -sh: echo: write error:连接超时 Re: imx95 low power mode 嗨@kannappan、 好了,我们要放元旦假期了。当我回到办公室时我会在我们的板上试一试然后给你回复。 祝您有美好的一天 顺祝商祺! Rita Re: imx95 low power mode 嗨@kannappan、 对不起,这周太忙了,我下周会为您测试并与您分享结果。 祝您有美好的一天 顺祝商祺! Rita Re: imx95 low power mode HI@Rita_Wang, 对于上述问题是否有任何答复。 谨致 Kannappan
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linux6.12+imx8mp内核报告Fixed dependency cycle(s) with xxx linux6.12+imx8mp内核启动时报告: [ 0.057737] /soc@0: 固定了与 /soc@0/bus@30000000/efuse@30350000/unique-id@8 的依赖循环 [ 0.058809] /soc@0/bus@32c00000/lcd-controller@32fc6000:修正了与 /soc@0/bus@32c00000/hdmi@32fd8000 的依赖循环 [ 0.058972] /soc@0/bus@32c00000/hdmi@32fd8000:修正了与 /soc@0/bus@32c00000/lcd-controller@32fc6000 的依赖循环 [ 0.059239] /soc@0/interrupt-controller@38800000: 修正了与 /soc@0/interrupt-controller@38800000 的依赖循环 [ 0.061960] /soc@0/bus@30000000/pinctrl@30330000: 修复了与 /soc@0/bus@30000000/pinctrl@30330000/miscgrp 的依赖循环 [ 0.061986] /soc@0/bus@30000000/pinctrl@30330000: Fixed dependency cycle(s) with /soc@0/bus@30000000/pinctrl@30330000/hoggrp [ 0.062566] imx8mp-pinctrl 30330000.pinctrl:initialized IMX pinctrl driver [ 0.063301] /soc@0/bus@30000000/efuse@30350000: Fixed dependency cycle(s) with /soc@0/bus@30000000/clock-controller@30380000 [ 0.064431] /soc@0/bus@30000000/efuse@30350000: Fixed dependency cycle(s) with /soc@0/bus@30000000/clock-controller@30380000 [ 0.065497] /soc@0/bus@30000000/clock-controller@30380000: 修正了与 /soc@0/interrupt-controller@38800000 的依赖循环 [ 0.074336] /soc@0/bus@32c00000/lcd-controller@32fc6000:修正了与 /soc@0/bus@32c00000/hdmi@32fd8000 的依赖循环 [ 0.074446] /soc@0/bus@32c00000/hdmi@32fd8000:修复了 /soc@0/bus@32c00000/lcd-controller@32fc6000 的依赖循环 [ 0.076363] /soc@0/bus@32c00000/lcd-controller@32fc6000:修正了与 /soc@0/bus@32c00000/hdmi@32fd8000 的依赖循环 [ 0.076855] /soc@0/bus@32c00000/lcd-controller@32fc6000:修正了与 /soc@0/bus@32c00000/hdmi@32fd8000 的依赖循环 [ 0.076990] /soc@0/bus@32c00000/hdmi@32fd8000:修正了与 /soc@0/bus@32c00000/lcd-controller@32fc6000 的依赖循环 原因是什么?需要处理吗? Re: linux6.12+imx8mp内核报告Fixed dependency cycle(s) with xxx Hi @machangbao  这是正常的,不用处理。 Best Regards, Zhiming Re: linux6.12+imx8mp内核报告Fixed dependency cycle(s) with xxx Hi @machangbao  这是内核上游引入得补丁,具体commit信息是: driver core: fw_devlink: Stop trying to optimize cycle detection logic commit bac3b10b78e54b7da3cede397258f75a2180609b upstream. In attempting to optimize fw_devlink runtime, I introduced numerous cycle detection bugs by foregoing cycle detection logic under specific conditions. Each fix has further narrowed the conditions for optimization. It's time to give up on these optimization attempts and just run the cycle detection logic every time fw_devlink tries to create a device link. The specific bug report that triggered this fix involved a supplier fwnode that never gets a device created for it. Instead, the supplier fwnode is represented by the device that corresponds to an ancestor fwnode. In this case, fw_devlink didn't do any cycle detection because the cycle detection logic is only run when a device link is created between the devices that correspond to the actual consumer and supplier fwnodes. With this change, fw_devlink will run cycle detection logic even when creating SYNC_STATE_ONLY proxy device links from a device that is an ancestor of a consumer fwnode. 6.12上面的fw_devlink框架相比以前更健壮,Fixed dependency cycle(s) with表示 fw_devlink 检测到环,并通过调整链接策略(例如降级某些 link 类型或不创建某些 link)来解决问题。这不是错误,而是信息提示,说明系统在启动时处理了潜在的死锁风险。 driver core: fw_devlink: Make cycle detection more robust fw_devlink could only detect a single and simple cycle because it relied mainly on device link cycle detection code that only checked for cycles between devices. The expectation was that the firmware wouldn't have complicated cycles and multiple cycles between devices. That expectation has been proven to be wrong. For example, fw_devlink could handle: +-+ +-+ |A+------> |B+ +-+ +++ ^ | | | +----------+ But it couldn't handle even something as "simple" as: +---------------------+ | | v | +-+ +-+ +++ |A+------> |B+------> |C| +-+ +++ +-+ ^ | | | +----------+ But firmware has even more complicated cycles like: +---------------------+ | | v | +-+ +---+ +++ +--+A+------>| B +-----> |C|<--+ | +-+ ++--+ +++ | | ^ | ^ | | | | | | | | | +---------+ +---------+ | | | +------------------------------+ And this is without including parent child dependencies or nodes in the cycle that are just firmware nodes that'll never have a struct device created for them. The proper way to treat these devices it to not force any probe ordering between them, while still enforce dependencies between node in the cycles (A, B and C) and their consumers. So this patch goes all out and just deals with all types of cycles. It does this by: 1. Following dependencies across device links, parent-child and fwnode links. 2. When it find cycles, it mark the device links and fwnode links as such instead of just deleting them or making the indistinguishable from proxy SYNC_STATE_ONLY device links. This way, when new nodes get added, we can immediately find and mark any new cycles whether the new node is a device or firmware node. Best Regards, Zhiming
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imx95 低電力モード 私は Linux 6.12 (Yocto ベース) を実行するカスタム i.MX95 ボードに取り組んでいます。USB3 ホスト コントローラに関連する RAM へのサスペンド (ディープ スリープ) 障害が発生しています。echo mem > /sys/power/state を実行すると、システムは xhci-hcd: WARN: xHC CMD_RUN タイムアウト、続いて PM: 非同期サスペンドに失敗しました: エラー -110 でサスペンドを中止します。USB ホスト モードが有効になっている場合、アクティブな USB トラフィックがない場合でも、この問題が継続的に発生します。私は GPIO によって制御される固定 5V VBUS レギュレータを使用しており、USB3 コントローラ、PHY、クロック、および電源ドメインは DTS (添付) で定義されています。私の要件は、システムが正常にディープスリープに入ることができるようにしながら、低電力モード中に USB VBUS の電源を完全にオフにすることです。参考までに、完全なサスペンド/再開 dmesg ログと関連する USB 関連の DTS ノードを添付しました。i.MX95 で xHCI サスペンド タイムアウトを回避するために必要な正しい DTS および/またはドライバ側の処理に関するガイダンスを希望します。 Re: imx95 low power mode CANを使ってEVKボードで再現するための詳細な手順を教えていただけますか?ありがとう Re: imx95 low power mode カスタム ボードでは fusb302 を使用していますが、usb3.0 としては有効になっていないため、usb2.0 として使用しています。 しかし、ディープスリープに入ると ( echo mem > /sys/power/state )、xhci-hcd ドライバでエラーが発生します。 テストのセットアップ: • SoC: i.MX95 • OS: Yocto Linux (カーネル 6.x、NXP BSP) • USBモード: ホスト (xHCI、USB3) • コネクテッドデバイス: USBフラッシュドライブ(大容量ストレージ) ボードを通常通り起動します。 USB ストレージ デバイスを USB3 ホスト ポートに接続します。 lsusb を使用して列挙を確認し、デバイスにアクセスできることを確認します。 次を使用して低電力モードに入ります: エコーメモリ > /sys/power/state このステップ自体の後にはエラーが表示されます。 設定されたウェイクアップ ソース (電源ボタン/ GPIO) を使用してシステムを再開します。 再開後、USB デバイスが次のいずれかの状態であることを確認します。 検出されない、または dmesgにxHCI / DWC3関連のエラーが表示される、または 再び動作させるには USB を再度差し込む必要があります。 エラーログ: エコーメモリ > /sys/power/state [ 117.057281] PM: 進入を一時停止(深部) [ 117.066009] ファイルシステムの同期: 0.005秒 [ 117.071209] ユーザー空間プロセスのフリーズ [ 117.076800] ユーザー空間プロセスの凍結が完了しました(経過時間 0.001秒) [ 117.083781] OOMキラーが無効になりました。 [ 117.087011] 残りの凍結可能なタスクを凍結しています [ 117.132725] 残りの凍結可能なタスクの凍結が完了しました(経過時間 0.041 秒) [ 117.140164] printk: コンソールを一時停止しています (デバッグするには no_console_suspend を使用してください) [ 117.156868] sd 0:0:0:0: [sda] SCSIキャッシュを同期しています [ 117.267552] xhci-hcd xhci-hcd.2.auto: 警告: xHC CMD_RUN タイムアウト [ 117.267611] xhci-hcd xhci-hcd.2.auto: PM: dpm_run_callback(): platform_pm_suspend は -110 を返します [ 117.267631] xhci-hcd xhci-hcd.2.auto: PM: 非同期サスペンドに失敗しました: エラー -110 [ 117.267702] PM: 一部のデバイスがサスペンドに失敗したか、早期ウェイクイベントが検出されました [ 117.268017] ハブ 1-0:1.0:hub_ext_port_status が失敗しました (err = -108) [ 117.268044] usb usb1-port1: 無効にできません (err = -108) [ 117.516365] PM: デバイスの再開に0.248秒かかりました [ 117.570639] OOMキラーが有効になりました。 [ 117.573777] タスクを再起動しています...完了しました。 [ 117.575261] sd 0:0:0:0: [sda] テストユニット準備失敗: 結果: ホストバイト=0x01 ドライババイト=DRIVER_OK [ 117.578423] ランダム: システム再開時にcrngが再シードされました [ 117.587117] sda: 容量が 120164352 から 0 に変更されたことを検出しました [ 117.598136] PM: 一時停止終了 -sh: echo: 書き込みエラー: 接続がタイムアウトしました Re: imx95 low power mode こんにちは@kannappanさん、 さて、元旦は休みになります。オフィスに戻ったら、ボードで試してみて、ご返答させていただきます。 良い一日をお過ごしください よろしくお願いいたします。 リタ Re: imx95 low power mode こんにちは@Rita_Wang 、 上記の問題に対する返答はありますか。 よろしくお願いします カンナパン Re: imx95 low power mode こんにちは@kannappanさん、 今週は忙しすぎて申し訳ありませんが、来週テストして結果を共有します。 良い一日をお過ごしください よろしくお願いいたします。 リタ
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无法将 S32K146EVB-Q144 板闪烁为 D1 发光的红色 我有一个 S32K146EVB-Q144 评估板,起初运行良好。 在我实施 Lin 栈的一次调试过程中,它停止工作了。 当我RESET控制器时,我看到 D1 上持续出现红灯,另外两个绿灯还在那里。 我在 2-3 号位置使用 J10 和 J107 选择 USB 电源,在 2-3 号位置使用 J104 选择 OpenSDA 应用程序闪存模式。 现在,S32DS 完全检测不到我的控制器。 我按照下面帖子中提到的步骤进行了尝试,症状似乎完全相同。 关于S32K144 D2 红色 LED 始终亮起 - NXP Community 在这里,我使用 P&E Kinetics 恢复工具在 OpenSDA 中停止了处理器,但仍无法闪存任何新应用程序。 即使实现了停止,我也无法再次闪光,红灯仍然亮着。 通过调整跳线 J104,控制器也能进入启动加载器模式,实际上我也能在其中闪存 ne 启动加载器应用程序。但不知何故,我无法再次写入闪存,如果我尝试闪存任何示例 .srec文件,D2 保持周期性闪烁(通常在成功闪烁时闪烁一次,然后应用程序开始运行)。 简而言之: -控制器无法到达主控制器或无法连续RESET -控制器无法再次写入闪存(可能是网络安全问题)。 除了涉及 SEGGER-JLINK 的技术外,我尝试了上述主题中提到的技术,因为我没有这种调试探针。我有一个 PE Multilink Universal,但它也无法恢复/擦除闪存。 以下是板的详细信息:主 板名称是:S32K146EVB-Q144 MicroBoot 内核版本为:1.08 引导 加载程序版本为:1.13 安装的应用程序: peMicro EVB-S32K144 海量存储/调试 应用程序 版本为:1.25 DUID 是: 39A33939-91818199-37539805-F97AE678 EUID 是:4141A238-1BDB8733-1854BA22-D38368D6 TUID 是: 74823938-47328196-8576CC9B-0242983E TOA 是 :86B6E505-56F042E0-79B2A114-62BA758F TOA2 是:86B6E505-EB1A8A7C-AF6E54B6-43532420 SUID 是:86B6E505-5BA18877-37239804-8003EC65 MCU 是否永久锁定? 如果不是,我该如何找回我的板? 我是否发现有任何硬件/软件故障?(仅供参考,D2 和 D3 发出绿光,我认为这意味着我的 5V 和 3.3V 电源轨工作正常) 是否有物理方法进行批量擦除?(无法使用 S32DS 紧急动力学选项,因为那里根本无法检测到板)。 OpenSDA 芯片的任何引脚接地都会导致闪存擦除吗? Re: Unable to flash S32K146EVB-Q144 board as D1 glowing red 请注意,在圣诞假期期间,我们的支持响应时间可能会比平时长。在某些情况下,您的请求可能会在新年后得到处理。感谢您的理解。 Re: Unable to flash S32K146EVB-Q144 board as D1 glowing red HI P&E恢复实用程序停止 MCU 后,关闭工具。 然后按照步骤 3 或 步骤 4 对 S32K146 重新编程。 我不确定这是否是由于 应用程序版本为: 1.25 .请按住 RESET 按钮 SW5,然后插入 USB 线并将 MS D-DEBUG-S32K146EVB-q144_pemicro_v121.sda 放入 BOOTLOADER 驱动器中。这将把 应用程序版本更新为 1.21。 我还附上了 lpit_periodic_interrupt_s32k146.srec。 顺便说一下,您不需要外接 Segger J-Link。如果按步骤 6 :插入 J7,同时按住 SW5,OpenSDA 就会进入 BOOTLOADER 模式。然后 将世纪佳缘 J-Link 应用程序固件 (如 OpenSDA_V1.bin然后,板载调试器将变为 J-Link。 祝好, Robin ------------------------------------------------------------------------------- 注: - 如果本帖回答了您的问题,请点击"ACCEPT AS SOLUTION" 按钮。谢谢! - 我们会在最后一次发帖后的 7 周内跟踪主题,之后的回复将被忽略 如果您以后有相关问题,请另开新主题,并参考已关闭的主题。 ------------------------------------------------------------------------------- Re: Unable to flash S32K146EVB-Q144 board as D1 glowing red 您好,Robin, ,感谢您的及时回复,我试着将其回滚到MSD-DEBUG-S32K146EVB-Q144_Pemicro_v121.SDA, ,其行为方式相同,启动加载器应用程序已闪烁,但 D1 仍闪烁红光,我无法闪烁 .srec使用 Kinetis 恢复工具停止运行后的文件。我看到控制器正在尝试闪烁 srec,但失败了,因为 D2 会周期性闪烁(通常只闪烁 3-4 次,应用程序就会被闪烁)。 然后,我尝试将引导加载器切换到OpenSDA_V1.bin,之后尝试使用 J-Link 指令器进行连接,结果看到以下日志 : SEGGER J-Link Commander V8.94 (Dec 10 2025 14:50:47 编译) DLL 版本 V8.94, Dec 10 2025 14:49:54 编译 通过 USB 连接 J-Link... 没问题 固件:J-Link OpenSDA 于 2023 年 1 月 31 日编译 13:42:36 硬件版本:V1.00 J-Link 正常运行时间(自启动以来):0d 00h 00m 28s S/N:621000000 vtref=3.300V 键入 " connect " 建立目标连接,'?'如需帮助 J-Link > connect 请指定设备/内核。 : S32K146 类型 '?'用于选择对话框 设备 > S32K146 请指定目标接口: J) JTAG(默认) S) SWD T) cjTag TIF > SWD SWD TIF SWD 指定目标接口速度 [kHz]。 : 4000 kHz 速度 > 100 设备 " S32K146 " 已选中。 通过 SWD 连接目标 ConfigTargetSettings() 开始 ConfigTargetSettings() 结束 - 用时 22us InitTarget() 开始 SWD 已选定。执行 JTAG -> SWD 切换序列。 停止 CPU 时超时。 InitTarget() end - Took 392ms 发现 SW-DP,ID 为 0x2BA01477 检测到 DPv0 CoreSight SoC-400 或更早版本 扫描 AP 映射以查找所有可用 AP AP[2]:由于已到达 AP 地图的尽头,因此停止 AP 扫描 AP[0]:AHB-AP (IDR: 0x24770011, ADDR: 0x00000000) AP[1]:JTAG-AP (IDR: 0x001C0000, ADDR: 0x01000000) 正在遍历 AP 映射以查找要使用的 AHB-AP, AP[0]:找到内核 AP[0]:AHB-AP ROM base:0xE00FF000 CPUID 寄存器:0x410FC241。实现者代码:0x41 (ARM) 找到了 Cortex-M4 r0p1,小端节序。 FPUnit:6 个代码 (BP) 插槽和 2 个文字插槽 CoreSIGHT 组件: romTBL [0] @ E00FF000 [0] [0]:E000E000 CID B105E00D PID 000BB00C SCS-M7 [0] [1]:E0001000 CID B105E00D 003BB002 PID DWT [0] [2]:E0002000 CID PID B105E00D 002BB003 FPB [0] [3]:D PID T PIU 正在初始化 126976 字节的工作内存 @ 0x1FFF0000 重置类型:正常 (https://kb.segger.com/J-Link_Reset_Strategies) E0000000 B105E00D 003BB001 E0040000 B105900D 000BB9A1 RESET:通过 DEMCR.VC_CORERESET RESET 后暂停内核。 RESET:通过 AIRCR.SYSRESETREQ 重置设备。 RESET:S_RESET_ST 永远不会被清除。CPU 似乎永远处于 RESET。 RESET:使用备用:重置密码。 RESET:通过 DEMCR.VC_CORERESET 重置后暂停内核。 RESET:通过重置引脚重置设备 RESET:VC_CORERESET 未停止 CPU。(调试逻辑也可以通过RESET引脚重置?)。 RESET:重新连接并手动关闭 CPU。 发现 ID 为 0x2ba01477 的 SW-DP DP v0 检测到 CoreSIGHT SoC-400 或更早版本的 AP 地图检测已跳过。 找到手动配置的 AP 映射。 AP[0]:AHB-AP (IDR: Not set, ADDR: 0x00000000) AP[0]:找到内核 AP[0]:AHB-AP ROM base:0xE00FF000 CPUID 寄存器:0x410FC241.实现者代码:0x41 (ARM) 找到了 Cortex-M4 r0p1,小端节序。 CPU 无法暂停 RESET:重置后核心未停机,尝试禁用 WDT。 RESET:通过 DEMCR.VC_CORERESET 重置后暂停内核。 RESET:通过RESET引脚RESET设备 RESET:VC_CORERESET 未停止 CPU。(调试逻辑也可以通过RESET引脚重置?)。 RESET:重新连接并手动关闭 CPU。 发现 ID 为 0x2ba01477 的 SW-DP DP v0 检测到 CoreSIGHT SoC-400 或更早版本的 AP 地图检测已跳过。 找到手动配置的 AP 映射。 AP[0]:AHB-AP (IDR: Not set, ADDR: 0x00000000) AP[0]:找到内核 AP[0]:AHB-AP ROM base:0xE00FF000 CPUID 寄存器:0x410FC241.实现者代码:0x41 (ARM) 找到了 Cortex-M4 r0p1,小端节序。 CPU 无法暂停 RESET:失败。切换RESET引脚并再次尝试RESET策略。 发现 ID 为 0x2BA01477 的 SW-DP 检测到 DPv0 CoreSight SoC-400 或更早版本 跳过 AP 映射检测。找到手动配置的 AP 映射。 AP[0]:AHB-AP (IDR: Not set, ADDR: 0x00000000) AP[0]:找到内核 AP[0]:AHB-AP ROM base:0xE00FF000 CPUID 寄存器:0x410FC241.实现者代码:0x41 (ARM) 找到了 Cortex-M4 r0p1,小端节序。 RESET:通过 DEMCR.VC_CORERESET RESET 后暂停内核。 RESET:通过 AIRCR.SYSRESETREQ 重置设备。 RESET:S_RESET_ST 永远不会被清除。CPU 似乎永远处于 RESET。 RESET:使用备用:RESET pin。 RESET:通过 DEMCR.VC_CORERESET RESET 后暂停内核。 RESET:通过重置引脚RESET设备 RESET:VC_CORERESET 未停止 CPU。(调试逻辑也可以通过RESET引脚重置?)。 RESET:重新连接并手动关闭 CPU。 发现 ID 为 0x2ba01477 的 SW-DP DP v0 检测到 CoreSIGHT SoC-400 或更早版本的 AP 地图检测已跳过。 找到手动配置的 AP 映射。 AP[0]:AHB-AP (IDR: Not set, ADDR: 0x00000000) AP[0]:找到内核 AP[0]:AHB-AP ROM base:0xE00FF000 CPUID 寄存器:0x410FC241.实现者代码:0x41 (ARM) 找到了 Cortex-M4 r0p1,小端节序。 CPU 无法暂停 RESET:重置后核心未停机,尝试禁用 WDT。 RESET:通过 DEMCR.VC_CORERESET 重置后暂停内核。 RESET:通过RESET引脚RESET设备 RESET:VC_CORERESET 未停止 CPU。(调试逻辑也可以通过RESET引脚重置?)。 RESET:重新连接并手动关闭 CPU。 发现 ID 为 0x2ba01477 的 SW-DP DP v0 检测到 CoreSIGHT SoC-400 或更早版本的 AP 地图检测已跳过。 找到手动配置的 AP 映射。 AP[0]:AHB-AP (IDR: Not set, ADDR: 0x00000000) AP[0]:找到内核 AP[0]:AHB-AP ROM base:0xE00FF000 CPUID 寄存器:0x410FC241.实现者代码:0x41 (ARM) 找到了 Cortex-M4 r0p1,小端节序。 CPU 无法停止运行 CPU 无法停止运行 CPU 无法停止运行 ****** Error:Failed to halt CPU. Memory zones: Zone:"默认" 说明:默认访问模式 Cortex-M4 已识别。 J-Link> Re: Unable to flash S32K146EVB-Q144 board as D1 glowing red 请使用示波器观察RESET引脚的波形,将波形发送给我,并告诉我RESET周期和高级宽度。在某些情况下,可能无法恢复,必须更换 S32K1 芯片。   连接策略& 恢复步骤: 目标:让调试器有机会停止内核并中和有问题的固件。 答:降低 SWD 速度 + “RESET 时连接” 在 J‑Link Commander 中: J-Link> device S32K146 J-Link> if SWD J-Link> speed 1000 ; start at 1 MHz; if still failing, drop to 100 kHz J-Link> connect 如果仍然失败,请使用手动重置下连接: 在外部将 RESET_B 保持在低电平,为板供电。 在命令行中运行连接。 释放RESET并立即: J-Link> r J-Link> h J-Link> halt 多试几次,尤其是在 100 kHz SWD 速度下,计时至关重要。 B. 更改 J‑Link RESET 策略 不同的 RESET 策略值的行为不同。在 Commander 中(具体 ID 可能因版本而异): J-Link> SetResetType = 3 ; a common “connect under reset / halt after reset”; Try 2 / 4 / 12 etc. depending on your J-Link version J-Link> r J-Link> halt 或者,尝试在 J-Link Commander 中的 RESET " 下选择 " Connect。 Re: Unable to flash S32K146EVB-Q144 board as D1 glowing red 根据 S32K146EVB-SPF-29844-RB.pdf: J104 1-2 来自 OpenSDA J 10 2-3 P5V0 的 RESET 信号。 如果你有外部 9V 或 12V 电源,也可以尝试连接 J107 1-2 P5V_SBC。如果您恰好有一个外部调试器,例如 PEMicro Multilink试试能否下载 S32K146 的程序。 最近下载的项目是什么?是否启用了 CSEc? 请回答我之前的问题,并向我提供使用示波器测量的RESET信号。
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