SEC Test code When https://source.codeaurora.org/ was still around there was some great test code with example builds of Job Descriptors (i.e. https://source.codeaurora.org/external/qoriq/qoriq-components/flib/tree/sec/rta/tests/make_rsa_keys_1.c) However I can't find where they code has been moved to.  Where can I find it now? Re: SEC Test code Thanks, that is exactly what I was looking for! Re: SEC Test code use the next link: https://github.com/nxp-qoriq/flib

PDB_ISR block - What does it do Hello, im going through the pmsm closed loop example of s32k144. want to know what does the PDB isr block do . there is already an option to set delays for pre triggers in the pdb config block. is the pdb isr block neccessary for the execution of pmsm closed loop. thanks Re: PDB_ISR block - What does it do Hello @Sriram  The PDB peripheral is an up-counting timer used to trigger ADC conversion at specific timings in order to measure at least 2 phase currents on the right moments. Also, the PDB is hardware triggered by FTM peripheral(responsible for generating the PWM signals) by asserting the FTM-INIT signal. For dual-shunt current reconstruction method used in this PMSM example, the PDB pre-trigger delay values are set to trigger the ADC conversion for currents A and B in the middle of PWM period and indeed, these values are set using the PDB Configuration Simulink block. The 3-phase currents are reconstructed inside the ADC ISR and also all control loops (slow loop and fast loop) are triggered inside the ADC ISR. To be able to execute all these tasks inside the ADC ISR, it is needed to disable first the FTM-PDB trigger.  As you can seen in the following figure, this is the first step we achieve by calling the PWM Init Trigger Disable and then get the ADC raw data for currents. After all real-time motor control tasks are executed, the hardware trigger from FTM to PDB has to be reinitialized to get new data for 3-phase current reconstruction and this is achieved using the PDB interrupt block that is going to be enabled after the PDB counter has reached the Interrupt Delay value of 4999. Inside the PDB_ISR function the FTM PWM Init Trigger Enable is called. In the following figure, you can observe the application timing diagram for PWM-ADC synchronization: For more details on how the PWM-PDB-ADC synchronization is achieved for PMSM motor control application, check out the following application note: AN12235 Hope this helps! Regards, Stefan.

S9KEAZ series into MCUXPRESSO Dear All. Is it a way to create a project into MCUXpresso for the S9KEAZN32ACLC MCU? I mean, using the standard way that is to create a SDK and build overt it? OR, maybe, by using the "generic M0+" entry? Hints welcome. Best regards. Jorgecon Re: S9KEAZ series into MCUXPRESSO Thanks, Zhang. It is clear. Re: S9KEAZ series into MCUXPRESSO Hello Jorgecon, MCUXPRESSO doesn't support S9KEAZ series. This series is automotive MCU which is supported by S32DS https://www.nxp.com/design/design-center/software/automotive-software-and-tools/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM the related BSP and drivers are under  "Embedded Software" of this page https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/automotive-mcus/ultra-reliable-kea-automotive-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KEA Hope this helps, Jun Zhang

Debugging an i.MX8MPlus Cortex-M7 core on the EVK. Hello all, I am working on setting up my development and debugging environment for the Cortex-M7 core of the i.MX 8M Plus.  I have successfully generated an SDK using the online NXP SDK builder tool, and I am able to open and build the FreeRTOS hello world example using the NXP MCUXpresso VSCode plugin.  However, I have not been able to flash or debug the i.MX 8M Plus on my EVK. I was able to use J-Link Commander with a rev 1.2 J-Link Ultra to confirm SWD communication was working, but I was unable to flash or debug, as Segger does not support debugging Cortex-M7 cores with this hardware revision.  I have since ordered an NXP MCU-Link Pro debugger, but I am having issues getting debugging going with that as well. Should the NXP MCU-Link Pro be able to debug the Cortex-M7 core of an i.MX 8M Plus? If not, what debugging probes are known to support JTAG or SWD debugging the Cortex-m7 core of an i.MX 8M Plus? Re: Debugging an i.MX8MPlus Cortex-M7 core on the EVK. I ordered a J-Trace Cortex and was able to debug successfully. I also had to follow section 4 of the AN14120 .pdf you linked above to debug without reset. Re: Debugging an i.MX8MPlus Cortex-M7 core on the EVK. Hi, Thank you for your interest in NXP Semiconductor products, I have a reference of a j-link plus working, do you have one handy to test it? Could you please follow the guide attached and pass the record with pro and possibly with plus? Notice that also in this post is stated that it's worked with plus. Regards

Can I get the S32K3XX Driver? Hello, @Robin_Shen  I am currently developing firmware for the S32K314 series without using the RTD. While searching for clock drivers, I came across a response you posted and checked the project. It seems that there is a driver folder in the project, which leads me to believe that there might be drivers available for the non-RTD version. Is there any way I can get access to the drivers for each module? Re: Can I get the S32K3XX Driver? thank you for answer! Re: Can I get the S32K3XX Driver? Hi The Baremetal Example Codes used to be available for download from docstore.nxp.com. But this was before the release of S32K3 RTD and is no longer available for download and is not recommended.  Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

MATLAB MBD ツールボックスを使用してアプリケーションを S32K3X4EVB-T172 ボードにダウンロードする際にエラーが発生しました MATLAB 2023aでNXP_MBDToolbox_S32k3xxバージョン1.4を使用して、S32K3X4EVB-T172ボードでサンプルs32k3xx_dio_s32ctを実行しようとしています。ハードウェア部と通信ポートを変更した後、「ターゲットにアプリケーションをダウンロード中に問題が発生しました」というエラーが発生しています。ランタイムエラーがあります。 エラーの詳細については、添付の写真を参照してください。

Request for i.MX8M custom board with raydium-rm68200 panel dts file Dear Forum members, i am trying to bring up display on iMx8mm processor board using raydium-rm68200 driver (drivers/gpu/drm/panel/panel-raydium-rm68200.c) in 5.10 kernel.  Earlier discussed one of the issue specific to rm68200 panel driver in below link. one of the comment mentioned dts file is attached for rm68200 panel but it's not attached in the zip file mentioned in one of the comments. Re: MIPI DSI LCD display in i.MX8M - NXP Community Request to share rm68200 panel dts file for reference? Regards Nela Android Graphics & Display i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Request for i.MX8M custom board with raydium-rm68200 panel dts file done with it. closing. Re: Request for i.MX8M custom board with raydium-rm68200 panel dts file Done with it. closing. Re: Request for i.MX8M custom board with raydium-rm68200 panel dts file Dear chavira Thank you so much for your input. >>https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hd... Referred above dts file and prepare/built successfully rm68200 panel dts file. Now, For the customized LCD Panel (GH8555BLV) at my desk, it uses rm68200 panel driver  along with initialization of  below registers 0x11 and 0x29. {{ DSI_CMD(0x11,0,0x00); //Sleep Out DelayX1ms(150); DSI_CMD(0x29,0,0x00); //Display On DelayX1ms(50); }} How to add above piece of registers initialization code during initialization phase in rm68200 display panel code. (drivers/gpu/drm/panel/panel-raydium-rm68200.c)(kernel version-5.10) Referred below link  https://forums.raspberrypi.com/viewtopic.php?t=332609 for register initialization but not didn't help much. please do let me know if  you have inputs about it. Regards Nela Re: Request for i.MX8M custom board with raydium-rm68200 panel dts file Hi @koteswararao18! Thank you for contacting NXP Support! You can check the next device tree for reference: https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8ulp-evk-rk055hdmipi4m.dtsi   Is compatible with the next display: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/5-5-lcd-panel:RK055HDMIPI4M   Best Regards! Chavira

Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board Hi, I'm currently working on a custom board utilizing the LX2160a processor with an XSPI flash to store firmware and boot from it. Looking into the NOR flash address location for the DDR-PHY firmware within the LSDK, I've noticed that it's set to 0x00800000. However, for our custom board's requirements, we need it to be at 0x00500000 instead. Attaching the LSDK NOR-Flash Map. I've attempted to locate this address within the Arm Trusted Firmware (ATF) repository, as BL2 handles the loading of this firmware, but I've been unable to find it. Does anyone have information on how to update the DDR-PHY firmware NOR flash address location? I assume it must be somewhere within the ATF repository since BL2 loads this firmware. Any guidance or pointers would be greatly appreciated. Thank you, Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board Our custom board has 256 MB of flash so I was using this address. I used 0x500000 address location and it works fine. Thank you. Not sure if atf doesn't support flash after 64MB. Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board It seems that the offset 0x8800000 exceeds the size of XSPI NOR flash. Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board Thank you for the response.  I did try that before and I tried to do again when you suggested now.  That MACRO is not having any impact on the location of DDR-PHY.  I generated a pbl with the suggested change and then erased the DDR phy from default location 0x800000 and flashed the image at a custom location 0x8800000. I see the below error. It is unable to find the PHY firmware to train. INFO: pll_ctrl2 = 0x19 INFO: SOC_SI_REV = 2 INFO: dll_lck_param = 0x212 INFO: dll_gain_ctl = 0x61 INFO: prog_acx4_anib_dis 0x0 INFO: Initialize PHY 1 config INFO: pll_ctrl2 = 0x19 INFO: SOC_SI_REV = 2 INFO: dll_lck_param = 0x212 INFO: dll_gain_ctl = 0x61 INFO: prog_acx4_anib_dis 0x0 INFO: Load 1D firmware WARNING: Firmware Image Package header check failed. WARNING: Failed to obtain reference to image id=36 (-2) ERROR: Failed to load 36 firmware. ERROR: Loading firmware failed (error code -2) ERROR: Calculating DDR PHY registers failed. INFO: Time before programming controller 401 ms INFO: Program controller registers INFO: Disable address decoding INFO: PHY handshake completed, timer remains 40 INFO: total size 16 GB INFO: Need to wait up to 2840 ms ERROR: Found training error(s): 0x100 ERROR: Error: Waiting for D_INIT timeout. ERROR: Writing DDR register(s) failed ERROR: Programing DDRC error ERROR: DDR init failed. ERROR: Asserting as the DDR is not initialized yet.ASSERT: plat/nxp/common/setup/ls_bl2_el3_setup.c:285 BACKTRACE: START: assert 0: EL3: 0x18017240 1: EL3: 0x1801a668 2: EL3: 0x18015a84 3: EL3: 0x1800da6c 4: EL3: 0x1800d108 BACKTRACE: END: assert Re: Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board In atf source code, please modify the following in plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h. #define PLAT_DDR_FIP_OFFSET 0x800000

How to display dsi to dual lvds using sn65dsi84? Hi, I would like to use sn65dsi84 to display mipi-dsi as dual-link lvds. However, only imx8m reference can be found. My processor is imx8qxp, using custom bsp in linux kernel 5.15.71. I found some imx8m references, but I don't know how to migrate to imx8qxp. For example, in the sample dts below, I don't know what the replacement for &mipi_dsi_bridge is. ------------------------------- &mipi_dsi_bridge { status = "okay";   port@2 {     mipi_dsi_bridge_out: endpoint {       remote-endpoint = <&sn65dsi84_in>;     };   }; }; ------------------------------- Can I find imx8qxp reference using sn65dsi84? Thanks in advance. Re: How to display dsi to dual lvds using sn65dsi84? Hi @hansung_jung  Please find arch/arm64/boot/dts/freescale/imx8x-mek.dtsi and refer adv7535 node to port your sn65dsi84 node. &mipi0_dsi_host { status = "okay"; ports { port@1 { reg = <1>; mipi0_adv_out: endpoint { remote-endpoint = <&adv7535_0_in>; }; }; }; };

about S32K3XX RTOS example i'm tried to executed the RTPS_example_S32K312_SC1/RTOS_example_S32K312_SC1 I DID EB tresos.exe and install new software Added a file whose file name ends with updatestie. generate the new project and then build project  but i meet the error be called the file Os.h not in this proejct. and in peripherals RTOS_S32K3XX is not found in the toolcahin/IDE project. the project will not compile! what can i do to solve the error? Re: about S32K3XX RTOS example Hi i figure out i missed to download s32m27X RTM in freeRTOS 10.6.0. Thank  you. Re: about S32K3XX RTOS example Hi  Seems that you are testing the example of S32K3xx_NXP_RTOS_version_0.4.1 Maturity level is CD. This is CD NXP RTOS 0.4.1 release for S32K3xx platform to support AUTOSAR OS version 4.4 validated on real hardware. Did you follow the method introduced in chapter 1.2.1 Installation Design Studio of S32K3xx_NXP_RTOS_4_4_153_CODEDROP_0_4_1_D2312_Readme.pdf? Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

如何找到已安装 SDK 的确切位置？ 我正在阅读“EVK-MIMXRT1060 的 MCUXpresso SDK 入门”，这篇文章介绍了包文件夹和每个示例的结构。 我尝试从已安装 SDK 窗口打开已安装 SDK 的本地位置，但只有 .zip文件。我尝试使用 Welcome | MCUXpresso SDK Builder (nxp.com) 从互联网下载 SDK，我解压了 .zip文件，还有一些示例文件夹。在哪里可以找到安装在 MCUXpresso IDE 中与 .zip 相同的示例文件夹文件？ 此外，我还检查了 IDE 中的 hello_world 文件夹结构和 hello_world 项目结构。这太不同了。在IDE中，有很多文件夹，例如“board”，“component”，“device”......您可以在所附图片中看到。例如，IDE 中有文件“semihost_hardfault.c”，但 .zip 的 hello_world 文件夹中没有此文件文件。如何了解IDE中项目的结构？现在我无法从文件夹（.zip将文件复制到 IDE。 抱歉我的英语不太好。谢谢。

sequence number and timestamps out of order in kernel log I created a kernel log in NOINIT RAM so that it could be saved across reboots. The initial goal was to save the kernel log in the state it was in right before a watchdog timeout occurred while interrupts were disabled. The interrupts, tragically, were disabled in library code we purchased. Since it's in NOINIT RAM we could dump it to the console and save it to a file on an SD card on the next boot. This all appears to be working well, however a couple of interesting anomalies in the log data are unsettling. Specifically, some of the log entries have either the sequence number or timestamp out of order. The majority of the log have all the timestamps and sequence numbers in order, but it's tough to feel certain that we can pinpoint the last log entry (to point to the active task that watchdogged) if this info can be out of sequence. Can anyone tell me if it's normal for this info to be out of sequence in the log? Thanks! Re: sequence number and timestamps out of order in kernel log I found a different way to solve our problem by using the MQX task watchdogs and expiry functions, so I'm abandoning the kernel logging facility effort. I heard that the kernel logging code has not changed in a very long time and should be good. Not sure why it wasn't working for me, but it was probably my fault somehow. Re: sequence number and timestamps out of order in kernel log sorry for confusion, because I saw same issues happened on Linux .  If you are using MQX,    it maybe MQX v5.    I would suggest you contact our MQX partner, Embedded Access for fast support.     Embedded Access - MQX Design, Products, & Services or contact with [email protected]. Regards Daniel Re: sequence number and timestamps out of order in kernel log The Linux Forum? This is a question about MQX, not Linux. Re: sequence number and timestamps out of order in kernel log Hi Sodacan I would suggest you post this question on Linux Forum, Linux experts are there. Forums - The Linux Forum Regards Daniel Re: sequence number and timestamps out of order in kernel log A related piece of confusion is that when I dump my saved kernel log to the console, in general (as long as none are out of order), the timestamps and sequence numbers do advance from the beginning of the log all the way to the end, even though I created it using the overwrite option. My expectation was that somewhere in the middle of the log the sequence numbers and timestamps would switch to an earlier value/time and advance from there. Not being an ARM ASM expert, I haven't figured out whether or not this is the expected behavior for the overwrite feature. I was expecting circular FIFO type behavior. Was my expectation incorrect? memset(kloginfo, 0xEE, sizeof(kloginfo)); result = _klog_create_at(sizeof(kloginfo), LOG_OVERWRITE, static_cast (kloginfo));

i.MX93: Understanding Compatibility Between A0 and A1 Silicon Versions Dear NXP Team, NXP released AN13997 on August 29, 2023, detailing the migration from silicon A0 to A1. Now, I am reaching out regarding the support for A0 silicon in the firmware-ele-imx_0.1.1 release. It appears that support for A0 silicon may have been dropped in this version. Specifically, I have noticed that the file mx93a0-ahab-container.img is not present in the firmware package. However, according to Semantic Versioning (SegVer), such changes should not result in breaking changes. Could someone kindly shed light on whether the exclusion of support for A0 silicon in firmware-ele-imx_0.1.1 is intentional or an oversight during the release process? Additionally, I would appreciate insights from experts on the implications of this change for both A0 and A1 silicon from bootloader perspective. Furthermore, I would like to provide some context regarding my current setup. I am currently utilizing a VAR-SOM-MX93 with A0 silicon, running on Yocto 4.3 Nanbield release with kernel version 6.1.24, mkimage version lf-6.6.3_1.0.0, and firmware-ele-imx_0.1.0 from meta-freescale. This configuration has been stable for our application, and any insight into the compatibility or recommended upgrade path would be greatly appreciated. Thank you in advance for your assistance and expertise. Linux Yocto Project Re: i.MX93: Understanding Compatibility Between A0 and A1 Silicon Versions Hi, Thank you for your interest in NXP Semiconductor products, It's an intentional change, i.MX 93 A0 was a sample sent for customers to begin with testing and development, A0 chips won't reach the market, nor the customers that once got A0 chips. The upgrade path should be from the development side, get an A1 version of the silicon with silicon improvements, BSP support and also, your production product would meet the same A1 chips. These are the reasons to move to A1 and why A0 is not supported anymore. Regards

LPDDR4 Stresstest fails with three frequency points but passes with single, yet highest frequency Hello everyone, I am currently working on a board bring-up with the following combination of SOC, RAM and Software for the RAM-Stresstest: - i.MX 8M Plus (1600 MHz) + Micron LPDDR4 4GB (MT53D1024M32D4DS) - DDR Stresstest "mscale_ddr_tool_v3.21" I have used the NXP RPA Excel sheet for generating the according ".ds"-file for the Stresstest program. The question is as following: Why does the Stresstest run smoothly and without errors, even under temperature fluctuations, when chosing 2000 MHz as the single frequency for the test, but fails when i chose the same parameterset, but now with three frequency points enabled. In that case the default, additional 200 MHz and 50 MHz, are tested as well.  Thats especially strange, because the first frequency point under test is 2000 MHz and the test fails immediately at the first iteration during the "memcpy SSN armv8_x32 test", where the 2000 MHZ frequency point is used (?!?!).  Bottomline: 1)How can it be that the same parameterset in the RPA sheet functions perfectly when only testing the highest, most layout/time critical frequency, but fails when i only enable the additional much lower frequency testpoints? Any help is hugely appreciated Greetings Niko i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: LPDDR4 Stresstest fails with three frequency points but passes with single, yet highest frequenc Hello @Manuel_Salas , its working now! Ergo i am doing well and hope that you do too:) The solution was indeed the change of the testtool.  Thank you very much! Niko Re: LPDDR4 Stresstest fails with three frequency points but passes with single, yet highest frequenc Hello @NikJur  I hope you are doing well. Could you please try again but now use the Config tools instead or mscale tool? Config tools V15 works well for me.Also you can see the user guide for config tools in section 4 that is about of how to use DDR tool. Best regards. Salas.

Doubt on using PWM and IC on FTM0 Use PWM_PAL to generate PWM on FTM0 channels 1, 3, 7 and manually initialize input capture rising edge callback FTM0 channels 2 and 6. It's clear that from the SDK configuration is not possible to use/configure IC_PAL and PWM_PAL using the same FTM0 peripheral. So, I would like to take the path of configuring the PWM channels using PWM_PAL and manually initialize input capture to detect the rising edge on FTM0 channels 2 and 6. Please help me know whether it is possible and status = PWM_Init(&pwm_pal_1_instance, &pwm_pal_1_configs); only affects the channels that are configured as PWM (1, 3, and 7) and still, other channels (2 and 6) of FTM0 can be configured as input capture (rising/falling/rising & falling) edge input.  We need these settings based on our project requirements.  Re: Doubt on using PWM and IC on FTM0 Hi@Shail_meera You are right, you can not set the ICRST bit, and then you use other timers to record the time of the trigger event. You are free to set it up however you want, but this is not a recommended usage and we have no such routine for you to refer to. Re: Doubt on using PWM and IC on FTM0 Please refer this section  which tells that FTM counter reset can be avoided if ICRST = 0. This will limit IC not to measure period between pulses but still can be used for raising/falling/rising & falling edge detection purpose. Re: Doubt on using PWM and IC on FTM0 So it means on every input capture event  FTM0_COUNT is reset to 0 which is used commonly by FTM0. There is a register CnSC which is used by each channel and setting ICRST = 0 should not reset the FTM0_COUNT values. And this should allow usage of input capture using same FTM0 instance. For input capture we will only need a interrupt call on rising/falling edge and I am calculating frequency using LPTMR by measuring the count between two rising edge. I need a solution to measure input frequency from FTM0 Channel 2 while having PWM output on FTM0 1, 3 and 7. Re: Doubt on using PWM and IC on FTM0 Hi@Shaik_meera There is not only related to SDK, but also FTM features. My suggestion is that you need to use two FTM modules to implement the PWM output and Input capture features respectively. For Input Capture, when a capture event is detected, it will resets the counter, which affects the PWM output. Re: Doubt on using PWM and IC on FTM0 Is there an alternative way to do this. May be initializing both PWM and IC manually using just C code. Is there any example to do this? Re: Doubt on using PWM and IC on FTM0 Hi@Shaik_meera No , you still can't achieve it, Re: Doubt on using PWM and IC on FTM0 I understand its cannot be done directly from SDK configuration. 1. PWM PAL I will configure using the SDK 2. For IC I will create below Init function and I will not add any configuration using SDK GUI: void FTM0_Ch2_risingedge_cb() { /* Rising edge detected for channel 2 */ } IC_InitFTM0_Channel2(void) { uint8_t chnlPairNum = 0U; chnlPairNum = (uint8_t)(2 >> 1); //for channel 2 /* Disable the dual edge mode */ FTM_DRV_SetDualEdgeCaptureCmd(FTM0, chnlPairNum, false); /* Set input capture mode */ FTM_DRV_SetChnMSnBAMode(FTM0, 2, 0U); /* Set the event which will generate the interrupt */ FTM_DRV_SetChnEdgeLevel(FTM0, 2,0x01); //rising edge interrupt /* Enable interrupt request for the current channel */ FTM_DRV_EnableChnInt(FTM0, 2); INT_SYS_InstallHandler(FTM0_Ch0_7_IRQn, FTM0_Ch2_risingedge_cb, (isr_t *)0); INT_SYS_EnableIRQ(FTM0_Ch0_7_IRQn); } Re: Doubt on using PWM and IC on FTM0 Hi@Shaik_meera No, this can't be done, You have to use two different FTM instance for PWM and IC respectively.

FLEXPWM outputs I need 5 different PWM outputs with adjustable different frequency and different duty cycle. I am using IMXRT1176 and it has 4 PWM peripherals from PWM1 to PWM4. I am using all physical ouptut pins of PWM2, PWM3 and PWM4 for another ICs.(for SDRAM and ENET connections.)  So I have only PWM1 available for my task. - FLEXPWM1_PWM0_A (N12 pin) - FLEXPWM1_PWM0_B (R14 pin) - FLEXPWM1_PWM1_A (R13 pin) - FLEXPWM1_PWM1_B (P15 pin) - FLEXPWM1_PWM2_B (P13 pin) The above PWM1, I can adjust different output frequency and duty cycle separately for each except (R14 pin) and (P15 pin).  For  (R14 pin) and (P15 pin), I can adjust different duty cycle but not adjust different frequency. Because both are connected to the same sub module of PWM1. How can achieve to use 2 extra PWM ouptuts that I need with different freq and duty cycle? Thanks. i.MXRT 106x Re: FLEXPWM outputs @MultipleMonomials  thank you very much for sharing very valuable information with us. You are right. By using XBARA peripheral, I can use 11 seperate PWMs with different frequency and different duty cycle adjustable each. I am not sure why NXP support team not well guide me in a right way.  I have tested it on my eval board imxrt1166 with adding following lines; I share with anyone who needs  more PWM outputs in addition to existing peripheral output pins pyhsically. With using XBARA, all FLEXPWM1-2-3-4 sub-module outputs can be directed/routed to XBARA physical output pins. BOARD_PWM_BASEADDR->SM[3].TCTRL = PWM_TCTRL_PWAOT0(1) | PWM_TCTRL_PWBOT1(1); //FLEXPWM1_PWM3SUBMODULE_A //FLEXPWM1_PWM3SUBMODULE_B XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputFlexpwm1Pwm3OutTrig0, kXBARA1_OutputIomuxXbarInout18); and add below lines to pin_mux.c files; IOMUXC_GPR->GPR20 |= IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(0x01); IOMUXC_SetPinMux(IOMUXC_GPIO_AD_34_XBAR1_INOUT18, 0U); // FLEXPWM1_PWM3_A Re: FLEXPWM outputs Another option here would be to route the signals from PWM2, 3, or 4 to other pins via the XBAR.  PWM signals can be routed through the XBAR via PWM register settings, see here for some more info. Re: FLEXPWM outputs @Gavin_Jia Do you have any suggestion about the problem? 回复： FLEXPWM outputs Hello @Gavin_Jia . I am working on FLEXIO, today . I viewed the "flexio_pwm" example in SDK. I applied it on my eval board to see its effect. I changed my previous two PWM pins to FLEXIO. See the below pls: IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_FLEXIO2_D00, 0U);  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_FLEXIO2_D02, 0U);  Later, I observed two signals on oscilloscope. I adjusted two pins as different freq and duty cycles as FLEXIO. My observation is as follows; - When I set some freq values for my two pins, one of the signal is not set at programmed freq value, instead it produces different freq. Such as when I set freq to 13KHz, I see it on scope screen as 49KHz or something different. This is true for 15,10,12,18Khz. However when setting to 20Khz, it is set as correctly. So, some freq values are not programmed well. For another Flexio signal, it is always set to 50KHz and always correct during my observation. - When I set only one of my signals, freq value is correctly programmed to 12,13,15,18,20,30Khz. No problem exists. Setting single pin works as expected. However, as I stated above, setting 2 pins yield unexpected results.Why? - Lastly, whether setting single or both Flexio output pins; When I set freq value below 12Khz, the example in SDK, is not working because of below lines;  #define FLEXIO_MAX_FREQUENCY (DEMO_FLEXIO_CLOCK_FREQUENCY / 2U) #define FLEXIO_MIN_FREQUENCY (DEMO_FLEXIO_CLOCK_FREQUENCY / 512U) Even though I changed FLEXIO_MIN_FREQUENCY as  DEMO_FLEXIO_CLOCK_FREQUENCY / 4096U value, I can not program freq value to flexio pins correctly. I tried that for only setting my single FLEXIO signal and both. However every time I saw the wrong freq setting on oscilloscope screen. Demo example and the .pdf link you sent, uses 48KHz pwm freq for only one output pin. I tried to change freq values lower than 12KHz, but it is not working as expected. Freq settings get wrong every time evn though I lowered FLEXIO_MIN_FREQUENCY macro. - Is there any limitation with setting lower freq with using Flexio? Below 12Khz is possible? Such as 500Hz or 1Khz? Wait your helps.Thanks  回复： FLEXPWM outputs Hi @burhanhagi , Thanks for your interest in NXP MIMXRT series! In this usage scenario, hardware resources are limited, so we can consider using FlexIO to generate PWM.  FlexIO is an on-chip peripheral available on NXP I.MXRT series. It is a highly configurable module capable of emulating a wide range of communication protocols, such as UART, I2C,SPI, and I2S. Users can also use FlexIO to generate PWM and PFM waveform. The standalone peripheral module FlexIO is not used for replacement of the PWM and PFM generator, but as an additional peripheral module of the MCU. This module enable users to build their own peripheral directly in the microcontroller. It is suggested to refer to this application note, as well as the flexio_pwm demo in the SDK: Best regards, Gavin

Does MPC5777c have SSCG capability? Hello. I have question about SSCG(Spread Spectrum Clok Generation) for MPC5777c. I couldn't find SSCG for MPC5777c Nowadays I am working on ways to improve EMC performance and reduce EMI. Q1. Does MPC5777c have SSCG capability? Q2. If MPC5777c doesn't have SSCG capability, Is there a function similar to SSCG? If so, please let me know. Q3. I would like to know all the unique features that can lower EMI and improve EMC performance of MPC5777c. Thank you for always helping me. I hope you have a great day. MPC5777C  Re: Does MPC5777c have SSCG capability? PLLDIG offer Frequency modulation. If PLL is modulated, frequency is spread proportionally around central frequency. It is exactly the feature you are looking for.

MPC5777c 有 SSCG 功能吗？ 您好。 我对MPC5777c 的 SSCG（扩频时钟生成）有疑问。 我找不到 MPC5777c 的 SSCG 目前我正在研究如何提高 EMC 性能并降低 EMI。 问题1 ：MPC5777c 具有 SSCG 功能吗？ 问2 。如果MPC5777c没有SSCG功能，是否有类似SSCG的功能？如果是的话，请告诉我。 问3 。我想了解所有可以降低 EMI 和提高 MPC5777c 的 EMC 性能的独特功能。 谢谢你一直以来的帮助。 祝您度过愉快的一天。 MPC5777C

I.MX RT1170 programming in production process Hi I'm developing a custom board with RT1170. Do you have any tool which can be used for programming flash via SDW or JTAG in production process? Re: I.MX RT1170 programming in production process Hi @Habib_MS  Thank you I try to use LinkServer. Re: I.MX RT1170 programming in production process Hello Again @Eugene3 , The most practical way to do programming in production process is through Manufacturing tool. However, it does not support SWD or JLINK, so if you want to use any of these, there are two ways: The first, but not the most efficient, is to do it through the link server with commands, programming each card individually. This is the tool that the MCUxpresso IDE uses to load an image, so if you are interested in using this option, I provide you with a link that can help you: LinkServer for Microcontrollers | MCU on Eclipse. The second is with a tool from the suppliers, either SEGGER or PEMICRO, however, you have to see this directly with them to process the corresponding licenses and thus be able to use their tool. BR, Habib. Re: I.MX RT1170 programming in production process Hi @Habib_MS  Thank you for your help. I'd like to program RT1170 by SWD or JTAG in the production stage. Is it possible with this tool? I could only find ways to program using USB or UART. Re: I.MX RT1170 programming in production process Hello @Eugene3 , The utility that can help you in the production stage is the MCUxpresso Secure Provisioning Tool version 8.0, in this software there is a "Manufacturing tool" section where you can load the image to several Boards at the same time, the following image shows where this tool is located: For more information about how this tool works, you can review chapter 5.7 of the document called MCUXpresso Secure Provisioning Tool User Guide v.8 which can be found in the following link:  MCUXpresso Secure Provisioning Tool | NXP Semiconductors It is important to highlight that this tool is only available from version 8 of the MCUxpresso secure provisioning tool, so it is important that you have it. BR, Habib.

S32K144 SPI payload limitation upwards 512bytes Hello community, I am working on S32K144 EVB board with NFC front-end device. S32K144EVB (master) communicates via SPI communication to NFC front-end device.  I would like to transfer 2kB payload and however more than 512 bytes does not work and S32K SPI driver get stuck and not IRQ is received. Does anyone know there, if there is certain limitation or managed to have bigger than 512bytes payload? Best regards Khulan Re: S32K144 SPI payload limitation upwards 512bytes Hello @nxp84325 @Khulan, I just sent you an email. Regards, Daniel Re: S32K144 SPI payload limitation upwards 512bytes Hi Daniel, I am working with Khulan on the same project. a Few questions: - is the same limitation present on S32K312? I have tried to send more than 4096 bits per frame with K312 and saw the same issue. Also, based on driver source code, it seems the same mask is applied to the TCR (0xFFF --> 12 bits). So I guess it's same. (using RTD version 3.0.0) - Concerning the S32K144, I have tried continuous mode. The problem is that PCS doesn't go back up at the end of the frame. Are we supposed to drive it manually? (using SDK 3.0.0) thanks in advance. Re: S32K144 SPI payload limitation upwards 512bytes Hi Daniel, We can confirm that our side that LSPI max framesize is 512 bytes. However we would need to support 1040 bytes payload. We can use alternative to S32K144EVB as well S32K312EVB. Does S32K312EVB use also same LSPI and would have same frame size limitation? Which document can I look in the future to get that information as well Otherwise we will further with continuous mode. Thanks and best regards Khulan Re: S32K144 SPI payload limitation upwards 512bytes Hi, I am using design studio version 3.5 with driver version S32SDK_S32K1XX_RTM_4.0.1. Best regards Khulan Re: S32K144 SPI payload limitation upwards 512bytes The .bitcount is 8 in your configuration, one frame is 8bit long. And .isPcsContinuos is false, so the CS deasserts after every frame. Again, which version of the SDK/RTD drivers do you use? BR, Daniel Re: S32K144 SPI payload limitation upwards 512bytes Hello Daniel, Thanks for the quick reply. I am using processor expert to generate my driver code and DMA mode is not enabled. It looks below. Where do you define TCR[FRAMESZ]) ? Best regards Khulan Re: S32K144 SPI payload limitation upwards 512bytes Hello @Khulan, Can you specify the revision of the drivers? What frame size have you set? The LPSPI module can send 4096b or 512B within one frame (TCR[FRAMESZ]), but it can send more frames in the continuous mode (TCR[CONT = 1]). Regards, Daniel