Wi-Fi 命令响应超时 我正在使用基于恩智浦 IW612 芯片组的 i.MXRT1062 跨界微控制器和村田 2EL M.2 无线卡开发一个项目。该项目使用了 MCUXpresso SDK 和 FreeRTOS。当前 SDK 版本为 25.12。 在固件运行过程中，调试控制台有时会显示以下输出： `[wifi] 警告：命令响应超时。命令 0x0，长度 1514，序列号 0x16` 或 `[wifi] 警告：命令响应超时。命令 0x0，长度 66，序列号 0x16` 或 `[wifi] 警告：命令响应超时。命令 0x0，长度 190，序列号 0x16` 或 `[wifi] 警告：命令响应超时。命令 0x0，长度 60，序列号 0x16` 我不知道这些行是什么意思，可能是无线模块出了问题。打印任务列表之后，会触发紧急情况并使固件停止运行。我认为这个问题通常发生在通过无线网络连接进行流量大小不一的传输约30分钟后。 SDK 文件中的相应位置位于 `wifi_wait_for_cmdresp` 函数中的 `中间件/wifi_nxp/wifidriver/wifi.c` 中。这一点还进一步得到证实：在之前的调试控制台输出与这一行之间，大约有20秒的间隔。 我该如何排查这个问题？我可以与您合作，提供进一步的调试信息或测试 SDK 的修复方案。 Re: Wi-Fi command response timeout 您好， 我知道您正在使用一个自定义应用程序，但您是以哪个 SDK 示例作为起点开发的？如果您能使用未经修改的 SDK 示例重现相同的问题，这将极大有助于定位问题。 看来驱动程序一直在等待命令响应，但在超时结束前并未收到响应。 请在 wifi_config.h 中启用以下调试宏： CONFIG_WIFI_CMD_RESP_DEBUG CONFIG_WIFI_EVENTS_DEBUG CONFIG_WIFI_IO_INFO_DUMP CONFIG_WIFI_EXTRA_DEBUG 启用宏后，请重新编译示例并再次进行测试。请分享输出结果。 最好用最新的 SDK 进行测试，看看问题是否依然存在。 Re: Wi-Fi command response timeout 这是固件卡住时的调试输出。如果您需要之前的日志行，请告诉我。 2026年6月23日 12:27:48.808 [RX] - [wifi] 警告：命令响应超时。命令 0x0，长度 890，序列号 0x16 SDIO多端口组寄存器值： **** 转储 @ 20218FC0 长度：196 **** 00 00 00 00 ff 00 00 00 c3 00 00 00 00 00 00 00 00 00 00 00 00 00 f0 7f 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 03 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 00 00 00 00 00 87 0c 00 00 00 00 00 00 00 00 00 00 1c c2 06 c0 f4 德 09 c0 00 1e ff ff 00 0a 36 01 00 00 96 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 10 cc f0 ff ff ff ff ff 00 00 ff ff ff ff ff ff f4 74 04 c0 80 98 04 c0 00 00 00 00 ******** 结束转储 ******* 名称 状态 优先级 堆栈号 ================================================== 主任务 X 3 581 6 print_dhcp R 0 683 17 空闲 R 0 92 2 tcp/ip B 3 400 1 Tmr Svc B 4 196 3 supplicant_main_tas B 2 1456 14 nfc_cfg B 0 715 7 dhcpd_task B 3 406 15 HTTP 服务器 B 1 888 18 wifi_scan_task B 1 255 11 wlcmgr_task B 3 244 13 wifi_drv_task B 3 228 10 lwip_rx B 3 431 8 wifi_core_task B 3 276 12 [wifi] 开始处理挂起 [wifi] 正在发起 wifi 身份验证 [固件下载] S 2026年6月23日 12:27:48.824 [RX] - 开始从 0x602319fc 下载固件：1618224 2026年6月23日 12:27:54.807 [RX] - [wifi_io] 错误：SDIO - 固件就绪寄存器未设置 [wifi] 错误：sd_wifi_reinit 失败。状态码-1 断言：wlan_process_hang：550 断言失败：恐慌！ 断言错误“0”：文件“C:/tmp/mcuxsdk/mcuxsdk/中间件/wifi_nxp/wifidriver/incl/mlan_api.h”第65行函数名“panic” Re: Wi-Fi command response timeout @DanielRuvalcaba你好，请问这个问题有任何进展吗？SDK 26.03 版本也存在这个问题，您还需要我提供更多调试信息吗？ Re: Wi-Fi command response timeout 你使用的是哪个SDK示例？ 请问能否提供重现此问题的步骤？ 您使用的是定制电路板还是恩智浦参考电路板？ 是否存在任何特定的操作或条件会持续触发该问题？ 问候， 丹尼尔。 Re: Wi-Fi command response timeout 我最初使用的是 wifi_setup SDK 示例，但现在已经做了很大的修改。我使用的是定制板。 我们注意到，当无线网卡接收（可能发送）流量较大（每秒 60 兆字节或更多）时，就会出现此问题，同时固件会向无线网卡发送命令以查询平均 RSSI 和 SNR。我们的代码每秒执行一次该操作，问题通常会在一分钟内（通常更短）被触发。 如果我禁用命令传输，就不会触发该问题。 我希望这些信息能帮助您重现该问题（关键时刻是接收流量和命令传输同时进行）。

imx95 M7 boot Hello, Can you please tell me how to boot the cortex M7 from uboot? It seems that cortex a55/uboot have no access to the TCM of M7, so it is not possible to load the image. On the other hand, the M33 crashed when the M7 is released on 0x9000 0000. It seems the the uboot commands (bootaux, prepaux, stopaux) have no effect at all, on uboot version 04.2025. I tried to boot the M7 with the SM on M33, I can stop it, change the boot vector, but releasing it on DDR memory causes an error. Can you give me some hints how to properly start the M7 with uboot or SM, or how to allow ddr access for the M7? Thank you in advance! Re: imx95 M7 boot Hello, I suggest you take a look in the next application note: https://docs.nxp.com/bundle/AN14748/page/topics/introduction.html Best regards. Re: imx95 M7 boot Hello, thank you for your reply. Unfortunately, the Application Note you mentioned, does not describe how to start the M7 core neither from Uboot, nor with SM on M33. It also doesn't mention how to configure the platform to provide DDR access to the M7. Can you help me with these topics? Do you have any suggestions? When will the booaux,prepaux and stopaux commands be fully implemented and usable in uboot? Thanks in advance! Re: imx95 M7 boot Hello, Please take a look in section 4.7.4.1.5 i.MX 95 of i.MX Linux User's Guide. Best regards. Re: imx95 M7 boot I managed to get it to work using the following instructions: fatload mmc 0:1 ${loadaddr} mcore-demos/imx95-15x15-evk_m7_TCM_hello_world.bin cp.b ${loadaddr} 0x203c0000 ${filesize} rproc stop 0 rproc start 0 But for this you need to edit the config imx-system-manager(for imx95evk-configs/mx95evk.cfg). You need to allow access to TCM memory for A55 non-secure LMM. My diff(Set LMM_1 from NOTIFY to ALL, add TCM and M7MIX region to A55 non-secure): -LMM_1                     NOTIFY +LMM_1                     ALL -OCRAM               EXEC, begin=0x0204C0000, size=96K +M7MIX                EXEC, begin=0x020380000, end=0x02047FFFF +OCRAM                EXEC, begin=0x020480000, size=352K +M7MIX                EXEC, begin=0x04A060000, end=0x04A09FFF Rebuild: in imx-system-manager folder - make config=mx95evk cfg - for perl rebuild files after chages. Then rebuild packets in yocto: bitbake -f -ccompile imx-system-manager bitbake imx-system-manager bitbake -f -ccompile imx-boot bitbake imx-boot After this there will be access to TCM memory from u-boot. But I have another problem: I need to update the M7 code from the file system in Uboot on the fly. But the code doesn't fit in the TCM region. That's why I'm using DDR. I've successfully launched the code, which runs and loads completely using DDR, but I don't know how to update it on the fly using u-boot, becaus u-boot have access to DDR from 0x90000000 .... M7 code use region from 0x80000000...This memory region not available from u-boot not only through imx-system-manager(.cfg), but also through the u-boot sources. I think this was done intentionally to separate memory across different memory regions between two different LMM. I wanted to update code M7 via the M33 code(imx-system-manager), added both regions for this LMM(m33), but only the M7 region is visible perfectly(0x80000000...). The U-boot region is visible(0x90000000), but the zeros are readable from m33 side... Re: imx95 M7 boot Hello, on my system I don't have rproc, but bootaux. The command does nothing in U-Boot. I managed to start the M7 like this. Load image to 0x88000000, there is a 32MB space which is shared my Cortex A and M7, but you have to disable dcache to be able to read/write to it from U-Boot Use System manager rst.w command to stop the core, cpu.w command to set boot vector to 0x8800 0000 and again rst.w to start the  M7 core. This worked for me. Good Luck

S32K324へのFreeRTOS SMPの展開 NXPのエンジニアの皆様、こんにちは。 S32K324チップ（マルチコア）上でFreeRTOS SMPを実行する必要があります。S32K358_SMPサンプルプログラムを参照したところ、図に示すようにSMP構成が実行されていないことがわかりました。 私はRTD 5.0.0とFreeRTOSを使用しています。バージョン5.0.0における私の問題点は以下のとおりです。 1. S32K324（マルチコア）チップはFreeRTOS SMPの展開をサポートしていますか？ 2. 御社には他に参考事例はありますか？あるいは、更新版に関連参考文献を掲載しましたか？ お返事をお待ちしております。 Re: S32K324 部署FreeRTOS SMP こんにちは、@ Wanyj FreeRTOSに対する技術サポートは限定的ですが、FreeRTOSのSMP機能に関してはサポート対象となります。 この例を参考にしてください。これは私が見つけた中で最も完全なSMP使用例です。 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3xx-FreeRTOS-SMP/ta-p/2292229

How does RT118x achieve the support for multiple images selection loading? Currently, my development environment is MCUXpresso IDE. In the SDK, the multicore examples consist of a master project and a slave project. Moreover, in the master project, only one slave  image file location can be specified. I want to achieve a function: Burn a CM33 image and multiple CM7 images into Flash. After the CM33 core starts up, it will load different CM7 images into RAM based on the switch status or other configuration items for running. How can this be achieved? Are there any examples? Re: How does RT118x achieve the support for multiple images selection loading? Hi @ethan_dang1 , Thanks for your interest in NXP MIMXRT series! RT118x can support this use case, but not through a ready-made ROM/MCUXpresso IDE feature that automatically selects one CM7 image from multiple candidates.   The RT118x boot container can describe multiple images, but this is a fixed boot-image/container mechanism, not a GPIO/switch-based runtime selection policy. For the requested behavior, CM33 should be implemented as a custom boot manager. After CM33 boots, it reads the switch/configuration, selects one CM7 image stored in Flash, loads it to the expected target memory, configures the M7 vector/start condition and access permission, and then releases/kicks off CM7. There is no confirmed SDK example that directly implements “one CM33 image + multiple selectable CM7 images”. The closest references are the multicore examples, multicore_trigger, the RT1180 M7 kick-off procedure, and dynamic code loading/overlay concepts. We apologize for any inconvenience this may cause!   Best regards, Gavin

S32K311 の eMIOS0 入力捕捉 IDE バージョン： S32 Design Studio for S32 Platform バージョン: 3.6.7 RTDバージョン：7.0.1 eMIOS0 のパス 0 がバス B として機能する eMIOS0 のチャネル 1 は入力捕捉として機能します（BUS B を使用） eMIOS0のチャネル4はPWM出力として機能します（内部数値） 同じ eMIOS0 が異なるチャネルで許可されているかどうか PWM と入力检测? EB に到達していない位置は通知され、位置が検出されていないことが通知されます。         Re: S32K311的eMIOS0输入捕获问题 eMISO_0、eMISO_1、eMISO_2は異なるチャネルで共有できます。設定の詳細については、UM拡張モジュラーIOサブシステム（eMIOS）のブロック図を参照してください。 Re: S32K311的eMIOS0输入捕获问题 こんにちは@北大街老司机 潜在王者 はい、同じインスタンス内の異なるチャネルは、異なるモードで設定できます。 「EB」とは、EB tresos Studioのことでしょうか？確認させてください。 BR、VaneB

NTAG213 CHIP Writing issue We are currently using your genuine NTAG213 chips, but we frequently experience an issue where data fails to be written during the encoding process. For example, when writing data to 1,000 chips, 80 of them failed initially. Upon retrying, the number of failures dropped to 60. While the defect rate decreased with repeated attempts, the final 26 chips remained completely un-writable, even after more than 10 retries. While this is somewhat manageable during our current testing phase, if this kind of issue occurs on our actual manufacturing line, it will cause significant operational and financial losses for our company. Could you please explain the potential causes of this writing failure and provide a solution to resolve this issue? Re: NTAG213 CHIP Writing issue Hello sir, Is possible that the issue isn't about the NTAG but about the NFC Reader you are using. There are NFC Reader solutions based on our NFC Readers designed specifically for mass-production. Could you please provide a little more information about your setup? Additionally, please keep in mind that this is a public community. If you have further specific questions please log in using your company's domain to create a ticket.

S32 Design Studio のライセンス更新 こんにちは、私のS32 Design Studioももうすぐ期限切れになります。延長を手伝ってください。 詳細は以下の通りです。 Arm向けS32 Design Studio アクティベーションID: 5D87-991A-4C45-DD49 評価期間：11日間 機能バージョン: 2.2 機能ステータス：評価中（11日間） よろしくお願いします。 Re: S32 Design Studio License Renewal こんにちは、 お客様のS32DSライセンスが延長されました。

i.MX8MP：CSI0 接口搭配 TP2860 编码器芯片，运行于连续时钟模式 您好， 我们正在尝试将 TP2860 视频编码器集成到基于 IMX8MP 的平台中，但我们无法捕获任何视频。看来CSIS无法与传入的MIPI数据流同步。 平台：VAR CustomBoard 内核上的 Variscite DART-MX8M-PLUS：linux-imx 6.6.52（恩智浦 电路板支持包，imx8-mipi-csi2-sam 驱动程序），yocto 版本 摄像头：TechPoint TP2860 MIPI 编码器（AHD/TVI-> MIPI-CSI2 桥），输出 MIPI 时钟：297 MHz（测量） 接口：CSI0（mipi_csi_0 @ 0x32e40000），2 车道，500 Mbps/Lane，FHD30 (1920x1080 @30) 管道：TP2860-> MIPI D-PHY-> CSIS-> (MediaMix Gasket)- > ISI0-> /dev/video2 v4l2 管道看起来没问题（参见附件 pipeline_info.txt） 相关的（扁平化）设备树信息已附在 devicetree.txt 文件中。 DPHYSTATUS 报告 0xC2（所有通道均处于 HS 模式），但 CSIS帧起始计数器始终为零（实际上，所有 mxc-mipi-csi2.0 计数器均为零）。 我们已经研读了恩智浦（NXP）的AN13857文档，并有以下几个问题： TP2860 在两次突发传输之间将 MIPI 时钟通道保持在 HS 状态（连续时钟模式）。这通过 CSIS DPHYSTATUS = 0xC2 在驱动程序启用 s_stream 之前和之后均保持该值得到了证实： => CSIS 寄存器转储（CSIS 基址 0x32e40000）： CSIS_CMN_CTRL [0x04] = 0x00004105 (ENABLE=1, LANE_NR=1->2 条通道, HDR_MODE=0) CSIS_DPHYCTRL [0x24] = 0x13000007 (hs_settle=0x13, D-PHY 启用) CSIS_DPHYSTATUS [0x20] = 0x000000C2 (HSCLK=1, HSDAT1=1, STOPSTATE_CLK=0) CSIS_INTSRC [0x14] = 0x00000000 (未触发中断) => CSIS_DPHYSTATUS[0x20] = 0x000000C2 第 7 位：HSCLK = 1（时钟通道处于 HS 模式） 第 6 位：HSDAT1 = 1（数据通道 1 处于 HS 模式） 第 1 位： ULPS_CLK = 0（未处于 ULPS 状态） 第 0 位：STOPSTATE_CLK = 0（从未处于 LP-11 停止状态） 这与 NXP AN13857 中的警告一致： " i.MX 8MM、 i.MX 8MN 和 i.MX 8MP 要求连接的摄像头在启用 Rx DPHY 之前处于 LP 状态 。但如果相机处于连续时钟模式，时钟 通道可能始终处于HS模式。在这种情况下，Rx DPHY 可能无法检测到 HS 模式，导致 错误地保持在停止或 ULPS 状态。" TP2860 在直播期间通过 I2C 进行寄存器回读： 0x40 -> 0x08 (驱动程序在 s_stream 之后选择的 MIPI 页面) 0x02 -> 0x7d (MIPI_EN0=1, 所有位均已设置) 0x28 -> 0x00 (STOP_CLK=0, ULPM=0) 0x10 -> 0x20 (启用 MIPI TX, 未处于 RESET 状态) 0x29 -> 0x00 (数据通道停止/ULPS: 无) 我们尝试启用 TP2860 内部 BT.1120 测试模式（排除模拟编码器路径）： 0x40-> 0x08（MIPI 页面）0x 22-> 0x80（TP_ENA=1：绕过模拟解码器，发送数字图案） 但这并不能改善现状。 我们将按以下方式配置 TP2860： 写入 0x02=0x3d、0x03=0x35、0x04=0x35<-- MIPI_ENx=0（通道关闭） 计时：0x2b=0x09（T_PREP RESET 默认），0x2C=0x0A 解码器 PLL 重置：REG 0x06 |= 0x80，msleep (10) MIPI PLL RESET: REG 0x14 |= 0x80、msleep(10)、deassert msleep(50)（PLL锁定时的扩展稳定时间） 0x02=0x7d, 0x03=0x75, 0x04=0x75HS） 问题： 是否支持将 imx8MP Rx D-PHY 与处于连续时钟模式的摄像机配合使用 BSP 机制（STOPPSTATE_CLK 永久为 0）？CSIS / D-PHY 是否有一种模式，在使能 HS-RX 之前，无需依赖时钟通道上 LP-11 的观测结果？ 除了 AN13857 之外，还有关于使用连续时钟 MIPI-CSI2 源进行 CSIS 操作的 imx8MP 的已知勘误表或应用笔记吗？ 包含 TP2860 编码器芯片的相同硬件适用于边界设备 i.MX8 MQ 设置 任何帮助都将不胜感激。 图形与显示 i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: i.MX8MP: CSI0 with TP2860 encoder chip in continous clock mode 你好， 我也遇到了类似的问题，请问您找到解决方法了吗？

关于 AT_NONCACHEABLE_SECTION_INIT() 宏的问题 你好 关于 AT_NONCACHEABLE_SECTION_INIT 及其在 fsl_dcp.c 中的用法，我有几个问题 这会导致一个变量被放入“NonCacheable.init”中章节。本节的名称暗示这是一个未被缓存但已初始化的区域。推测该变量需要由核心以外的主节点进行访问。 我们以 evkmimxrt1020_dcp 为例（适用于 RT1020-EVK） 本示例中的链接器脚本将“NonCacheable.init”放置在 .data 段中（因此在 DTC 中），该区域已初始化，但并非指定的非缓存区域。 这看起来可能是个问题！ 我们再来看看 AT_NONCACHEABLE_SECTION_INIT() 在 DCP 驱动程序中的用法： 变量 `s_dcpContextSwitchingBuffer` 尚未初始化！ 因此有两种情况： 这是故意未初始化的。但在这种情况下，应使用宏 `AT_NONCACHEABLE_SECTION()` 而不是 `AT_NONCACHEABLE_SECTION_INIT()`。 它实际上需要进行初始化。在这种情况下，问题在于它尚未被初始化。 顺祝商祺！ 最大值 Re: questions about AT_NONCACHEABLE_SECTION_INIT() macro 你好@mastupristi， 感谢您的详细分析。我们已经审阅了您提出的这两点。 1. 将 NonCacheable.init 放置在 DTCM 中——这不是缓存一致性问题 您观察得很对，链接器脚本确实放置了 `NonCacheable.init`写入位于 `SRAM_DTC`（DTCM）中的 `.data` 区域。 不过，这在 RT1020 上不会引发缓存一致性问题。DTCM 是 Cortex-M7 上的紧密耦合内存，其访问路径完全通过硬件设计绕过了 L1 数据缓存。尽管它并未被放置在单独命名的 `NCACHE_REGION` 中，但 DTCM 中的数据本质上不可缓存，且对于 DCP 等支持 DMA 的外设而言，访问这些数据是安全的。 请帮忙检查一下这个AN：https://www.nxp.com/docs/en/application-note/AN12042.pdf 而且，如果您修改链接器脚本以将此部分放在 OCRAM 或 同步动态随机存取存储器(SDRAM) 中，则必须确保相应的 MPU 区域配置为不可缓存，或者驱动程序/应用程序执行适当的缓存维护（清理/失效）。 2. 宏的使用——观察正确，不影响功能 你说的没错，`s_dcpContextSwitchingBuffer` 在调用 `AT_NONCACHEABLE_SECTION_INIT()` 时并未指定显式的初始化函数。根据 SDK 规范，`AT_NONCACHEABLE_SECTION_INIT()` 适用于初始值不为零的变量（`= {xx}`），而 `AT_NONCACHEABLE_SECTION()` 适用于初始化为零的变量。 由于该变量的存储范围为静态，因此 C 语言无论如何都会保证其被初始化为零——这并不存在功能性错误。该缓冲区不依赖于任何特定的初始值；DCP 硬件会在运行时管理其内容。 也就是说，使用 `AT_NONCACHEABLE_SECTION () `在语义上更合适，并且可以节省208字节的闪存。我们认为这是一个提升代码质量的机会。 致以最诚挚的问候， Gavin

questions about AT_NONCACHEABLE_SECTION_INIT() macro Hello, I have a few questions about AT_NONCACHEABLE_SECTION_INIT and its use in fsl_dcp.c This causes a variable to be placed in the “NonCacheable.init” section. The name of this section suggests an area that is not cached but is initialized. Presumably, the variable needs to be accessed by a master other than the core. Let's take the example evkmimxrt1020_dcp (for the RT1020-EVK) The linker script in this example places “NonCacheable.init” in .data (and thus in DTC), which is initialized but is not the designated non-cached area. This looks like it could be a problem! Let's also take a look at how AT_NONCACHEABLE_SECTION_INIT() is used in the DCP driver: The variable `s_dcpContextSwitchingBuffer` has not been initialized! So there are two scenarios: It is intentionally left uninitialized. In this case, however, the macro `AT_NONCACHEABLE_SECTION()` should be used instead of `AT_NONCACHEABLE_SECTION_INIT()`. It actually needed to be initialized. In this case, the problem is that it hasn't been initialized. best regards Max Re: questions about AT_NONCACHEABLE_SECTION_INIT() macro Hi @mastupristi , Thank you for your detailed analysis. We have reviewed both points you raised. 1. NonCacheable.init placed in DTCM — Not a cache coherency issue Your observation is correct that the linker script places `NonCacheable.init` into `.data`, which resides in `SRAM_DTC` (DTCM). However, this does not cause a cache coherency problem on RT1020. DTCM is tightly-coupled memory on Cortex-M7 — its access path bypasses the L1 D-Cache entirely by hardware design. Even though it is not placed in a separately named `NCACHE_REGION`, data in DTCM is inherently non-cacheable and safe for DMA-capable peripherals like DCP to access. Please help check this AN: https://www.nxp.com/docs/en/application-note/AN12042.pdf And If you modify the linker script to place this section in OCRAM or SDRAM, you must ensure the corresponding MPU region is configured as non-cacheable, or that the driver/application performs proper cache maintenance (clean/invalidate). 2. Macro usage — Correct observation, no functional impact You are correct that `s_dcpContextSwitchingBuffer` uses `AT_NONCACHEABLE_SECTION_INIT()` without an explicit initializer. Per SDK convention, `AT_NONCACHEABLE_SECTION_INIT()` is intended for variables with non-zero initial values (`= {xx}`), while `AT_NONCACHEABLE_SECTION()` is for zero-initialized variables. Since this variable has static storage duration, C guarantees zero-initialization regardless — there is no functional bug. The buffer does not depend on any specific initial value; the DCP hardware manages its contents at runtime. That said, using `AT_NONCACHEABLE_SECTION()` would be more semantically appropriate and would save 208 bytes of Flash. We acknowledge this as a code quality improvement opportunity. Best regards, Gavin

S32K328 微型控制器的 CPU / 热负荷 我们需要帮助在项目中实现 S32K328 微控制器的 CPU/热负载。请告诉我测试 CPU/热负荷的 API。请说明在多核中运行的所有步骤。 Re: CPU /Thermal load for S32K328 micro controller 你好， 对于 S32K3，没有用于 “CPU/热负载测试” 的专用单个 RTD API。通常这是通过以下方式实现的： - 利用应用程序忙循环或 RTOS 任务在每个内核上产生 CPU 负载 - 通过 ADC API，通过内部 TempSense 路径监测芯片温度 有关温度监测，请查看 ADC TempSense API： Adc_Sar_Ip_TempSenseEnable() Adc_Sar_Ip_GetConvData() Adc_Sar_Ip_TempSenseCalculateTemp() 更多信息，如https://community.nxp.com/t5/S32K/Internal-Temperature-sensor/m-p/1688673 用于在 S32K328 上多核执行： - 创建/使用 S32K3 多核 RTD 项目 - 使用 NXP 多核启动流程启动次核心 - 在每个核心上运行 CPU 压力任务 - 定期读取 TempSense 并记录温度与负载的关系 多核项目生成指南见以下链接 https://community.nxp.com/t5/S32K/Multicore-applications-on-the-S32K3-series-processors/m-p/2050051 BR, Petr Re: CPU /Thermal load for S32K328 micro controller 根据 S32K UM，内部有温度传感器（TempSense）。S32 DESIGN STUDIO sdk 中可能有一些例程

MC33879 initialization voltage abnormality and slow initialization After supplying power to mc33879, enable the en pin and connect a 12V power to the D1 pin of mc33879. Without giving the command, measure the voltage at the S1 pin, which is 12.45V, slightly higher than 12V. Is this normal? Similarly, D1 is connected to a 12V power supply, and S1 is connected to a CAB 500-C current sensor. After I power it on, I control the EN pin high level. According to the manual, after stabilizing at 100us, the command can be issued. However, I need to issue the command 10ms later for the function to be turned on properly because my SPI command has an open/short circuit command detection. The second time I issue the same command every 10ms, the SPI data will display the current channel fault. The third time I issue the same command every 10ms, and the fault will disappear. What's going on? Re: MC33879 initialization voltage abnormality and slow initialization VDD is 5V Re: MC33879 initialization voltage abnormality and slow initialization It seems there are fault for open or short circuit. You may need to double check your schematics with mc33879 application diagram Does VDD connect with 5V instead of 12V? Re: MC33879 initialization voltage abnormality and slow initialization Please share your schematic.

S32K344 MDIO MDC support >2.5 MHz? The S32K344 EMAC peripheral MAC_MDIO_Address.CR field supports CSR clock dividers down to /4, for up to a 20 MHz MDC (with 80 MHz AIPS_PLAT_CLK). Many PHYs and other MDIO devices support MDC >2.5 MHz, and this can be very helpful for reducing transaction runtimes. Experimentally, we have been able to configure the S32K344 MDIO bus for this higher speed and interface with an external PHY.  However, we noticed the S32K344 datasheet ("MDIO Timing Specifications") publishes a max supported MDC frequency of just 2.5 MHz. A faster MDC would be helpful for our application; despite the datasheet specification, does the S32K344 provide any official support for running MDC >2.5 MHz? Re: S32K344 MDIO MDC support >2.5 MHz? Thank you! Re: S32K344 MDIO MDC support >2.5 MHz? Hello @andye , The EMAC register interface may allow divider settings that would nominally generate an MDC frequency above 2.5 MHz. However, for S32K344 the officially supported maximum MDC frequency is the value published in the datasheet, i.e. 2.5 MHz. Therefore, operation above this limit cannot be considered officially supported. Even if communication appears to work at a higher MDC frequency in a specific setup, this would be outside the published specification and should be treated as application-specific experimental behavior. In practice, increasing MDC reduces the available timing margin for MDIO setup/hold and output valid timing, and it also makes the interface more sensitive to the RC time constant of the MDIO line (for example due to pull-up resistance, bus capacitance, routing, and the number of attached devices).  Best regards, Pavel

mcxn947 smartdma のコード領域はどれくらいありますか? SmartDMAでアセンブリコードを実行する場合、最大コードサイズはどれくらいですか？ Re: how much code space does mcxn947 smartdma has こんにちは、 @justdomyself さん。 投稿ありがとうございます！ SmartDMAには、明確なコードサイズ仕様がありません。SmartDMAの各機能モジュールを正しく動作させるには、それぞれを固定のメモリアドレスに配置する必要があります。 SmartDMAファームウェアのインストールは、基本的にSmartDMA機能モジュールのコード配列を指定されたRAMアドレスにコピーすることから成ります。 RAMX（最大96KB）はCortex-M33コードバスに接続されており、SmartDMA機能モジュールを含むコード格納に最適なRAM領域です。 この情報がお役に立てば幸いです。

S32G3的MCAL多核配置 SOC型号：S32G399A，RTD版本4.0.2   目前我们的EB工程已经实现了在同一个M核上驱动相关外设，现在因为功能分核的需要，MCAL需要拆分到不同的M核上，比如spi_0在M7_0上使用，spi_1在M7_1上使用；     有没有MCAL的多核配置工程或者文档可供参考？ Re: S32G3的MCAL多核配置 Hi,RoseRice 很抱歉我们没有直接的例程和文档符合您的应用需求。 你可以尝试参考AN13750(AN13750: Enabling Multicore Application on S32G2 using S32G2 Platform Software Integration – Application note), 该文档内容中提供了多核启动和应用的方法，是官方推荐 multicore应用方式。 希望对您有所帮助，有任何问题随时联系。 BR Joey

S32 Design Studio License Renewal Hi NXP, My S32 Design Studio License will expire in 20 days and I would like to renew the license.  Below is the information I think you need for renewal. ActivationId: 1DF1-047B-B6E1-B256 Evaluation Days: 20 Feature Version: 2.2 Feature Status: Evaluation (20 days) Regards and thank you, Rob

S32M24xEVB 的错误 我试过该套件的示例代码，只有 S32M24xEVB_BLDC_6Step_Sensorless 能正常工作。我做错了什么？大厅给出了这些错误（缺少标头）： ....Building file: ../generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.c C:/Users/nitro/workspaceS32DS.3.5_DP_V10/S32M24xEVB_BLDC_6Step_Hall/generate/include/Adc_Ip_BOARD_INITPERIPHERALS_PBcfg.h:44:10: fatal error：Adc_Ip_Types.h：No such file or directory Building file: ../generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.c 44 | #include"Adc_Ip_Types.h" | ^~~~~~~~~~~~~~~~ 编译终止。 ../generate/src/Aec_Ip_Cfg.c:41:10: fatal error：Aec_Ip_Types.h：No such file or directory Invoking：标准 S32DS C 编译器 41 | #include"Aec_Ip_Types.h" | ^~~~~~~~~~~~~~~~ 编译终止。 make：*** [generate/src/subdir.mk:78: generate/src/Adc_Ip_BOARD_INITPERIPHERALS_PBcfg.o] ***.错误 1 make：*** Waiting for unfinished jobs.... make：*** [generate/src/subdir.mk:78: generate/src/Aec_Ip_Cfg.o] Error 1 ../generate/src/Aec_Ip_Sa_BOARD_INITPERIPHERALS_PBcfg.c:42:10: fatal error：Aec_Ip_Types.h：No such file or directory Building file: ../generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.c 42 | #include"Aec_Ip_Types.h" arm-none-eabi-gcc " @generate /src/adc_ip_board_initPeriperiperals_pbcfg.args "-MMD -MP -MF"generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.d"-MT"generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.o"-o"generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.o""../generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.c" | ^~~~~~~~~~~~~~~~ 调用：Standard S32DS C Compiler 编译终止。 调用：标准 S32DS C 编译器 make：*** [generate/src/subdir.mk:79: generate/src/Aec_Ip_Sa_BOARD_INITPERIPHERALALS_PBcfg.o] ***错误 1 arm-none-eabi-gcc " @generate /src/adc_ip_board_initPeriperherals_pbcfg.args "-MMD -MP -MF"generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALALS_PBcfg.d"-MT"generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.o"-o"generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.o""../generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.c" 在文件中包含来自.../generate/src/cdd_gdu_board_initPeriperiperals_pbcfg.c:43: arm-none-eabi-gcc " @generate /src/adc_ip_board_board_initPeriperherals_pbcfg.args " -MMD -MP -MF"generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALALS_PBcfg.d"-MT"generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.o"-o"generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.o""../generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.c" C:/Users/nitro/workspaceS32DS.3.5_DP_V10/S32M24xEVB_BLDC_6Step_Hall/generate/include/Gdu_Ip_BOARD_INITPERIPHERALS_PBcfg.h:46:10: fatal error：Gdu_Ip_Types.h：No such file or directory 46 | #include"Gdu_Ip_Types.h" | ^~~~~~~~~~~~~~~~ 编译终止。 make：*** [generate/src/subdir.mk:80: generate/src/CDD_Gdu_BOARD_INITPERIPHERALALS_PBcfg.o] ***Error 1 In file included from ../generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.c:41: C:/Users/nitro/workspaceS32DS.3.5_DP_V10/S32M24xEVB_BLDC_6Step_Hall/generate/include/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.h:43:10: fatal error：Dpga_Ip_Types.h：No such file or directory 43 | #include"Dpga_Ip_Types.h" | ^~~~~~~~~~~~~~~~~ 编译终止。 make：*** [generate/src/subdir.mk:80: generate/src/Dpga_Ip_BOARD_INITPERIPHERALS_PBcfg.o] ***.Error 1 In file included from C:/Users/nitro/workspaceS32DS.3.5_DP_V10/S32M24xEVB_BLDC_6Step_Hall/generate/include/Ftm_Pwm_Ip_Cfg.h:54, from ./generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.c:41: C:/Users/nitro/workspaceS32DS.3.5_DP_V10/S32M24xEVB_BLDC_6Step_Hall/generate/include/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.h:45:10: fatal error：Ftm_Pwm_Ip_Types.h：No such file or directory 45 | #include"Ftm_Pwm_Ip_Types.h" | ^~~~~~~~~~~~~~~~~~~~ 编译终止。 在从 ../generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.c:47包含的文件中： C:/Users/nitro/workspaceS32DS.3.5_DP_V10/S32M24xEVB_BLDC_6Step_Hall/generate/include/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.h:46:10: fatal error：Ftm_Gpt_Ip_Types.h：No such file or directory 46 | #include"Ftm_Gpt_Ip_Types.h" | ^~~~~~~~~~~~~~~~~~~~ 编译终止。 make：*** [generate/src/subdir.mk:80: generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALALS_PBcfg.o] *** [generate/src/Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_PBcfg.o] Make错误 1 make：*** [generate/src/subdir.mk:80: generate/src/Ftm_Gpt_Ip_BOARD_INITPERIPHERALS_PBcfg.o] ***.错误 1 " make-j8 all " 以退出代码 2 终止。版本可能不完整。 PMSM_FOC 就像是不完整的： -j8 all 无法运行程序"" ：启动失败 错误：程序"" 未在 PATH 中找到 Re: errors with S32M24xEVB HI 您是否点击了"更新代码" 按钮，参照 4.2 使用配置工具生成配置文件？ 你是否已参考 2. 获取软件 ，安装了 SW32K1_S32M24x_RTD_4.4_R21-11_2.0.0_D2308_DS_Updatesite.zip 和 SW32K1_S32M24x_RTD_R21-11_2.0.0_P04_D2404_DS_updatesite.zip（出自 S32M24X 板设置指南）？ 我能够毫无错误地构建这三个项目。 C:\NXP\MC_DevKits\S32M24xEVB\sw\S32M24xEVB_BLDC_6Step_SensorlessandS32M24xEVB_BLDC_6Step_HallandS32M24xEVB_PMSM_FOC_1Sh   你在这里下载了 S32 Design Studio-版本 & 更新了吗？ 别忘了安装 适用于 Arm 嵌入式处理器的恩智浦 GCC v10.2 版本 1728 由 S32DS 扩展和更新提供 祝好， Robin ------------------------------------------------------------------------------- 注： - 如果本帖回答了您的问题，请点击"ACCEPT AS SOLUTION" 按钮。谢谢！ - 我们会在最后一次发帖后的 7 周内跟踪主题，之后的回复将被忽略 如果您以后有相关问题，请另开新主题并参考已关闭的主题。 -------------------------------------------------------------------------------

DTM software to work with R&S CMW500 Hi all,  I would like to work on KW45B41Z-EVK board with R&S CMW500 equipment for BLE testing directly but I found the following problem on it. 1) R&S CMW500 can recognize the USB visual COM driver for the kit but I cannot find the driver file for the MCU-Link and my equipment seems to be windows based system so I need how to download windows driver for the kit. 2) For the software running in EVK, I load the example code of hci_bb_bm code on it and it can run Generic FSK connectivity test demo software thru TeraTerm and try to connect this COM port into CMW500 and the initial check on the DTM connection with equipment is passed but EVK board seems to be not able to response to read test command from equipment and then making any BLE RF PHY link testing.   Therefore, I don't sure any specific software from NXP to be fit with DTM interface with equipment directly or any advise for using hci_bb_bm software to run with DTM with standard BLE tester equipment included R&S CMW500. Kinetis K Series MCUs Re: DTM software to work with R&S CMW500 Hello, hope you are doing well!   This application note provides the RF evaluation test result of the KW45B41Z-EVK for BLE applications using the connectivity_test and HCI_bb application examples: AN13228 KW45B41Z-EVK RF System Evaluation Report for Bluetooth Low Energy Applications Also, maybe these posts could be helpful:  How to use the HCI_bb on Kinetis family products and get access to the DTM mode  This article is presenting two parts: How to flash the HCI_bb binary into the Kinetis product. Perform RF measurement using the R&S CMW270 BLE HCI Application to set transmitter/receiver test commands This article provides the steps to show how user could send serial commands to the device. Bluetooth LE HCI Black Box Quick Start Guide This article describes a simple process for enabling the user controls the radio through serial commands. Best regards, Sofia.

FRDM-IMX93 无法识别 RPI-CAM-MIPI 你好，我想让 RPI-CAM-MIPI 与 FRDM-IMX93 主板配合使用。 我遵循了主板的用户手册： https://docs.nxp.com/bundle/UM12181/page/topics/camera_module_rpi_cam_mipi.html 我按照说明连接了摄像头。 我从 ONSEMI github (https://github.com/ONSemiconductor/ap1302_binaries/tree/main/NXP_i.MX93) 那里拿到了 ap1302_60fps_ar0144_27M_2Lane_awb_tuning.bin，重命名了然后把它放进了主板： root@imx93-11x11-lpddr4x-frdm:~# ls /lib/firmware/imx/camera/ ap1302.fw 我重新启动了相机，但日志和手册上的不一样： root@imx93-11x11-lpddr4x-frdm:~# dmesg | grep ap1302 [ 0.341004] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c：修正了与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.371040] /soc@0/bus@42800000/csi@4ae00000: Fixed dependency cycle(s) with /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c [ 0.411142] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c：修正了与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.433309] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c：修复了与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.464010] /soc@0/bus@42800000/csi@4ae00000: Fixed dependency cycle(s) with /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c [ 0.476107] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c：修正了与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.495817] /soc@0/bus@42800000/csi@4ae00000: 修正了与 /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c 的依赖循环 [ 2.093316] /soc@0/bus@42800000/csi@4ae00000: 已修复与 /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c 的依赖循环 [ 2.104580] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c：修复了与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 摄像头似乎没有出现： root @imx93 -11x11-lpddr4x-frdm：~# media-ctl-p 无法枚举 /dev/media0 (-2) root @imx93 -11x11-lpddr4x-frdm：~# v4l2-ctl--list-devices mxc-isi-cap（平台：4ae40000.isi）： /dev/video0 /dev/video1 root@imx93-11x11-lpddr4x-frdm:~# i2cdetect -y 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- UU -- -- UU -- -- -- -- -- -- -- -- -- -- -- -- 30：-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- root@imx93-11x11-lpddr4x-frdm:~# 我重新检查了一切。我卡住了。有什么好办法吗？ Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 你好@jventura 您的连接是错误的，蓝色一侧应与摄像头一侧相同。 致敬， Zhiming Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 我附上了照片，但我也用万用表检查了连续性，一切正常，FRDM 上的引脚与 CAM 上的引脚相通... Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 从另一边 Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 在这里 Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 您好@jventura ，能否分享显示 RPI-CAM-MIPI 和 FRDM93 之间连接的照片？ 致敬， Zhiming Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 谢谢@Zhiming_Liu 😄 我检查了无数次，但每次都漏掉了。 总之，情况有所好转，但看来我还是遇到了.fw文件的问题： root@imx93-11x11-lpddr4x-frdm:~# dmesg | grep ap1302 [ 0.340881] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c: 已修复与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.370918] /soc@0/bus@42800000/csi@4ae00000: 已修复与 /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c 相关的依赖循环 [ 0.411017] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c: 已修复与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.433185] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c: 已修复与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.463890] /soc@0/bus@42800000/csi@4ae00000: 已修复与 /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c 相关的依赖循环 [ 0.475987] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c: 已修复与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 0.495704] /soc@0/bus@42800000/csi@4ae00000: 已修复与 /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c 相关的依赖循环 [ 2.098808] /soc@0/bus@42800000/csi@4ae00000: 已修复与 /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c 之间的依赖循环 [ 2.110107] /soc@0/bus@42000000/i2c@42530000/ap1302_mipi@3c: 已修复与 /soc@0/bus@42800000/csi@4ae00000 的依赖循环 [ 10.757527] ap1302 2-003c: 直接加载固件 ap1302_ar0144_single_fw.bin 失败，错误代码 -2 [ 10.757549] ap1302 2-003c: 将回退到 sysfs 备用方案：ap1302_ar0144_single_fw.bin [ 10.770396] ap1302 2-003c：请求固件失败： -2 [ 10.818467] ap1302 2-003c: 使用驱动程序 ap1302 进行探测失败，错误代码 -2 root@imx93-11x11-lpddr4x-frdm:~# media-ctl -p 无法枚举 /dev/media0 (-2) root@imx93-11x11-lpddr4x-frdm:~# root@imx93-11x11-lpddr4x-frdm:~# ls /lib/firmware/imx/camera/ ap1302.fw ONS EM I GitHub 上的 ap1302_60fps_ar0144_27M_2Lane_awb_tuning.文件是否 正确？ Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 嗨 @jventura ap1302_60fps_ar0144_27M_2Lane_awb_tuning.bin 是正确的。请尝试 参考手册 中的以下建议 一个名为  ap1302_ar0144_single_fw.bin  。将其放置在  /lib/firmware  文件夹下。 此致， Zhiming Re: FRDM-IMX93 not recognizing RPI-CAM-MIPI 谢谢志明，成功了！ 不过，Gopoint DMS 的演示版却无法显示……我觉得可能是媒体管道出了问题，我会查查看。

KW45 Secure Boot with no private key Hello, is there a method for authenticating images signed by external PKI? Let me explain better my question. I would like to enable secure boot by burning fuse CUST_PROD_OEMFW_AUTH_PUK with sha-256 of public key. I have the certificate with the public key provided by the OEM but I don't have the related private key because I am not the signer. I can only sign my plain test by external portal with a dedicated PKI and obtain ECDSA signature. I was referring to the following image but, assuming that i can obtain the signature, how can I know the exact tbs? in particular the data contained in the vector table? I hope I have explained my question in a good way. Thank you, Alessandro Re: KW45 Secure Boot with no private key AN14670 EdgeLock 2GO Provisioning via SPSDK for MCUs AN14624 EdgeLock 2GO Provisioning via Secure Provisioning Tool (SEC) for MCUs AN14109 KW45 and K32W148 Secure Boot Using the SEC Tool Re: KW45 Secure Boot with no private key Hi @alereale  It is possible to configure external signature provider. It is documented here: Signature provider - Generic workflows — Secure Provisioning Tool 26.03 Short story: You need to implement custom HTTP server providing the API for signing the application, the sample implementation of the server is provided as a source code. Re: KW45 Secure Boot with no private key Hi @marek-trmac Thank you for your reply. I was wondering if that is the only solution? In this way, I need to "force" the OEM to implement such a custom HTTP server. I say that because the OEM already has a server where I can upload my binary file for signing it. In general, can you confirm that the only way to enable Secure Boot in KW45 is to go through Secure Provisioning Tool? Thank you very much. Regards, Alessandro