2378631_en-US

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S32K344 MDIO MDC support >2.5 MHz?

The S32K344 EMAC peripheral MAC_MDIO_Address.CR field supports CSR clock dividers down to /4, for up to a 20 MHz MDC (with 80 MHz AIPS_PLAT_CLK). Many PHYs and other MDIO devices support MDC >2.5 MHz, and this can be very helpful for reducing transaction runtimes. Experimentally, we have been able to configure the S32K344 MDIO bus for this higher speed and interface with an external PHY. 

However, we noticed the S32K344 datasheet ("MDIO Timing Specifications") publishes a max supported MDC frequency of just 2.5 MHz.

A faster MDC would be helpful for our application; despite the datasheet specification, does the S32K344 provide any official support for running MDC >2.5 MHz?

Re: S32K344 MDIO MDC support >2.5 MHz?Thank you!Re: S32K344 MDIO MDC support >2.5 MHz?

Hello @andye ,

The EMAC register interface may allow divider settings that would nominally generate an MDC frequency above 2.5 MHz. However, for S32K344 the officially supported maximum MDC frequency is the value published in the datasheet, i.e. 2.5 MHz. Therefore, operation above this limit cannot be considered officially supported.

Even if communication appears to work at a higher MDC frequency in a specific setup, this would be outside the published specification and should be treated as application-specific experimental behavior.

In practice, increasing MDC reduces the available timing margin for MDIO setup/hold and output valid timing, and it also makes the interface more sensitive to the RC time constant of the MDIO line (for example due to pull-up resistance, bus capacitance, routing, and the number of attached devices). 

Best regards,

Pavel