PF81 PF82 PMIC - プロセスノードとテクノロジーの詳細 こんにちは、 現在、NewSpace LEO アプリケーション向けに PF8100/PF8200 PMIC を評価しており、放射線分析と信頼性評価のための製造プロセスの詳細をより深く理解したいと考えています。 NXP の担当者から以下の情報をご提供いただけますか。 * プロセス ノード (例: 180nm、130nm、その他)? * 使用されているプロセス テクノロジー (例: BCD、FDSOI、バルク CMOS)? PF8200 は ISO 26262 ASIL-B(D) 準拠のオートモーティブ アプリケーション向けに設計されており、堅牢なプロセス制御が可能で、LEO での短期ミッションに適しています。 この情報が NDA の対象である場合は、公式チャネルを通じて喜んで話し合います。 PF8200 | PF8100 i.MX用PMIC Re: PF81 PF82 PMIC - Process Node and Technology Details エリカCさん この短い情報で十分だと思います。今後数年のうちに、LEO ミッションから得られた IC の放射線耐性データを公開できるようになることを願っています。 どうもありがとう！ マチェイ Re: PF81 PF82 PMIC - Process Node and Technology Details こんにちは、 このコミュニティ チャネルでは詳細な情報を共有できないことをご了承ください。 要求した情報は次のとおりです: CMOS の場合は 130 nm。 さらに詳しい情報が必要な場合は、サポート チケットを開いて、さらにサポートを受けてください。 https://www.nxp.com/support/support:SUPPORTHOME ご理解のほどよろしくお願いいたします。

FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Zephyr 4.3.0 MCUExpresso SDK 2.16 Application note used for Example AN14196 Board used mcx_n9xx_evk/mcxn947/cpu0 Description: I am trying to replicate an NXP SDK FlexPWM example in Zephyr OS. The main goal is to reproduce the SDK behavior where: A simple PWM signal is generated using the FlexPWM peripheral. A callback (interrupt handler) is executed after a specified number of PWM edges are counted(Via E-capture). SDK Behavior (Working): Using the SDK pwm.c example, the PWM signal is generated correctly. The FlexPWM interrupt fires as expected. The callback function executes once the configured number of edges is reached. Zephyr Behavior (Issue): Using Zephyr, I am able to successfully generate the PWM signal with the FlexPWM peripheral. However, the FlexPWM interrupt is never triggered , and the callback function is never executed. (IRQ_CONNECT(120, 0, FLEXPWM1_SUBMODULE0_IRQHandler, NULL, 0); was used to connect the interrupt line to IRQHandler  ) Debugging and Investigation Done So Far: I compared the FlexPWM register configurations between: The SDK example (pwm.c) The Zephyr application (main.c) All relevant register values appear to match during the peripheral setup phase. I disabled Zephyr power management to ensure the CPU is not entering a low-power state by adding following configs    CONFIG_PM=n CONFIG_PM_DEVICE=n This change did not affect the behavior—the interrupt is still not triggered. PWM output on the pin is correct, which suggests the peripheral clocking and basic configuration are working. Question / Request for Help: Are there any Zephyr-specific requirements for enabling FlexPWM interrupts (e.g., IRQ configuration, ISR registration, clock gating, or NVIC setup) that differ from the SDK? Is there anything additional that must be done in Zephyr to ensure FlexPWM interrupts are properly routed and handled? Are there known limitations or missing support for FlexPWM edge-count interrupts in Zephyr? Any guidance on how to correctly enable and handle FlexPWM interrupts in Zephyr would be greatly appreciated. Thank you. Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hello @wima88  After building, please check the .config file to confirm that the interrupt is enabled. Also you can send it to me, I help you check.   Thank you.    BR Alice     Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hi Alice ,  I Scan the .config and could not find any red flags their. I upload the .config as well(had to rename since .config is not supported).  After further investigation into the Zephyr base setup, I noticed the following behavior difference between Zephyr and the MCUX SDK: Even though the FlexPWM register configuration and values are identical between Zephyr and the SDK, the interrupt is never triggered by the peripheral itself in Zephyr after initialization. In the MCUX SDK, I can observe that the SM0STS register bits CFB0 and CFB1 are being set periodically, which results in the expected interrupt behavior. In Zephyr, these same status bits (SM0STS->CFB0 and SM0STS->CFB1) are never set, even though: The peripheral setup is identical The PWM output is correct During the initial peripheral setup, these bits are automatically set once on both the SDK and Zephyr sides, and both environments execute the IRQ handler once during this initial setup. However, after this initial IRQ execution, the interrupt status bits are never toggled again in Zephyr, and no further interrupts occur. In contrast, the MCUX SDK continues to toggle these status bits periodically as expected, resulting in repeated interrupt callbacks. This suggests that while the initial interrupt path is functional in Zephyr, the FlexPWM peripheral does not continue generating interrupt events afterward, despite identical register configuration. Any insight into why the FlexPWM status bits (CFB0/CFB1) are not being set in Zephyr, or whether additional Zephyr-specific handling is required to enable periodic interrupt generation, would be greatly appreciated. Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hello @wima88  Thanks for your patience. I confirmed with our internal Zephyr expert. In your project, you are using the MCUXpresso SDK driver instead of the Zephyr driver. This may cause potential conflicts. Your application uses Flexcomm1 submodule 0, which is also enabled in the Zephyr devicetree for the FRDM‑MCXN947 board. If it is enabled, Zephyr will initialize the FlexPWM driver in the startup code before main() executes. Therefore, if you choose to configure FlexPWM in your application as you are doing now, you should disable the FlexPWM node in the devicetree to avoid conflicts. Thank you. BR Alice Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Thank you. I understand that their may be a conflict because Zephyr initializes the FlexPWM driver before main() executes. However, I need to verify something: if I'm correct, Zephyr's devicetree is also handling the pin mux configuration through pinctrl. If I disable the flexpwm1 node in the devicetree to avoid the conflict, would I then need to manually set up the pin mux configuration in my application code, or will the pinctrl settings remain active even with the node disabled?   Wimansha  Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hello @wima88  ”if I'm correct, Zephyr's devicetree is also handling the pin mux configuration through pinctrl. If I disable the flexpwm1 node in the devicetree to avoid the conflict, would I then need to manually set up the pin mux configuration in my application code, “ ->> Yes. BR Alice

KV5 DMA 和 UART 早上好 我导入了使用 UART 和 DMA 的示例。原始示例中使用的是 UART0。它很管用。我改用其他端口，现在试着用 UART4，但不行。我能看到 TX 结束时调用了回调，但 RX 结束时从未调用过回调。我不明白你的意思。我确信引脚和连接都没问题。我正在使用 KV5 的塔式系统。 我在这里提供一个稍作修改的示例，用于更改 UART。 欢迎提供一切帮助 谢谢 Pietro Re: KV5 DMA and UART 你好，皮耶罗 能否帮助我们确认您使用的是哪个 UART-DMA 示例，以及是哪个版本的 SDK？ 您能帮助我们分享您的联系吗？ 最诚挚的问候，路易斯 Re: KV5 DMA and UART 文件在这里。

SJA1105 in Linux, all 5 ports through PHY interfaces? Hi, I'm working on a project based around a SMARC format computer-on-a-module with a Rockchip RK3399 CPU. On the same motherboard we have a SJA1105 switch. The CPU runs Linux (5.4) and uses the NET_DSA_SJA1105 driver. Our CPU needs to communicate with other devices over Ethernet so the CPU needs to be connected to the switch. In the SJA1105 datasheet and in the Linux kernel device tree examples the host cpu is always connected to the switch as a fixed link directly over xMII. (https://www.kernel.org/doc/Documentation/devicetree/bindings/net/dsa/sja1105.txt) We cannot do this as our SMARC module only gives us pin output from the RK3399 Ethernet integrated PHY, we do not have physical access directly to the xMII interface on the CPU no matter how much we would want to. Also in the SJA1105 datasheet it says the following: "Note that Ethernet connectivity to the host processor is only needed if the system has to support AVB operation or other bridge management protocols such as STP/RSTP. If such operations are not needed, all the ports can be used for data traffic." Since we don't need AVB or STP/RSTP and since we anyway don't have access to the cpu xMII interface we have decided to just use the switch as a normal 5-port switch with PHY interfaces on every port. 4 ports where the PHY's actually goes to real RJ45 connectors and one port where the PHY is hardwired in the circuit board to the PHY that we get from our CPU on the SMARC board. This would give us a Linux device tree looking something like this: (only SJA1105 relevant part shown, indentation also became screwed when pasted here) &spi2 { status = "okay"; #address-cells = <1>; #size-cells = <0>; num-cs = <2>; cs-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>, <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; sja1105_1: sja1105@1 { status = "okay"; reg = <1>; #address-cells = <1>; #size-cells = <0>; clocks = <&ethswitch_osc>; compatible = "nxp,sja1105t"; spi-max-frequency = <25000000>; fsl,spi-cs-sck-delay = <1000>; fsl,spi-sck-cs-delay = <1000>; spi-cpha; pinctrl-names = "default"; pinctrl-0 = <&ethswitch_pins>; reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { /* Implicit "sja1105,role-mac;" */ label = "eth0"; phy-handle = <&rmii_phy0>; phy-mode = "rmii"; reg = <0>; }; port@1 { /* Implicit "sja1105,role-mac;" */ label = "lan1"; phy-handle = <&rmii_phy1>; phy-mode = "rmii"; reg = <1>; }; port@2 { /* Implicit "sja1105,role-mac;" */ label = "lan2"; phy-handle = <&rmii_phy2>; phy-mode = "rmii"; reg = <2>; }; port@3 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy3>; label = "lan3"; phy-mode = "rmii"; reg = <3>; }; port@4 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy4>; label = "lan4"; phy-mode = "rmii"; reg = <4>; }; }; }; }; This devicetree is valid and compiles, however during the probe the NET_DSA_SJA1105 fails because it cannot find a HOST CPU port (as we have not specified one). This error comes from net/dsa/dsa2.c *dsa_tree_find_first_cpu(struct dsa_switch_tree *dst) so it's not specific to sja1105 part of the driver but rather deeper in the Linux Distributed Switch Architecture. In all devicetree examples there is always one port configured as host cpu connected with fixed link over xMII, for example like this: port@4 { /* Internal port connected to eth2 */ ethernet = <&enet2>; phy-mode = "rgmii"; reg = <4>; /* Implicit "sja1105,role-phy;" */ fixed-link { speed = <1000>; full-duplex; }; }; If I try to modify my device tree to have the ports look something more like this: ports { #address-cells = <1>; #size-cells = <0>; port@0 { /* Implicit "sja1105,role-phy;" */ ethernet = <&gmac>; phy-mode = "rmii"; reg = <0>; fixed-link { speed = <100>; full-duplex; }; }; port@1 { /* Implicit "sja1105,role-mac;" */ label = "lan1"; phy-handle = <&rmii_phy1>; phy-mode = "rmii"; reg = <1>; }; port@2 { /* Implicit "sja1105,role-mac;" */ label = "lan2"; phy-handle = <&rmii_phy2>; phy-mode = "rmii"; reg = <2>; }; port@3 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy3>; label = "lan3"; phy-mode = "rmii"; reg = <3>; }; port@4 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy4>; label = "lan4"; phy-mode = "rmii"; reg = <4>; }; }; Then the driver is satisfied and probes successfully and sets up the SJA1105 switch. Ports 1-4 work but port 0 (where CPU is connected via a PHY) does of course not work as it's now configured as xMII would be directly connected to it when in reality we have a PHY there in between the SJA1105 and the host CPU. Is this a limitation the the DSA SJA1105 Linux driver, that you always must configure a fixed link over xMII? Can I somehow configure directly from the device tree that i DO NOT wish to have a dedicated cpu host port at all but rather just 5 normal ports (of which one then happens to so be connected to the CPU via a PHY...) Or can I configure the CPU host port to be there as a fixed-link, but explicitly specify that there is actually a PHY there also and not a xMII interface? I have tried dozens and dozens of combinations and still not found any way to configure this so that it will work with our supposedly very simple setup. Am I just missing something really obviously simple here? Any ideas how to proceed? Or is this just not possible with the Linux DSA SJA1105 driver? Regards Re: SJA1105 in Linux, all 5 ports through PHY interfaces? @kalamata @Sabeur were you able to arrive at a solution to this issue. I am running into a similar situation with Toradex imx8mp SoM.  Re: SJA1105 in Linux, all 5 ports through PHY interfaces? @kalamata @Sabeur Did you arrive at a solution to this issue? I am running in a similar problem but with Toradex Verdin IMx8mp SoM. Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi,  I see the phy-mode and phy-handle for the port 0: port@0 { /* Implicit "sja1105,role-mac;" */ ethernet = <&gmac>; label = "eth0"; phy-handle = <&rmii_phy0>; phy-mode = "rmii"; reg = <0>; }; This is how the device tree should look like. Also, the gmac node should contain &gmac {     phy-handle = <&rmii_gmac_phy>;     phy-mode = "rmii"; }; best regards, Sabeur Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi Kalamata,  Thanks for the details.  So my assumptions were correct.  You should be able to specify phy-handle and phy-mode for the connected MAC interfaces. It was tested virtually, means MAC -> PHY - > --- <- PHY <- MAC from 5.3 Kernel version. (see 0e27921816ad99f78140e0c61ddf2bc515cc7e22). So this is the right way to describe this kind of HW connection in the device tree. Regards,  Sabeur Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi Sabeur, Thank you for the reply! Is the above data path possible in your setup ? Yes, we are using exactly that setup: (CPU) Mac - Phy - Phy - Switch Mac (see attachments) Has the Rockchip RK3399 CPU an internal PHY ? Yes, it has an internal PHY, and we are stuck using this internal PHY, as it's the only thing coming out from the Advantech ROM-5780 SMARC module where our CPU is located, so we could not use the CPU MAC interface directly even if we wanted to. See attached pictures for how our setup differs from the typical setup suggested by the SJA1105 datasheet. We have an Advantech ROM-5780 Computer-on-a-chip module (i.e. a Rockchip RK3399 CPU) packaged in SMARC format. The Rockchip RK3399 has an integrated PHY interface and that is what we have access to on the output pins on the SMARC module. We do NOT have physical access to the MAC pins of the RK3399 Ethernet controller as they are not coming out via the SMARC module, so we are stuck using the RK3399 PHY interface. Therefore on the 5:th port on the SJA1105 where we intend to connect our CPU we have a PHY controller (just like we have on ports 1-4) and that PHY controller is permanently wired to the PHY controller coming out of the RK3399 CPU. Regards, Kalamata Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi, Theoretically it should be possible however, i will not work out of the box because the expected setup is to have a direct link. The data path which can work is: Mac - Phy - Phy - Switch Mac. In this case you will need to modify the DSA kernel and specify Phy handle and Phy mode for both CPU Mac and Switch Mac. Now the question is: is the above data path possible in your setup ? Has the Rockchip RK3399 CPU an internal PHY ? Best regards, Sabeur Re: SJA1105 in Linux, all 5 ports through PHY interfaces? The PHY-to-PHY back to back is possible. You have to use the phy-handle property. You can also bypass auto-negotiation and set a fix speed with the "fixed-link" property in devicetree bindings. If you are having problem and you suspect your devicetree configuration is correct, kindly check the control path interface (SPI/I2C/MDIO).

iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi，NXP支持专家， 我们参考iMX93EVK 设计了一块板子，只使用了LVDS连接LCD，请问：   uboot传什么启动参数 bootargs 到Linux kernel?   怎么修改 include\configs\imx93_evk.h ? Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi Zhiming_Liu, uboot指定一下fdtfile就行 请问怎么修改代码来实现 指定 fdtfile呢？谢谢 Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  uboot里只需要指定内核使用的fdtfile为这个dtb就行。不需要其他参数。另外这个里面的屏幕参数需要根据实际的屏幕改一下。menuconfig不需要改，如果简单一点的话，你就直接改imx93-11x11-evk-boe-wxga-lvds-panel.dts，然后uboot指定一下fdtfile就行。 Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi Zhiming_Liu,     你好，      Hi, 你们想要内核使用LVDS对吗？ 如果是想要驱动内核里的LVDS，参考内核设备树就行。 linux-imx/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts     我们想通过LVDS显示，不太明白你的回答。 1. 我们的iMX6DL板子，通过LVDS显示，uboot传bootargs包含 video 参数，iMX93的uboot不需要传video参数吗？ 2.  imx93-11x11-evk-boe-wxga-lvds-panel.dts需要修改吗？  把imx93-11x11-evk-boe-wxga-lvds-panel.dts编译成 dtb，只烧录这1个dtb文件到 EMMC ？ 编译 Linux Kernel ,  menuconfig  需要修改吗？ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, 你们想要内核使用LVDS对吗？ 如果是想要驱动内核里的LVDS，参考内核设备树就行。 linux-imx/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts at lf-6.12.y · nxp-imx/linux-imx Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 嗨， @Zhiming_Liu ， uboot 规范 fdtfile imx93-11x11-evk-boe-wxga-lvds-panel.dtb，显示屏自由格式，波形显示量 lvds 时钟拉腿，无时间波形（所有信号均为波形） Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, @Zhiming_Liu       我们板子的 DDR 与NXP iMX93EVK同型号，只是容量为 1GB（EVK 为2GB）， u-boot imx93_evk.h #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 改成了 1GB DDR */  还是 DDR: 3733MTS Training FAILED 能不能禁用这个DDR校准？ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  你们用的对应引脚都正确设置了吗？上电过程正确吗？ Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  布线不同也需要重新校准。 Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  出现这个错Training FAILED说明是DDR校准有问题。如果你们不是EVK，需要通过Config Tool校准并生成新的DDR时序文件，然后替换进uboot里的DDR时序。Config Tool的使用可以参考这个文章：https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX93-DDR-setting-and-config-tool-usage/ta-p/1759391 Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, @Zhiming_Liu ,    LVDS信号线连接正确，LCD屏连接 iMX6DL 能正常显示。  不管是 u-boot 2023.04还是 2025.04， make imx93_9x9_qsb_defconfig配置，然后编译后，用imx-mkimage生成flash.bin 才能在我们的板子上启动，我们参照 iMX93EVK设计的硬件原理图。 使用 make imx93_11x11_evk_defconfig配置，就会出现如下错误，M33 prepare ok 后就没有输出信息了。  U-Boot SPL 2023.04 (Jan 13 2026 - 10:22:53 +0800) SOC: 0xa1009300 LC: 0x2040010 PMIC: Over Drive Voltage Mode DDR: 3733MTS Training FAILED M33 prepare ok    Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 你好，@刘志明 U-Boot 2025.04-g4ddbad60eff3-dirty(Jan 14 2026 - 11:05:46 +0800) RESET 状态：POR CPU：1700 MHz 时的恩智浦 i.MX93 (52) Rev1.1 A55 CPU：33C 时的工业温度等级（-40C 至 105C）型号：恩智浦 i.MX93 11X11 EVK 主板 动态随机存取存储器(DRAM)：1 GiB optee optee：OP-TEE api uid 不匹配 optee 由 NXP yocto 生成，怎么修改这个 api uid 不匹配，谢谢？ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  现在板子起来的了吗？能正常进入内核了吗？ Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, @Zhiming_Liu  能够正常挂载 rootfs。 请教另一个问题， 我们板子上的 EMMC 是 8GB，但是文件系统只使用了4GB，想把另外的4GB用来存数据， 使用NXP yocto制作rootfs时，是不是能把文件系统占用的空间改大到8GB， 还是有另外的方法能够使用剩余的4GB ?  谢谢 root@imx93evk:/# fdisk -l Disk /dev/mmcblk0: 7.28 GiB, 7818182656 bytes, 15269888 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: dos Disk identifier: 0x076c4a2a Device Boot Start End Sectors Size Id Type /dev/mmcblk0p1 * 16384 540671 524288 256M c W95 FAT32 (LBA) /dev/mmcblk0p2 540672 7835157 7294486 3.5G 83 Linux ------------------------------------------------------------------ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  在conf/local.conf中使用下面的宏： IMAGE_ROOTFS_EXTRA_SPACE = "4000000" https://docs.yoctoproject.org/singleindex.html#term-IMAGE_ROOTFS_EXTRA_SPACE Best Regards, Zhiming

frequency measurement example code for the s32k3xx Hi all, I am working with an S32K3 series MCU and I want to measure the frequency of an external signal coming on a GPIO pin using the eMIOS peripheral. I have checked the S32K3 reference manual, S32 Design Studio, MCUXpresso Config Tools, and available SDK examples, but I could not find any clear documentation or example that explains how to configure eMIOS for frequency measurement, including pin routing, channel mode selection, clock configuration, or the required settings in the .mex file. I would appreciate it if you could guide me on the correct eMIOS mode to use for this purpose or share any reference example, code snippet, or configuration screenshot that demonstrates a working frequency measurement setup on S32K3. Re: frequency measurement example code for the s32k3xx Hi Please refer to these examples for configuring eMIOS in IPWM mode: Example S32K344 eMIOS DS3.5 RTD500 S32K344_Example_Emios_Icu_IPWM_measurement_DS34_RTD_100_v2 Example IP S32K312 EMIO PWM Generation & Duty capture using Polling DS3.5 RTD300 Example IP S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300 Example ASR S32K312 EMIO PWM Generation & Duty capture using Polling DS3.5 RTD300 Example ASR S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300 Please note that the S32K3 projects are usually used with S32DS(S32 Configuration Tool) or EBTresos as configuration tools, and not with MCUXpresso Config Tools. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: frequency measurement example code for the s32k3xx Hi @Robin_Shen, I am using the Example S32K344 eMIOS DS3.5 RTD500 as my base code. I modified the project to measure input frequency by configuring eMIOS_1 Channel 7 as an input (IPWM mode). I updated the S32 Configuration Tool accordingly and added the required changes in the main file. I am reading the measured value using the Ipwm_duty_cycle_array(checked inside the watchdog task). However, even when no external signal is applied on PTA24, the measured value is always 100. Could you please explain why a constant value is reported without any input signal? Is this expected behavior due to default pin state, internal pull-up, clock source, or IPWM configuration? I have attached snapshots for reference. Re: frequency measurement example code for the s32k3xx If you want to use polling method instead of interrupt method, please poll the status via Emios_Icu_Ip_GetInputState before calling Emios_Icu_Ip_GetDutyCycleValues. while(TRUE != Emios_Icu_Ip_GetInputState(INSTANCE_1, CHANNEL_7)){} Emios_Icu_Ip_GetPulseWidth(INSTANCE_1, CHANNEL_7); Emios_Icu_Ip_GetDutyCycleValues(INSTANCE_1, CHANNEL_7, &Ipwm_duty_cycle); Ipwm_duty_cycle_array[index] = (Ipwm_duty_cycle.ActiveTime * 100) / Ipwm_duty_cycle.PeriodTime; Re: frequency measurement example code for the s32k3xx Hi @Robin_Shen , As I want to use interrupt-based measurement, I unchecked IcuSignalMeasureWithoutInterrupt (please refer to the image below) and modified the main.c according to the interrupt-based example code. Currently, the IRQ handler is triggered, which confirms that the interrupt configuration is working. However, the measured ActiveTime and Period Time values are always 0. Could you please help explain why the interrupt is generated but both timing values remain zero? Is this related to IPWM mode configuration, edge selection, signal level on the pin, or missing ICU start/notification API calls? I have attached the configuration snapshot for reference. In this code same as the example code but I just changed the channel 5 instead of 7. Re: frequency measurement example code for the s32k3xx This seems similar to the discussion in the S32K344 MCAL IPWM ICU CAPTURE: Please call Emios_Icu_Ip_IrqHandler first, and then call Emios_Icu_Ip_GetDutyCycleValues. Re: frequency measurement example code for the s32k3xx Hi @Robin_Shen , Thank you for the clarification, the issue is resolved now and the interrupt-based measurement is working as expected.I have one additional question. I want to know how to run the eMIOS module using an external clock source? Could you please guide me on what key configuration changes are required for this? Re: frequency measurement example code for the s32k3xx You are welcome.  I may not have understood your question. Please correct me if I am wrong. I see that your Emios_Icu has IcuEmiosBusSelect set to EMIOS_ICU_BUS_A. Would you like to change it to something else? By the way, the S32K3_RTD_Training_eMIOS_public.pdf file in the S32K311 EMIOS GPT might be helpful to you. Please post a new question in community you have any questions that are not related to the original topic of an existing case. It helps to keep it clear. Re: frequency measurement example code for the s32k3xx Hi @Robin_Shen , I am trying to measure input frequency on multiple eMIOS channels. When I configure and enable only one channel, the project builds and works correctly. However, when I enable a second eMIOS/ICU channel for frequency measurement, I immediately get configuration errors and the project fails to build. I have attached a screenshot of the configuration error for reference. Re: frequency measurement example code for the s32k3xx Hi @Robin_Shen,  I am trying to measure the input frequency on PTE25 (eMIOS1 Channel 5). I am applying a 10 Hz signal from a DSO, and I have verified that the input signal is stable. However, the measured frequency value is unstable and fluctuates around 900–1200, even though the input is only 10 Hz. To debug this, I changed the IcuSignalMeasurementProperty to ICU_PERIOD_TIME and updated the IRQ handler as shown below: void EMIOS1_4_IRQ_Customized(void) {     Emios_Icu_Ip_IrqHandler(1, 5);     period_time = Emios_Icu_Ip_GetTimeElapsed(1, 5);     if (period_time)    {         uint64_t emios_freq = 48000000ULL; // hardcoded         signal_frequency = emios_freq / period_time; captured = 1;    } } Even after these changes, the frequency value remains unstable. Could you please help me understand why the measured frequency is incorrect and unstable for a low-frequency input, and what configuration changes are required to correctly measure a 10 Hz signal using eMIOS/ICU?   Re: frequency measurement example code for the s32k3xx I will be on leave until February 2nd. I suggest you post a new question; my colleague will provide technical support. Thank you for your understanding.

IMX8MP - No audio during playback with SOF sound card Hi, I am trying to run playback using the SOF sound card on the IMX8M Plus EVK, but I am not able to hear any audio from the headphone jack. Here are the steps I am using to run the playback: Boot the device and interrupt to enter uboot Use "editenv fdtfile" and change the device tree name to "imx8mp-evk-sof-wm8960.dtb" Continue the boot Run "aplay -l" to obtain SOF sound card ID Run the following commands to initiate playback: amixer -c [sof_card_id] cset name="Left Output Mixer PCM Playback Switch" on amixer -c [sof_card_id] cset name="Right Output Mixer PCM Playback Switch" on aplay -Dhw:[sof_card_id],0 [path_to_wav_file] The wav file used in this case is 32 bit, 48Khz stereo. I see no error when running the playback command. I have also tried playing the same wav file using the default device tree and the wm8960 sound card, and I am able to hear the output. Please let me know what I can do to solve this issue. i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Multimedia Re: IMX8MP - No audio during playback with SOF sound card Hi @aporter28  Did you refer this guide? SOF User Guide on NXP i.MX8 platforms — SOF Project 2.11.0 documentation Best Regards, Zhiming Re: IMX8MP - No audio during playback with SOF sound card That worked great, thanks! I am currently just exploring the capabilities of SOF on NXP boards. Re: IMX8MP - No audio during playback with SOF sound card Hello @aporter28 , On my setup the control you want to modify is named 'Headphone'. Assuming SOF card number is 0 please try this. amixer -c 0 sset Headphone 80% Also you can use the alsamixer TUI and modify the Headphone control Can you share with us what project are you working on with the Sound Open Firmware? 

i.MX RT1060 QTMR 级联模式，带输入捕获-无上限 当级联两个 TMR 通道用于 32 位计数器时，我似乎无法正常进行输入捕获。仅使用一个通道时，输入捕获可以正常工作，但当我尝试级联通道时却无法正常工作。 1.定义了 TMR1 ch0 和 ch1 结构。TMR1 ch0 时钟源为 kQTMR_ClockDivide_1，TMR2 ch1 时钟源为 kQTMR_ClockCounter0，输出 2. qtmr_begin 初始化通道。它们被设置为自由运行。TMR1 IRQ 已启用。为输入捕获启用 TMR1 中断。计时器启动。 当我调用 getCount 时，上层计数（通道 1）只能得到 0。否则，如果我忽略上面的计数，下面的计数总是正确的。 const qtmr_config_t QuadTimer_1_Channel_0_config = { .primarySource = kQTMR_ClockDivide_1, .secondarySource = kQTMR_Counter0InputPin, .enableMasterMode = false, .enableExternalForce = false, .faultFilterCount = 0, .faultFilterPeriod = 0, .debugMode = kQTMR_RunNormalInDebug }; const qtmr_config_t QuadTimer_1_Channel_1_config = { .primarySource = kQTMR_ClockCounter0Output, .secondarySource = kQTMR_Counter0InputPin, .enableMasterMode = false, .enableExternalForce = false, .faultFilterCount = 0, .faultFilterPeriod = 0, .debugMode = kQTMR_RunNormalInDebug }; void qtmr_begin() { QTMR_Init(TMR1, kQTMR_Channel_0, &QuadTimer_1_Channel_0_config); QTMR_Init(TMR1, kQTMR_Channel_1, &QuadTimer_1_Channel_1_config); /* Ensure free-running (no stop at compare) */ TMR1->CHANNEL[kQTMR_Channel_0].CTRL &= ~TMR_CTRL_LENGTH_MASK; TMR1->CHANNEL[kQTMR_Channel_1].CTRL &= ~TMR_CTRL_LENGTH_MASK; /* Setup the input capture */ QTMR_SetupInputCapture(TMR1, kQTMR_Channel_0, QTMR_CounterInputPin, false, true, kQTMR_RisingEdge); /* Enable at the NVIC */ EnableIRQ(TMR1_IRQn); /* Enable timer compare interrupt */ QTMR_EnableInterrupts(TMR1, kQTMR_Channel_0, kQTMR_EdgeInterruptEnable); QTMR_StartTimer(TMR1, kQTMR_Channel_0, kQTMR_PriSrcRiseEdge); QTMR_StartTimer(TMR1, kQTMR_Channel_1, kQTMR_CascadeCount); } void TMR1_IRQHandler(void) { QTMR_ClearStatusFlags(TMR1, kQTMR_Channel_0, kQTMR_EdgeFlag); qtmrIsrFlag = true; } void getCount(void) { // Discard the first capture for (int i = 0; i < 2; i++) { while (!qtmrIsrFlag) { } qtmrIsrFlag = false; uint16_t lowerCount = TMR1->CHANNEL[kQTMR_Channel_0].CAPT; uint16_t upperCount = TMR1->CHANNEL[kQTMR_Channel_1].HOLD; uint32_t counterValue = ((uint32_t)upperCount << 16) | lowerCount; } } i.MX RT106x Re: i.MX RT1060 QTMR Cascade mode w/ Input Capture - No Upper Count 我在某种程度上已经明白了这一点。我使用了错误的寄存器来读取上部（通道 1）的计数。HOLD 寄存器不保存级联通道的计数，它用于存储特定事件期间的计数器值，无论是硬件还是软件，通常用于同步事件或保存先前的值等。 我应该只是读取 CNTR 寄存器。我可以在 IRQ 处理程序中或之后立即读取，然后同步到低 16 位。 不过，我发现还有一个问题不明白。如果我将频道 1 计时器 RESET 为 0，则计数始终从 1 开始，而不是 0。因此，（通道 1）上限计数的捕获时间总是偏差 1。为了补偿，我必须将通道 1 计数器 RESET 为 0xFFFF 才能获得正确的计数。为什么？ const qtmr_config_t QuadTimer_1_Channel_0_config = { .primarySource = kQTMR_ClockDivide_1, .secondarySource = kQTMR_Counter0InputPin, .enableMasterMode = false, .enableExternalForce = false, .faultFilterCount = 0, .faultFilterPeriod = 0, .debugMode = kQTMR_RunNormalInDebug }; const qtmr_config_t QuadTimer_1_Channel_1_config = { .primarySource = kQTMR_ClockCounter0Output, .secondarySource = kQTMR_Counter0InputPin, .enableMasterMode = false, .enableExternalForce = false, .faultFilterCount = 0, .faultFilterPeriod = 0, .debugMode = kQTMR_RunNormalInDebug }; void qtmr_begin() { QTMR_Init(TMR1, kQTMR_Channel_0, &QuadTimer_1_Channel_0_config); QTMR_Init(TMR1, kQTMR_Channel_1, &QuadTimer_1_Channel_1_config); /* Ensure free-running (no stop at compare) */ TMR1->CHANNEL[kQTMR_Channel_0].CTRL &= ~TMR_CTRL_LENGTH_MASK; TMR1->CHANNEL[kQTMR_Channel_1].CTRL &= ~TMR_CTRL_LENGTH_MASK; /* Setup the input capture */ QTMR_SetupInputCapture(TMR1, kQTMR_Channel_0, QTMR_CounterInputPin, false, true, kQTMR_RisingEdge); /* Enable at the NVIC */ EnableIRQ(TMR1_IRQn); /* Enable timer compare interrupt */ QTMR_EnableInterrupts(TMR1, kQTMR_Channel_0, kQTMR_EdgeInterruptEnable); QTMR_StartTimer(TMR1, kQTMR_Channel_1, kQTMR_CascadeCount); QTMR_StartTimer(TMR1, kQTMR_Channel_0, kQTMR_PriSrcRiseEdge); } void TMR1_IRQHandler(void) { QTMR_ClearStatusFlags(TMR1, kQTMR_Channel_0, kQTMR_EdgeFlag); qtmrIsrFlag = true; } void getCount(void) { // Discard the first capture uint16_t lowerCount; uint16_t upperCount; uint32_t counterValue; for (int i = 0; i < 2; i++) { /* Reset channel 1 count to 0 - for some reason we have to reset to one value before or the count is off by 1...so we reset to 0xFFFF */ TMR1->CHANNEL[kQTMR_Channel_1].CNTR = 0xFFFF; while (!qtmrIsrFlag) { } qtmrIsrFlag = false; lowerCount = TMR1->CHANNEL[kQTMR_Channel_0].CAPT; upperCount = TMR1->CHANNEL[kQTMR_Channel_1].CNTR; counterValue = ((uint32_t)upperCount << 16) | lowerCount; } } Re: i.MX RT1060 QTMR Cascade mode w/ Input Capture - No Upper Count 嗨@azone， 非常感谢您关注我们的产品并使用我们的社区。 我根据你关于使用QTMR Cascade模式和输入捕获的问题进行了验证测试。 硬件：MIMXRT1060-EVKB , 将输入信号连接至 J33-6。 软件：QTMR3 通道 0 和通道 1 配置为级联模式 使用此设置，当计数器级联时，输入捕获可以正常工作。 设置 Edge 中断标志后，您可以读取捕获寄存器： board_qtmr_baseaddr->channel[board_qtmr_input_capture_channel0].capt； 和 BOARD_QTMR_BASEADDR->CHANNEL[BOARD_QTMR_INPUT_CAPTURE_CHANNEL1].CAPT； 顺祝商祺！ MayLiu Re: i.MX RT1060 QTMR Cascade mode w/ Input Capture - No Upper Count 你好@azone、 感谢您提供的最新信息。 关于你的新问题，我也为你做了一个测试。 输入频率为 1kHz 的信号和频率为 150MHz 的 TMR 时钟，可以得到正确的数值。 硬件：MIMXRT1060-EVKB，我向 J33-6 输入 1KHZ 信号。 SW: 请参阅我之前的帖子。 致以最崇高的敬意 MayLiu Re: i.MX RT1060 QTMR Cascade mode w/ Input Capture - No Upper Count 嗨，谢谢您的答复。我从你的配置中看出，获得级联通道 1 计数的最佳方法是同时为该通道设置输入捕获并读取 CAPT 寄存器，而不是依赖读取 CNTR 寄存器。 这招管用。但对于通道 1 来说，它仍然算出了一个过高的值。我使用的是 SDK 的应用程序接口，而不是直接操作寄存器，但我的配置似乎与您的相同。 举例说明，当我输入频率为 1kHz 的信号，TMR 时钟为 150MHz 时，我预计计数将为 150,000。这意味着高 16 位计数为 "2"，低 16 位计数为 "18928"=150,000。但是，我得到的上限计数是 "3"。在测量任何频率时，它总是偏差+1。为什么会这样？ const qtmr_config_t QuadTimer_1_Channel_0_config = { .primarySource = kQTMR_ClockDivide_1, .secondarySource = kQTMR_Counter0InputPin, .enableMasterMode = false, .enableExternalForce = false, .faultFilterCount = 0, .faultFilterPeriod = 0, .debugMode = kQTMR_RunNormalInDebug }; const qtmr_config_t QuadTimer_1_Channel_1_config = { .primarySource = kQTMR_ClockCounter0Output, .secondarySource = kQTMR_Counter0InputPin, .enableMasterMode = false, .enableExternalForce = false, .faultFilterCount = 0, .faultFilterPeriod = 0, .debugMode = kQTMR_RunNormalInDebug }; void qtmr_begin() { CLOCK_EnableClock(kCLOCK_Timer1); QTMR_Init(TMR1, kQTMR_Channel_0, &QuadTimer_1_Channel_0_config); QTMR_Init(TMR1, kQTMR_Channel_1, &QuadTimer_1_Channel_1_config); /* Explicitly disable secondary source - not supported in API and not necessary but doing it anyways */ TMR1->CHANNEL[kQTMR_Channel_0].CTRL &= ~TMR_CTRL_SCS_MASK; TMR1->CHANNEL[kQTMR_Channel_1].CTRL &= ~TMR_CTRL_SCS_MASK; /* Ensure free-running (no stop at compare) */ TMR1->CHANNEL[kQTMR_Channel_0].CTRL &= ~TMR_CTRL_LENGTH_MASK; /* Setup the input capture */ QTMR_SetupInputCapture(TMR1, kQTMR_Channel_0, kQTMR_Counter0InputPin, false, true, kQTMR_RisingEdge); QTMR_SetupInputCapture(TMR1, kQTMR_Channel_1, kQTMR_Counter0InputPin, false, true, kQTMR_RisingEdge); /* Enable at the NVIC */ EnableIRQ(TMR1_IRQn); /* Enable timer compare interrupt */ QTMR_EnableInterrupts(TMR1, kQTMR_Channel_0, kQTMR_EdgeInterruptEnable); } void TMR1_IRQHandler(void) { uint16_t lowerCount; uint16_t upperCount; QTMR_ClearStatusFlags(TMR1, kQTMR_Channel_0, kQTMR_EdgeFlag); qtmrIsrFlag = true; lowerCount = TMR1->CHANNEL[kQTMR_Channel_0].CAPT; upperCount = TMR1->CHANNEL[kQTMR_Channel_1].CAPT; // UPPER COUNT IS ALWAYS OFF BY +1 } void getCount(void) { uint32_t counterValue; while (!qtmrIsrFlag) { } qtmrIsrFlag = false; counterValue = ((uint32_t)upperCount << 16) | lowerCount; } } Re: i.MX RT1060 QTMR Cascade mode w/ Input Capture - No Upper Count 好的，感谢您的测试。一定是我的配置出错了。我们可以修改硬件，使用 32 位 GPT 代替 16 位 QTMR，这样我就不用再使用级联模式了。不过，为了帮助其他可能看到此问题的人，我会尽量花一点时间找出错误，更新本帖。

Lear [Stellantis_Smart_ECB] [S32K324]- MCAL Supplier Review Hello Team, Lear asked for a MCAL review (service paid by BSSM hours)  ---------------------------------------------------------------------------------------- As with last review let me send you some information regarding our configuration used in order to speed up this exchange (also see MCAL configurations and other review related docs in the attachments): Configuration Objectives Please clarify the main goals of the current configuration.  Core clock configuration at max core speed with: -Analog continous sampling non-interrupt-based of around 30 signals including external muxes (checking the result conversions in SW in a 3ms task) -Around 40 digital signals trhough DIO. -1 external interrupt using ICU driver and connected emios -1 spi external device (nxp’s fs26). -Minimum XRDC configuration without usage of HSEr -Sleep configuration not considered as low power mode is fully in SBC FS26 hands (microcontroller powered down during low power mode). -ASIL C compliance -FYI using vector os Modules in Scope that we need to focus on Which MCAL modules should we prioritize ? MCU MCL ADC PORT GPT SPI PWM RM Current Issues or Concerns Are there any known issues or areas of concern in the current configuration that we should prepare to address? No current concern for this config ------------------------------------------------------------------------------ BR Stefano RTD Source: Direct Customer Re: Lear [Stellantis_Smart_ECB] [S32K324]- MCAL Supplier Review Hi cuongnguyenphu, if you are able to plan for beginning next week the review with Lear pls. propose some date/time suitable for you. Thanks and BR Stefano Re: Lear [Stellantis_Smart_ECB] [S32K324]- MCAL Supplier Review Hi @StefanoGattazzo  Let me check the input files and comeback with the estimation soon  Re: Lear [Stellantis_Smart_ECB] [S32K324]- MCAL Supplier Review Hi cuongnguyenphu, is it ok next week? BR Stefano Re: Lear [Stellantis_Smart_ECB] [S32K324]- MCAL Supplier Review Hi @StefanoGattazzo  Sorry for my late response. I was busy in the last week for other tickets. Can we setup a meeting with LEAR on Thursday this week (22/1/2026) with your suggested time. I will arrange my schedule to join the meeting One of my first look in the ARXML file is the mismatch between some configuration nodes that appear in only K3 RTD 3.0.0 but was removed in K3 5.0.0. For example in RTD 5.0.0 our package don't have below nodes, so it will be removed: Could you please ask Lear to share again the latest configuration files that match with the RTD version they want to work on (RTD 5.0.0)

s32k312 int sram' 溢出了 8 字节 亲爱的恩智浦工程师 在我使用 S32K312 期间，当我尝试增加全局变量时，S32DS 在编译后报告了一个 " int SRAM 溢出 8 字节 " 错误。我已经上传了地图和链接文件。能否请您帮忙分析一下这个问题？谢谢。 Re: s32k312 int sram' overflowed by 8 bytes 你好，@fengba_360、 这仅仅意味着您使用的 sram 超过了链接器文件中声明的 64KB。你可以尝试缩小堆，将全局变量、不可缓存变量和可共享变量移出 sram，或者改用闪存。 请检查项目编译的地图文件，并根据程序的大小调整链接文件。有关定义和建议，您可以参考社区的一些旧帖子： 无法增加 s32 中的堆大小 - NXP Community 调整 S32K312 的 int_sram 内存分配 致以最诚挚的问候， Julián

SPC と FlexIo_Sent_Ip を使用した SENT NXPコミュニティの皆様、こんにちは。 私は、NXP リアルタイム・ドライバ (RTD) を利用して、S32K3 マイクロコントローラ上の SENT センサ (単線) の同期モードを実装する作業に取り組んでいます。 SENT 受信に関する私の現在の理解とアプローチは、ハードウェア支援によるデコード機能を提供する「Flexio_Sent_Ip」ドライバを使用することです。 同期モードでは、S32K3 はマスターとして機能し、定期的にトリガー パルスを SENT センサに送信し、SENT センサは SENT データ フレームで応答する必要があります。 私の主な質問はピン構成に関するものです。 1 つの FlexIO ピンを両方に使用することは可能ですか? - センサのマスタートリガーパルス（出力）を生成します。 - Flexio_Sent_Ip ドライバーを使用して、センサーから後続の SENT データ (入力) を受信します。 Flexio_Sent_Ip モジュールの S32 構成ツールを調べていたところ、「SPC 機能のアクティブ化」オプションがあることに気付きました。 この特定の機能では、トリガー用に別の FlexIO ピンを構成する必要があるようです。 この観察から、Flexio_Sent_Ip はトリガーとデータに対して同じ物理ピン上での入力/出力機能の組み合わせをサポートしていない可能性があると考えられます。 S32K3 上の Flexio_Sent_Ip を使用して同期 SENT のシングルピン ソリューションを実現できるかどうかを明確にしていただけますか? S32K3 で同期モードを実装するための推奨されるベスト プラクティスは何ですか? よろしくお願いいたします。 スーパーバード Re: SENT with SPC and FlexIo_Sent_Ip こんにちは@superbird SENT は、一方向通信インターフェース(センサ出力、MCU 入力)として設計されています。これは過酷なオートモーティブ環境向けに最適化されたデジタル プロトコルであり、同じピンが動的に役割を切り替えることは一般的ではありません。 S32K3/S32M27x SENT ドライバー統合マニュアルと RTD に付属のユーザー マニュアルを確認することをお勧めします。これらのドキュメントには、ドライバの制限、ハードウェアとソフトウェアの要件、使用手順、構成ガイドラインなど、ドライバに関する詳細情報が記載されています。これらのドキュメントは、たとえば次の場所にあります。 C:\NXP\S32DS.3.6.2\S32DS\ソフトウェア\プラットフォームSDK_S32K3\RTD\Sent_TS_T40D34M60I0R0\ドキュメント さらに、RTD にはサンプル コードも提供されており、機能性をより深く理解するための参考資料として役立ちます。 最後に、SPC プロトコルに関しては、MCU から特定のトリガー パルスを受信した後にのみデータを送信します。現在、サンプル コードはありませんが、S32K3/S32M27x SENT ドライバのユーザー マニュアルには、SPC 機能を使用するために SENT チャネルを構成する手順を概説した専用のセクションが含まれています。 BR、ヴェインB

i2c call back is not getting called Hello Team, I am working with a DAC module (MCP47FEB21A0) that is interfaced with an LPC55S69 over I²C. I observed that I2C_MasterTransferBlocking() works correctly, but when I use I2C_MasterTransferNonBlocking(), the I²C callback is never invoked. I2C_MasterTransferNonBlocking() is returning kStatus_Success. For reference, I2C_MasterTransferCreateHandle() is called once during I²C initialization. Could someone please explain why the I²C callback is not getting called when using I2C_MasterTransferNonBlocking()? Regards, Santhosh Re: i2c call back is not getting called Hi @sushmasan  I think you can refer to the  lpcxpresso55s69_lpc_i2c_interrupt_b2b_transfer_master_cm33_core0 SDK demo. BR Harry Re: i2c call back is not getting called Hi @Harry_Zhang , Thanks for your response. I have other sensor modules that are working with non-blocking calls. I am using a BMP390 sensor, and the I²C communication works fine with non-blocking calls. For example, if one of the register addresses is 0x01, I assign the subaddress as shown below: masterXfer.subaddress = (uint32_t)0x01; However, for the DAC (MCP47FEB21A0) module, the subaddress is assigned differently: uint8_t subAddress; subAddress = (uint8_t)(reg_addr << 3); // Based on the MCP47FEB21A0 datasheet, the register address must be shifted left by 3 masterXfer.subaddress = (uint32_t)subAddress; Is it going to make any difference? Regards, San Re: i2c call back is not getting called Hi @sushmasan  I think you can try to set subaddressSize = 0 and put the DAC’s command byte(s) and data bytes directly in masterXfer.data, then start a write transfer. BR Harry Re: i2c call back is not getting called Hi @Harry_Zhang , I even tried it, uint8_t txData[3] = {0}; txData[0] = (uint8_t) (reg_addr << 3); txData[1] = (uint8_t)(data >> 8); /* Data high byte */ txData[2] = (uint8_t)(data & 0xFFU); /* Data low byte */ masterXfer.data = txData; masterXfer.dataSize = 3; /* 3 bytes total */ I have some data which is of 2 bytes, so after the adding reg addr it becomes 3 bytes. Still I²C callback is not getting called when I use I2C_MasterTransferNonBlocking(). Regards, San Re: i2c call back is not getting called Yesterday I replied to your message, but mistakenly I did a reply to the topic. I am not sure whether you have noticed it or not, that's why responding to your message again here. Hi @Harry_Zhang , I even tried it, uint8_t txData[3] = {0}; txData[0] = (uint8_t) (reg_addr << 3); txData[1] = (uint8_t)(data >> 8); /* Data high byte */ txData[2] = (uint8_t)(data & 0xFFU); /* Data low byte */ masterXfer.data = txData; masterXfer.dataSize = 3; /* 3 bytes total */ I have some data which is of 2 bytes, so after the adding reg addr it becomes 3 bytes. Still I²C callback is not getting called when I use I2C_MasterTransferNonBlocking(). Regards, San Re: i2c call back is not getting called Hi  @sushmasan  Can you share the your code so I can take a look? BR Harry Re: i2c call back is not getting called Hi @Harry_Zhang , Please find the code snippet for your reference, #define I2C5_BASE (0x40096000u) #define I2C5_MASTER_BASE (I2C5_BASE) #define I2C5_MASTER_CLOCK_FREQUENCY (12000000) #define I2C5_MASTER ((I2C_Type *) I2C5_MASTER_BASE) static void i2c_master_callback(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData) { /* Signal transfer success when received success status. */ if (status == kStatus_Success) { // Successfully completed data transfer g_MasterCompletionFlag = true; g_i2cCallBackStatus = kStatus_Success; } /* Signal transfer failure when received failure status. */ else { if(status == kStatus_I2C_Nak) { g_i2cCallBackStatus = kStatus_I2C_Nak; } else if (status == kStatus_I2C_Addr_Nak) { g_i2cCallBackStatus = kStatus_I2C_Addr_Nak; } else if (status == kStatus_I2C_ArbitrationLost) { g_i2cCallBackStatus = kStatus_I2C_ArbitrationLost; } else { g_i2cCallBackStatus = false; } } return; } bool i2c_readwrite(i2c_master_transfer_t *masterXfer) { status_t status = kStatus_Fail; status_t finalStatus = kStatus_Fail; bool retVal = false; g_MasterCompletionFlag = false; g_i2cCallBackStatus = kStatus_Fail; /* Send master non-blocking data to slave (Performing the write operation) */ /* Allowing the CPU to continue executing other tasks in parallel while the I2C transfer is being handled in the background. */ status = I2C_MasterTransferNonBlocking(I2C5_MASTER, &g_m_handle, masterXfer); PRINTF("(%s() => Wait for the data transfer to slave completion. status:%d \r\n",__func__,status); /* Wait for transfer completed. */ while (!g_MasterCompletionFlag) { } g_MasterCompletionFlag = false; // Driver-level error (could not start transfer) if(status == kStatus_Success) retVal = true; // Transfer completed else retVal = false; g_i2cCallBackStatus = kStatus_Fail; return retVal; } // THIS IS WITH I2C NON BLOCKING CALL -> CALL BACK IS NOT GETTING INVOKED. bool dac_write_reg(uint8_t reg_addr, uint16_t data) { /* The DAC needs 1 address byte + 2 data bytes. */ static i2c_master_transfer_t masterXfer = {0}; static uint8_t txData[3] = {0}; bool retVal = false; bool write_status = false; memset(&masterXfer, 0, sizeof(masterXfer)); txData[0] = (uint8_t) (reg_addr << 3); txData[1] = (uint8_t)(data >> 8); txData[2] = (uint8_t)(data & 0xFFU); masterXfer.slaveAddress = 0x60; masterXfer.direction = kI2C_Write; masterXfer.subaddress = 0; masterXfer.subaddressSize = 0; masterXfer.data = txData; masterXfer.dataSize = 3; masterXfer.flags = kI2C_TransferDefaultFlag; write_status = i2c_readwrite(&masterXfer); if(true == write_status) { PRINTF("(%s) -> I2C write PASS @line:%d \r\n",__func__,__LINE__); retVal = true; } else { PRINTF("(%s) -> I2C write failed with status %d \r\n",__func__,write_status); retVal = false; } return retVal; } // THIS IS WITH I2C BLOCKING CALL -> WORKING FINE int8_t dac_write_reg(uint8_t reg_addr, uint16_t data) { /* The DAC needs 1 address byte + 2 data bytes. */ i2c_master_transfer_t masterXfer; uint8_t txData[2]; uint8_t subAddress; memset(&masterXfer, 0, sizeof(masterXfer)); subAddress = (uint8_t)(reg_addr << 3); /* DAC reg byte */ txData[0] = (uint8_t)(data >> 8); /* Data high byte */ txData[1] = (uint8_t)(data & 0xFFU); /* Data low byte */ masterXfer.slaveAddress = 0x60; masterXfer.direction = kI2C_Write; masterXfer.subaddress = (uint32_t) subAddress; masterXfer.subaddressSize = 1; masterXfer.data = txData; masterXfer.dataSize = 2; masterXfer.flags = kI2C_TransferDefaultFlag; status_t status = I2C_MasterTransferBlocking(I2C5_MASTER, &masterXfer); if (status == kStatus_Success) { PRINTF("(%s) -> dac_write_reg PASS @line:%d \r\n",__func__,__LINE__); status = 1; } else { PRINTF("(%s) -> I2C_MasterTransferBlocking() failed with status %d \r\n",__func__,status); status = -1; } return status; } int main() { I2C_MasterGetDefaultConfig(&masterConfig); I2C_MasterInit(I2C5_MASTER, &masterConfig, I2C5_MASTER_CLOCK_FREQUENCY); I2C_MasterTransferCreateHandle(I2C5_MASTER, &g_m_handle, i2c_master_callback, NULL); dac_write_reg(0x08, 0x0001); } Re: i2c call back is not getting called Hi @sushmasan  i have reviewed your code.  But I'm sorry, I couldn't find a clear error. I think you can also use an oscilloscope to check if the data transmission is correct and if the returned data is correct. BR Harry

S32k324-MCU0 开启安全启动时无法擦除内存中的某些区域 @Silpa_Muppalla Re: S32k324-MCU0 嘿，大卫 这个问题问错了论坛，你能删除这个主题吗？谢谢！ Re: S32k324-MCU0 本来希望今天能抽出时间拨打调试电话来解决这个问题的根源 Re: S32k324-MCU0 能否提供另一个主题的链接，以便我仔细检查。下面是 3 个寄存器的外设转储：MC_ME、DCM_GPR、MSCM。开启安全启动后，我们可以写入闪存，但由于某种原因，我们在执行擦除操作时会被锁定。 Re: S32k324-MCU0 你能否提供更多细节或对其他话题的参考（如果相关）？谢谢

i.MX 8M Plus DDR4-3200 长度匹配建议 我正在为 i.MX 8M Plus （部件号：MIMX8ML8CVNKZAB）设计 DDR4 接口，希望确认 长度与 DDR4-3200 操作的匹配建议。 在现有文件（IMX8MPHDG、AN5097 等）中， ，介绍了 DDR 路由的一般准则。 不过，我无法找到 长度匹配的明确数值限制，特别是在 3200 MT/s 的 DDR4 运行条件下。 对于运行速度为 3200 MT/s 的 DDR4，请告知 以下信号组的推荐长度匹配（最大偏斜/长度差） ？ -CK (CK/CK#) -DQS (DQS/DQS#，在字节通道内和字节通道之间) -DQ（在字节通道内且相对于 DQS）-CA/地址/控制信号 此外，请澄清： - 关于 i.MX 8M Plus DDR4 设计的长度匹配规则，应以哪个文件为准 - SoC 的内部 DDR 训练通常可以补偿多少偏斜？ Re: i.MX 8M Plus DDR4-3200 length matching recommendations 感谢您之前的回复。 我知道i.MX 8M Plus参考板 没有实现DDR4，也没有公布明确的DDR4长度匹配 值。 对于在 i.MX 8M Plus 上以 3200 MT/s 的速度运行 DDR4， ，请说明 PCB 布线和长度匹配的推荐设计方法 ？ 具体而言： -DDR4-3200 的运行是否通过设计 （采用适当的电路板设计）进行假设和验证？ -在没有 DDR4 参考板的情况下，应将 什么视为长度匹配和偏差 控制的主要指导原则？ 如果遵循标准的 DDR4 信号完整性规则，AN5097 是否可以用作 i.MX 8M Plus 设计的通用 DD R4 路由指南 ，尽管它不是 针对特定设备的？ Re: i.MX 8M Plus DDR4-3200 length matching recommendations 请参阅我们的 i.MX 8M Plus 硬件开发人员指南和参考板设计。 Re: i.MX 8M Plus DDR4-3200 length matching recommendations 我们知道，硬件指南和验证板设计是i.MX 8M Plus上DDR4的主要参考。 但是，我们认为这些文件没有充分详细地描述 DDR4 路由、长度匹配和偏斜限制。 您能否分享您提到的具体硬件指南和DDR4验证板设计的链接，以便我们可以再次确认我们引用的文档是否正确？ Re: i.MX 8M Plus DDR4-3200 length matching recommendations 对于在 i.MX 8M Plus 上以 3200 MT/s 的速度运行 DDR4， ，请说明 PCB 布线和长度匹配的推荐设计方法 ？ 具体而言： -DDR4-3200 的运行是否通过设计 （采用适当的电路板设计）进行假设和验证？ -在没有 DDR4 参考板的情况下，应将 什么视为长度匹配和偏差 控制的主要指导原则？ 答：我们只提供 i.MX8MP 的硬件指南，使用 DDR4 的硬件设计请参考该指南。对于使用 DDR4 的 i.MX8MP，我们有验证板的设计，我会分享给你的。 如果遵循标准的 DDR4 信号完整性规则，AN5097 是否可以用作 i.MX 8M Plus 设计的通用 DD R4 路由指南 ，尽管它不是 针对特定设备的？ 答：不，请勿参考，i.MX8MP 请按照硬件指南进行特殊操作。 Re: i.MX 8M Plus DDR4-3200 length matching recommendations 亲爱的@yamamo10、 我没有也没有找到 DDR4 的特殊文件，但我仍会继续为你们检查，一旦有更新的信息，我会与你们分享。 我记得你的需求。 祝您度过愉快的一天和周末 祝您有美好的一天 顺祝商祺！ Rita Re: i.MX 8M Plus DDR4-3200 length matching recommendations 感谢您分享可用的硬件指南和验证板设计。 据我们了解，除了提供的材料外，目前没有其他文档或设备特定指南来描述 i.MX 8M Plus 的 DDR4 PCB 布线、长度匹配或偏斜限制。 在此基础上，我们将使用通用的 DDR4 信号完整性最佳实践和内部 SI 分析进行设计，同时遵循 i.MX8MP 硬件指南作为主要参考。 感谢您的支持。 如果今后有任何其他建议或更新，我们希望您能与我们分享。 Re: i.MX 8M Plus DDR4-3200 length matching recommendations 我已通过电子邮件发送给您，请查收。

将 KSZ9131Rnxi 与 iMX 8M Nano 连接 你好、 我想在我们的载板上使用 imx8M Nano SOM 来操作 KSZ9131RNXi。phy 和 fec mac 的驱动程序加载正常，但是我的通信速度确实只有 10Mbits，而且只有在操作系统启动后才输入以下内容： $ethtool -s eth0 speed 10 duplex full PHY 采用 RGMII 模式连接，速度为 1000Mbit/S。 如何解决此问题以在启动后不使用键入此命令来操作 phy？以及为什么 100Mbits 和 1000Mbits 不起作用？ 我将非常感谢你们的贡献。 Re: Interfacing KSZ9131Rnxi to iMX 8M Nano 您好@Elias_M， ，感谢您联系恩智浦支持中心！ 你是如何在设备树中设置的？ 我相信这个问题可以通过正确的设备树配置来解决。 你能分享你的设备树文件以便我查看吗？ 如果无法共享，可以参考以下链接提供的示例 致以最崇高的敬意， Chavira Re: Interfacing KSZ9131Rnxi to iMX 8M Nano 你好，@ Chavira、 感谢您的支持。 以下是 Linux 中的 fec 设备树的描述： &fec1 { fsl、magic-packet； pinctrl-names ="默认" ； pinctrl-0 =<& pinctrl_fec1_gpio> 、 <&pinctrl_fec1> ； phy-mode ="rgmii-id" ； phy-handle =<& ethphy0> ； phy-supply =<& reg_3v3_eth0> ； status ="okay" ；     mdio { #address-cells =<1> ； #size-cells =<0> ；   ethphy0：ethernet-phy@0 { 兼容 ="ethernet-phy-ieee802.3-c22" ； reg =<0> ； 中断父级 =<& gpio5> ； 中断 =<2 IRQ_TYPE_LEVEL_LOW> ； micrel,led-mode=<1> ； }; }; }; reg_3v3_eth0: 调节器-ethphy { 兼容 ="调节器-固定" ； off-on-delay=<500000> ； regulator-always-on； 调节器启动；   regulator-min-microvolt =<3300000> ； regulator-max-microvolt =<3300000> ； 调节器名称 ="3v3_eth0" ； startup-delay-us =<200000> ；   }; pinctrl_fec1_gpio: fec1gpiogrp { fsl,pins =<   /* PHY 中断 */ MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; };   pinctrl_fec1: fec1grp { fsl,pins =< MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f >; }; Re: Interfacing KSZ9131Rnxi to iMX 8M Nano 嗨 @Elias_M， 为了更好地理解，我需要检查整个设备树文件。 致以最崇高的敬意， Chavira Re: Interfacing KSZ9131Rnxi to iMX 8M Nano 你好，@ Chavira、 这些是 uboot v2020.04 和 linux v5.5 的 dts 文件。 如何在 board_phy_config 中添加延迟，还是驱动程序中已经包含了这些延迟？

[滥用] 帖子作者：@hrc-amilcar/板：mcuxpresso-sdk/报道者：@hrc-amilcar @hrc-amilcar 报告了 @hrc-amilcar 发布的帖子 RT685：SDK 25.12 中的 AES HASHCRYPT 密钥， 原因如下： 原因： 其他 详情： 我的帖子被标记为垃圾邮件，但它不是垃圾邮件。这是一个合法的 MCUXpresso SDK 问题。为什么会被标记？ 发布链接： https://community.nxp.com/t5/MCUXpresso-SDK/RT685-AES-HASHCRYPT-Secret-Key-in-SDK-25-12/m-p/2289098#M5421 文章作者：@hrc-amilcar | Email Author @hrc-amilcar|Email Author Reported by： @hrc-amilcar|Email Reporter 报告的帖子有 0 个回复。

WVTS 测试未通过 您好， 我们在运行 Android 12.1.0_1.0.0 并支持 Widevine L1 的 imx8mq 定制板上进行了 WVTS 测试。 结果中有一些失败的项目。 测试结果详情 arm64-v8a WvtsDeviceTestCases com.google.android.wvts.MediaDrmParameterizedTests#testValidateMetrics[L1] 失败 java.lang.AssertionError: license_sdk_version value empty: metrics com.google.android.wvts.MediaDrmParameterizedTests#testStableDrmIdentifier[L3]. 失败 设备 ID 不稳定：ac9e72902e704bef69ca002db4e8e8e8cd8e8f8cc039fe4fe34ed78b53b0bc81838、9c99ccd3cd3c902c902fc7902c7354e2932a26dc5e2bc6c6c68cf211037d8aefc75a87d8d0568de：数组最初在元素 [0] 处有所不同；预期：& lt；-84 & gt；但是：& lt；-100 & gt; com.google.android.wvts.MediaDrmParameterizedTests#testValidateMetrics[L3]. 失败 java.lang.AssertionError: license_sdk_version value empty: metrics com.google.android.wvts.WidevineBusinessLogicTests#testWidevineVersion 失败 java.lang.assertionError：cdm 版本 16.1.0 的版本号未知 com.google.android.wvts.WidevineH264PlaybackTests#testClearWith1080P30SessionlessUsingSecureDecoder 失败 java.lang.Exception：元器件故障：& lt；音频已达到秒数：音频仅播放到 0 毫秒而不是 20000 毫秒 & gt; & lt；无异常：播放期间出现异常（尝试使用封闭会话）& gt; & lt；视频已达到秒数：视频仅播放到 0 毫秒而不是 20000 毫秒 & gt; com.google.android.wvts.WidevineH264PlaybackTests#testClearWith1080P30SessionlessUsingUnsecureDecoder 失败 java.lang.Exception：元器件故障：& lt；音频已达到秒数：音频仅播放到 0 毫秒而不是 20000 毫秒 & gt; & lt；无异常：播放期间出现异常（尝试使用封闭会话）& gt; & lt；视频已达到秒数：视频仅播放到 0 毫秒而不是 20000 毫秒 & gt; 所需的 CDM 最低版本似乎是16.1.1。但是，widevine_l1_android-12.1.0_1.0.0使用的谷歌 Widevine 代码的 CDM 版本是16.1.0。 请帮助我们解决这些故障。 谢谢。 BR、 特里斯坦 Android i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus 安全 Re: Failed WVTS test 我们正在使用的包含 vendor/widevine 下 CDM 的 libwvdrmengine 已由 NXP 修补，以支持 Widevine L1。不过，我们似乎不能只替换 libwvdrmengine 中的 cdm 文件夹。 恩智浦是否为支持 Widevine L1 的 libwvdrmengine 更新版本提供了新补丁？ 此外，如果是这样，我们还能在 Trusty OS 中使用相同的宽频 TA 吗？ 谢谢。 Re: Failed WVTS test 尝试将 CDM 版本升级到比 v16 更晚的版本，然后再试一次 Re: Failed WVTS test 对不起，我的回复晚了，我刚刚收到补丁，已通过邮件发送给您，请查收。

M7 上的 S32g274 PFE 以太网演示 1、我在截图中找不到 PFE 以太网演示的示例项目。另外，我找不到可以直接用 s32ds3.5 编译器编译的项目。您能告诉我吗？ 2、我需要调试 M7 和 A53 同时启动，而 M7 内核的 PFE 以太网功能保持正常的情况。不过，我发现这里对时钟初始化的描述有所不同。由于需要在 M7 引导加载程序中初始化时钟，因此 M7 APP 不应执行时钟初始化。但 PFE 以太网要求在时钟初始化之前先进行 EMAC 初始化。这是自相矛盾的。我们应该如何处理？ Re: S32g274 PFE Ethernet demo on M7 你好，@sdx111 感谢您的回复。 有一个演示版，但基于早期版本的代码库。 BR 切宁 Re: S32g274 PFE Ethernet demo on M7 在哪里可以找到可以用 S32DS 编译器编译的 S32g PFE 以太网（包括 lwip 栈）演示项目？ Re: S32g274 PFE Ethernet demo on M7 你好，@sdx111 谢谢您的帖子。 1.PFE 主服务器是 PFE MCAL 版本中包含的一个示例项目，它不支持 S32DS，我建议在 EB 中对其进行配置。 2。PFE master 是一个在开发时未考虑引导加载程序的示例，因此当使用引导加载程序启动板然后运行 PFE 主服务器时，需要修改原始代码，调用后可能需要关闭并打开 P FE 分区。 BR 切宁

使用人工智能笔记本电脑进行恩智浦人工智能和 ML 开发 大家好， 我计划使用 AI 笔记本电脑作为恩智浦AI 和 ML 项目的主要开发机器，包括 eIQ 机器学习工具和基于 i.MX 的边缘 AI 平台。 我想利用人工智能笔记本电脑的强大功能来完成训练、优化人工智能模型以及部署到恩智浦嵌入式设备等任务。 根据您的经验，对于恩智浦的开发而言，人工智能笔记本电脑的哪些功能最为重要？例如 GPU 与 CPU 在训练和推理方面的性能对比 为实现流畅的人工智能工作流程而推荐的内存 存储类型和速度考虑因素 恩智浦人工智能工具的最佳操作系统（Linux 与 Windows 如果您对恩智浦人工智能项目使用人工智能笔记本电脑有任何意见、建议或实际经验，我将不胜感激。 提前感谢！

Request for FRDM-MCXW72 Allegro ASCII (.alg) design files for Altium import Hi NXP Team and Community, I am currently working on a design based on the FRDM-MCXW72 development board. I have downloaded the design files (Design Resources ZIP), but I see the layout file is in binary Cadence Allegro format (.brd). Since I use Altium Designer, I am unable to import the binary .brd file directly. Could you please provide the layout in Allegro ASCII (.alg) format? Alternatively, an ODB++ export would also work perfectly. This would allow me to import the reference design correctly and accelerate my development process. Thank you for your support! Best regards,  Jinhao Protocol: Bluetooth Re: Request for FRDM-MCXW72 Allegro ASCII (.alg) design files for Altium import Hello, hope you are doing well. The design files we provide are only available in .brd format. If a customer wishes to convert these files into a different format, each customer would need to handle the conversion on their own. I apologize for the inconveniences, but this is the only format that is available. Would the Gerber files be helpful for you? These are located in the FRDM-MCXW72\Gerbers directory of the MCX W72 Design Files. If you'd like to review the layout, you could use the Altium viewer. Best regards, Ana Sofia.