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i.mx8M Plus Processor || Power Dissipation Value Details Hello NXP Team, We are designing a Hardware platform using the MIMX8ML6NKZACVB Processor. Can you please share the power dissipation value for this processor? Re: i.mx8M Plus Processor || Power Dissipation Value Details Hi, Thank you for your interest in NXP Semiconductor products, The part number misses some parameters for its differentiation. It misses if it's industrial or automotive. However, both packages have a thermal resistance of the following, it depends on every customer to take the thermal resistance, environmental and processing load conditions to select an specific part. As a suggestion, you could use the NXP EVK heatsink part: Name: HEAT SINK 40*40*15MM, BLACK ALUMINUM Manufacturer: Suzhou Puqiao Electronic CO.,LTD Manufacturer part number: NXP-PQ-HS0002 Regards
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MIMXRT1064-EVKセンサーデバイスの初期化に失敗しました こんにちは 私には2つの問題があります。 1.ボードを接続しても、MCUExpresso IDEの「ボードとデバイスの選択ページ」にボードが表示されません。 2.コンソールには「センサーデバイスの初期化に失敗しました!」と「センサーチップU32を確認してください」と表示されます。 この問題を解決するにはどうすればいいですか? Re: MIMXRT1064-EVK sensor device initialize failed これは、QFlashから起動するようにDIPスイッチSW4を変更したMIMXRT1060-EVKBです。その後、エラーが発生します。Minicomを介してUbuntu 24.02に接続されています。 何かヒントをください。 Re: MIMXRT1064-EVK sensor device initialize failed こんにちは、 NXP Semiconductors製品にご関心をお寄せいただき、また、弊社をご利用いただける機会をいただき、誠にありがとうございます。 アドバイスをする前に、テスト環境(ボード、デモ、IDEなど)について説明していただけますか? すてきな一日を、 TIC ------------------------------------------------------------------------------- 注記: この投稿があなたの質問への回答になっている場合は、「正解としてマーク」ボタンをクリックしてください。ありがとう! - 最後の投稿から7週間はThreadをフォローしますが、それ以降の返信は無視されます。 後日、関連する質問がある場合は、新しいThreadを作成し、閉じられたThreadを参照してください。 -------------------------------------------------------------------------------
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FS5600 : NOT Registers Hello NXP ,  according to the FS5600 datasheet , it states that for registers that contain secure bits , it is obligatory to write to the register itself and its respective NOT register .  When interfacing with an MFS5600AMBA0ES , we remarked that a write to just the register (without any writes to the NOT register) is enough and the content of the register is overwritten . Is this behaviour normal ? I thought the NOT logic registers are available for all ASILB parts . Best Regards FS65&FS45 Re: FS5600 : NOT Registers It can be simply understood that you first write to the relevant registers without writing to the NOT registers. Therefore, the registers updated first will not have any effect on the SBC. The SBC will only be updated when the NOT registers are changed accordingly. Re: FS5600 : NOT Registers >"That behavior should not change SBC configuration at last even though you can Write it successful" Do you confirm that the value of the Register is indeed modified BUT the written configuration will not be taken into consideration ? For Example :  FS5600_WriteRegister(Reg,dummy) ---> val = FS5600_ReadRegister(Reg) , should i expect val to be equal to dummy but the dummy configuration will not affect the Sbc functionality unless we also write to the NOT register ? Is my assumption correct ? Thank you in advance  Re: FS5600 : NOT Registers I confirmed in the EVB: That behavior CAN NOT change SBC configuration at last even though you can Write it successful, if no operate the related NOT register. So you need operate the register and related NOT register together for getting successfully. Re: FS5600 : NOT Registers That behavior should not change SBC configuration at last even though you can Write it successful., if no operate the related NOT register. I will confirm again in the EVB tomorrow and let you know the result. Re: FS5600 : NOT Registers Could you please share with me what could potentially happen if NOT registers are also not modified .  Just for some general reference !  Thanks in advance for the help !  Re: FS5600 : NOT Registers 1:In my case the register's value changes even when i don't modify the NOT register .  Is this normal behaviour ? is there some usecase where NOT registers are disabled for example through an OTP register etc ... [gw]That's normal behavior but we don't recommend you do that, you'd better operate this NOT register also. Re: FS5600 : NOT Registers 1:In my case the register's value changes even when i don't modify the NOT register .  Is this normal behaviour ? is there some usecase where NOT registers are disabled for example through an OTP register etc ... [gw]That's normal behavior but we don't recommend you do that, you'd better operate this NOT register also. Re: FS5600 : NOT Registers I don't really get what you mean . In my case the register's value changes even when i don't modify the NOT register .  Is this normal behaviour ? is there some usecase where NOT registers are disabled for example through an OTP register etc ... Br Re: FS5600 : NOT Registers Hi  You'd better operate the respective NOT register also. Hope this could help you! Thanks!
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How to use HSE in S32DS3.6.6 version? I couldn't find the HSE peripheral driver in version 3.6.6 of S32DS. How should I use HSE in version 3.6.6?   HSE can be found in S32DS3.5    And, How can I migrate the project of version 3.5 to version 3.6? Re: How to use HSE in S32DS3.6.6 version? Hi @ZDDL  This is not about version of S32 Design Studio, it’s about version of used RTD drivers. Sometimes the Crypto driver is not available in first initial release of new RTD and it is provided later in separate package. You can check section “2.5  Support and Driver Plugins Delivered” in release notes for each package. For example, in case of RTD 7.0.0, Crypto driver is provided in package 7.0.0 QLP02 which must be installed on top of RTD 7.0.0. In case of RTD 7.0.1, Crypto driver is provided in package 7.0.1 P02: Notice that this is Code Drop release only, it needs to be replaced by RFP (ready for production) version once it is available. I recommend to check the versions rather here than in the S32DS updates: https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-STDSW-D Open the link and then go to “Automotive SW - S32K3/S32M27x - Real-Time Drivers for Cortex-M”. The release notes file for each RTD also contains information about version of S32 Design Studio which was used for development and testing of that RTD. And we recommend to use the same version for your development. Regards, Lukas
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LS1043A is SEC a requirement for Secure Boot? Since the LS1043A can come with either SEC enabled, or SEC disabled. Is it a hard requirement that SEC be enabled for Secure Boot? If we have an LS1043A that already has SEC disabled from NXP can Secure Boot still be achieved? Documentation is unclear, but seems like Secure Boot is still available even if SEC is not. Is this correct? QorIQ LS1 Devices Re: LS1043A is SEC a requirement for Secure Boot? Hi, If the LS1043A silicon lacks the SEC engine, it is physically incapable of triggering the ROM-based logic required to start a secure chain. The Arm CoT/mbedtls path in LSDK is not a "workaround" for missing hardware; it is simply a different software architecture for chips that do have the necessary security hardware. regards Re: LS1043A is SEC a requirement for Secure Boot? Ok, so a LS1043ASN7MNLB is not capable of secure boot with arm trusted firmware, correct? A LS1043ASEN7MNLB would be capable of secure boot with arm trusted firmware, because it has the SEC enabled, correct? Now you said that for the non-SEC chip it is not capable of a 'hardware-rooted' secure boot. Does that mean a software version / 'software-rooted' of secure boot could work? In the LSDK 21.08 it does also mention instead of NXP CoT there is Arm CoT that utilizes mbedtls. However, it looks like in the documentation that it does not support the LS1043A chip.  Just trying to get some clarification. Thank you for the reply. Re: LS1043A is SEC a requirement for Secure Boot? Hello, No, it is not correct that Secure Boot is available if the SEC engine is disabled . For the LS1043A, having the SEC engine (security acceleration) enabled is a hard requirement for establishing a hardware-rooted Secure Boot. Regards
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IMX-LVDS-HDMIアダプターカード IMX-LVDS-HDMI | NXPセミコンダクターズ こんにちは、 IMX-LVDS-HDMIボードの全体寸法(幅×長さ×高さ)をお知らせいただけると幸いです。 Re: IMX-LVDS-HDMI Adaptor Card 基板上で確認できます。 これがあなたのお役に立てば幸いです。
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MCXN236VNLT 自定义板-启用时钟后的 RTC0 外设挂起代码 我正在开发 MCXN236VNLT 定制板。当我启用 RTC0 外设时,单片机会挂起,而且当我启用时钟并访问 RTC0 上的任何寄存器时,我的 Cyclone 会失去连接。 clock_config.c有以下作用: CLOCK_SetPLL0Freq(&pll0Setup); /*!< 将 PLL0 配置为所需值 */ CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 监测已禁用 */ CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVbat); /* OSC_32 kHz 输出时钟到 启用启用 */ vbat_osc_config_tg_vbatOscConfig_BOARD_BootClockPLL150M = { .coarseAdjustment = kVBAT_OscCoarseAdjustment05, .enableInternalCapBank = true、 .enableCrystalOscillatorBypass = true、 .xtalCap = kVBAT_OscXtal12pFCap, .extalCap = kVBAT_OscExtal12pFCap, }; VBAT_SetOscConfig(VBAT0,&g_vbatOscConfig_BOARD_BootClockPLL150M); SYSCON->CLOCK_CTRL|= syscon_clock_ctrl_fro1mhz_clk_ena_mask; /*!< 启用 FRO_1M */ CLOCK_EnableClock(kCLOCK_Rtc0); rtc0->ctrl |= rtc_ctrl_clk_sel_mask; (hangs here!) 如果在调试器中跳过这一行,MCU 将继续启动,直到其他代码尝试访问 RTC0 上的任何寄存器。 目前我能想到的办法都试过了。Systick 和 MRT 也在运行,具有更高的中断优先级,但即使禁用,似乎也只是 RTC0 的时钟问题。 奇怪的是,当 McuxPresso 停止连接时,它会在 0x0 " 处打开 " adc0_irqHandler () 的选项卡,并在 0x0 处显示 " 没有可用于 " adc0_irqHandler () 的来源 " " 我使用的是外置 32768 晶振,如果我将时钟改为内置 16k 时钟,代码就能运行得更远一些: status_t IRTC_Init(RTC_Type*基础 常数 IRTC_CONFIG_T*config) { assert(NULL != config); 并在"断言" 失败。"config" = 配置,而不是 NULL,这是怎么回事?唉! 如果您有任何新的看法或想法,我们将不胜感激! MCX N Re: MCXN236VNLT custom board - RTC0 Peripheral hanging code when clock enabled 你好@jmullen_condose、 感谢您的来信。正如您在MCXN947 上使用 32k osc 初始化 iRTC 失败中提到的,造成这一问题的原因是要求在 RTC 初始化和访问 RTC 寄存器之前提供时钟源。 默认情况下,RTC CTRL[CLK_SEL] 位域选择 FRO16K 时钟源。因此,在 RTC CTRL[CLK_SEL] 切换到 OSC32K 时钟源之前,FRO16K 时钟必须保持启用状态。这是正确初始化 RTCCLKSEL 时钟选择器的唯一正确方法。 此外,我还将为 MCXN236 创建一个内部票据。在获得永久性修复之前,请参考该帖子中描述的解决方法。 希望对你有所帮助。 BR 西莱斯特 Re: MCXN236VNLT custom board - RTC0 Peripheral hanging code when clock enabled 你好,@jmullen_condose、 如@Celeste_Liu 所述,MCXN947 已报告过该问题。在最新版本的配置工具版本 26.03 中,MCXN236 MCU 的问题也已得到修复。请参阅禁用 FRO16K 和访问 RTC0->CTRL寄存器时提供的以下代码: 使用最新的配置工具 26.03 版本,该版本可为这种使用情况提供正确的初始化代码。 顺祝商祺! 马雷克-诺伊齐尔
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S32ds for arm activation S32DS applied for a license on the first computer and now after installing it on a different computer, it won't install. Display this Software Activation Code is already used on this station for 3 Activated 2.2. After looking for a solution on the Internet and deleting C:\ProgramData\FLEXnet, I'm now reporting this. Your Software Activation Code is for another feature. Do you want to return it? I can't get it to install on either computer now. License Quantity:Fulfillment ID:Expiration Date:Product:Machine:Activation Code. 1 129093311 Mar 20, 2030 S32 Design Studio for ARM v2.2 Update 2 2546bee2510f6ab15c2b06ab1de4ebf023002a53 195a-78d8-b2b2-b28b 回复: S32ds for arm 激活 Just find a few of them in the forums and try activating them with someone else's. 回复: S32ds for arm 激活 Have you solved it yet? I'm having the exact same problem as you.
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S32 Design Studio for ARM 2.2 ライセンスの問題 S32 Design Studio for ARM v2.2 私は長い間ARM 2.2用のS32DSを有効化していましたが、昨日アプリケーションを起動すると「ライセンスがありません」と表示されます。同じアクティベーションコードで再アクティベートしようとすると、「お使いのソフトウェアアクティベーションコードは別の機能用です。返却しますか?」と表示されます。再インストールあまり効果がない。 「C:\ProgramData\FLEXNet」を削除しようとしましたが、効果がありませんでした。 手伝ってくれますか? Re: S32 Design studio for ARM 2.2 License problem こんにちは、 S32DS v2.2インストーラー(アップデート2なし)をダウンロードし、実行して再度アクティベートしてください。
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iMX93 セットアップ yocto 自動署名 SRK (imx-boot 用) こんにちは、 私はiMX93セキュアブートワークフローについて学んでおり、Yoctoと統合したいと考えています。 u-boot-imx の ahab ガイドのドキュメントに従って、SRK を uboot および関連するファームウェアに署名できるようになりましたが、プロセスは非常に複雑です。ドキュメントの指示に従って、uboot spl、uboot、atf ele などの yocto からのバイナリ出力を見つけ、特定の csf 設定ファイルとオフセットを使用して手動で署名しました。 そこで質問なのですが、この複雑なワークフローをYoctoに統合する方法はありますか?cstとkeyの場所を定義するだけで、Yoctoがimx-bootに署名してくれるような方法があれば教えてください。私の質問に答えてください。 注:私は自社製品にこのリポジトリのマニフェストを使用しています。https://github.com/nxp-real-time-edge-sw/yocto-real-time-edge/blob/real-time-edge-scarthgap/real-time-edge-3.0.0.xml Re: iMX93 setup yocto auto sign SRK for imx-boot こんにちは、@phuongchobo102さん このレイヤーを参照してください。 https://github.com/nxp-imx-support/meta-nxp-security-reference-design/blob/walnascar-6.12.49-2.2.0/meta-secure-boot/README.md よろしくお願いします、 志明
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FRDM-MCXN236 无法在 MCUXpresso IDE 中下载& 调试程序 客户:FlexPower PN:PMCXN236V 客户报告说,在测试期间,FRDM-MCXN236主板无法在MCUXpresso IDE中下载或调试软件开发工具包示例项目。他们已经尝试进入 ISP 模式,但编程和调试仍然失败。 使用 blhost,设备报告 MCXN236 处于不安全状态。客户想了解如何将设备恢复到出厂状态,以便可以正常下载和调试 SDK 示例项目。 C:\Work\blhost\blhost_2.6.7\bin\win>blhost-u 0x1FC9,0x0158 -- get-property 1 注入命令 "get-property" 响应状态 = 0 (0x0) 成功。 响应字 1 = 1258488320 (0x4b030200) 当前版本 = K3.2.0 C:\Work\blhost\blhost_2.6.7\bin\win>blhost-u 0x1FC9,0x0158 -- get-property 17 注入命令 "get-property" 响应状态 = 0 (0x0) 成功。 响应字 1 = 1520786085 (0x5aa55aa5) 响应字 2 = 3 (0x3) 网络安全状态 = 不安全 C:\Work\blhost\blhost_2.6.7\bin\win>blhost-u 0x1FC9,0x0158 flash-erase-all 注入命令 "flash-erase-all" 对命令 "flash-erase-all "的成功通用响应 响应状态 = 0 (0x0) 成功。 LinkServer RedlinkMulti 驱动程序 v25.6(2025 年 6 月 26 日 19:34:05-crt_emu_cm_redlink 版本 1017) 在 E: /temp/mcx/mcx_n236/world/frdmcxn236_hello_world/debug\ MCXN236.xml (5) 远程配置完成重新连接到现有的 LinkServer 进程。 探测固件:MCU-LINK FRDM-MCXN236 (R0e7) CMSIS-DAP V3.160(恩智浦半导体) 序列号:25ALGRSCQCA3F VID: PID:1FC 9:0143 USB 路径:0001:0017:00 在搜索优质核心后 使用内核 0 中的内存 (30) 仿真 器连接的处理器处于安全模式 (40) 调试暂停调 试接口类型 = CoreSIGHT DP(DAP DP ID 6BA02477)而不是 SWD TAP 0 处理器类型 = CoreSIGHT DP (DAP DP ID)DAP AP 上的 Cortex-M33( CPU ID 00000D21)0 硬件断点数量 = 8 闪存补丁数量 = 0 硬件监视点数量 = 4 个探测点( 0):已连接 & 重置。dpID:6BA02477。CpuID: 00000D21.信息: 调试协议:SWD。RTCK:已禁用。矢量捕捉:已禁用。 CoreSIGHT 调试 ROM 的内容: RBASE E00FE000:CID B105100D PID 0000095000 ROM(类型 0x1) ROM 1 E00FF000:CID B105100D PID 04000BB4C9 ROM(类型 0x1) ROM 2 E000E000:CID B105900D PID 04000BBD21 cST ARM armv8-M 类型 0x0 杂项-未定义 ROM 2 CID PID cST ARM cST ARM FPBv2 类型 0x0 其他——未定义 ROM 2:CID PID cST ARM ITMv2 类型 0x43 追踪源——总线 ROM 1:CID PID 04000BBD E0001000 B105900D 04000BBD21 E0002000 B105900D 04000BBD21 E0000000 B105900D 04000BBD21 E0040000 B105900D21 cSt 类型 0x11 Trace Sink — TPIU NXP:MCXN236 DAP 步幅为 1024 字节(256 个字) 已检查 v.2 片内闪存 mcxnxx.cfx 图像 'MCXNxxx Jun 26 2025 18:25:00' 打开闪存驱动 MCXNxxx.cfx 请求 VECTRESET,但 ARMv8-M CPU 不支持。使用 SOFTRESET 代替。 使用软复位运行闪存驱动程序 检测到闪存变体 'MCXNxxx (1024KB)' (1MB = 128*8K, 地址 0x0) 正在关闭闪存驱动程序 MCXNxxx.cfx 检查 v.2 片上闪存 MCXNxxx.cfx 图像 'MCXNxxx Jun 26 2025 18:25:00' 打开闪存驱动 MCXNxxx.cfx 请求 VECTRESET,但 ARMv8-M CPU 不支持。使用 SOFTRESET 代替。 使用软复位运行闪存驱动程序 检测到闪存变体 'MCXNxxx (1024KB)' (1MB = 128*8K, 地址 0x0) 正在关闭闪存驱动程序 MCXNxxx.cfx 已连接:was_reset=true。was_stopped=false 等待与 3330 端口的 telnet 连接 ... 启用 GDB 非停止模式 打开闪存驱动 MCXNxxx.cfx 请求 VECTRESET,但 ARMv8-M CPU 不支持。使用 SOFTRESET 代替。 使用软复位运行闪存驱动程序 闪存变体 “mcxnXXX (1024KB)”(0x0 时为 1MB = 128*8K)在闪存中 写入 13800 字节以寻址 0x00000000 失败读取 checksumSectors 消息就绪性——rc Em (12)。 目标拒绝调试访问位置 0x040048B0 发送操作 EraseSector 信息失败 - rc Em(12).目标拒绝调试访问位置 0x040048A0 关闭闪存驱动 MCXNxxx.cfx 状态-正在运行或正在执行重置请求-重读状态失败-rc Nn (05)。DAP 访问 中的 Wire ACK 故障,未能发送操作终止信息 - rc Em(12)。目标拒绝对位置 0x040048A0 的调试访问 Commit Flash 写入时出现目标错误:Em(12).目标拒绝了位置 0x040048A0 GDB 短截线的调试访问权限(C:\NXP\LinkServer_25.6.131\ 二进制文件\ crt_emu_cm_redlink)终止-GDB 协议问题:管道已被 GDB 关闭。 处理器处于非安全模式 状态-正在运行或正在执行重置请求-重读状态失败-rc Nn (05)。DAP 访问中的导线 ACK 故障 启动 ROM | 启动配置 | 闪存 开发板 MCX N 安全(Edgelock | 安全启动 | OTP) Re: FRDM-MCXN236 can't download & debug in MCUXpresso IDE 您好, 在我使用 MCUXpresso 安全配置工具 26.03 之后,我在 FRDM-MCXN947 上遇到了确切的问题。有什么办法可以解决这个问题? Re: FRDM-MCXN236 can't download & debug in MCUXpresso IDE 尝试批量删除,可能是 CFPA/CMPA 中的某些设置造成了问题。 你可以在 SPSDK 中使用命令行执行 nxpdebugmbox-i pyocd cmd erase-f mcxn947,也可以使用 SEC 工具按下批量擦除按钮。 Re: FRDM-MCXN236 can't download & debug in MCUXpresso IDE 尝试批量删除,可能是 CFPA/CMPA 中的某些设置造成了问题。 你可以在 SPSDK 中使用命令行执行 nxpdebugmbox-i pyocd cmd erase-f mcxn947,也可以使用 SEC 工具按下批量擦除按钮。 Re: FRDM-MCXN236 can't download & debug in MCUXpresso IDE 嗨,Sabina, 谢谢。它起作用了! 仅供参考,我使用的是 MCUXpresso 安全配置工具中的 CMPA 和 CFPA 的默认设置。一旦我执行 " 版本 image " 然后执行 " Write image ",就会出现这个问题。 Re: FRDM-MCXN236 can't download & debug in MCUXpresso IDE @alanlow 主要取决于你选择的配置文件,普通的未签名应该不会影响你在 mcuxpresso 中进行调试的能力,但是如果你选择了不同的配置文件,那么当你回到 mcuxpresso ide 时,可能会有其他设置导致错误。我建议如果你正在使用安全配置工具测试任何东西来版本和写入镜像,那么与其选择 " attach to to target " 这不会刷新映像,你应该连接到当前的运行点,而不是使用 mcuxpresso ide " 调试 "。
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在 S32K324 的 HSM 中创建/更新密钥目录的步骤 您好, 我们正在努力将 HSE 与 S32K324 结合使用。在哪里可以找到密钥目录的默认(基本)分配?此外,还想知道更新它的标准程序。 谢谢! 阿尼尔 Re: Procedure for create/update Key catalog in HSM for S32K324 你好@anilsp31PA HSE 固件参考手册修订版对此进行了描述。下节 2.7: 6.1.5关键目录 简而言之,只有在 CUST_DEL 生命周期中才能使用 HSE 服务 HSE_SRV_ID_FORMAT_KEY_CATALOGS(结构 hseFormatKeyCatalogsSrv_t)创建/格式化密钥目录。目录在安全内存中创建,只有 HSE 才能访问。用户只能通过 HSE 服务(格式化、密钥导入/生成/更新/删除等)访问密钥目录。 一旦生命周期升级到 OEM_PROD 或 IN_FIELD,就不能再更改或格式化目录了。 如果您使用 Autosar Crypto 驱动程序,请查看 RTD Crypto 驱动程序中包含的 SW 示例。它说明了如何配置目录以及应使用哪种应用程序接口。 目录格式所需的所有规则均可在上述部分找到。 此致, Lukas Re: Procedure for create/update Key catalog in HSM for S32K324 请参阅 S32K3xx 网络安全概述并提出-培训
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S32DS for S32 PlateForm过期 你好,我的S32DS软件显示licence已经过期,激活码为C90E-B544-714D-BEAE,麻烦帮忙延期一下。 Re: S32DS for S32 PlateForm过期 你好、 通过查看您的账户,您昨天已经激活了 S32DS v3.5,对吗?
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OsIf FreeRTOS 模式导致 UART DMA int 时从 ISR 上下文调用 vPortEnterCritical。 环境: - MCU:S32K324(双核 Cortex-M7) - RTD 版本:[S32K3_RTD_4_0_0_HF02_D2407_ASR_REL_4_7_REV_0000_20240725/ S32DS 3.5] - FreeRTOS 版本:[FreeRTOS 内核 V10.5.1] - OsIf 模式:从 OsIf_BareMetal → OsIf_FreeRTOS 更改 (IPCF 元器件所必需) 问题: 将 OsIf 切换到 FreeRTOS 模式后,当 UART Lpuart DMA 中断触发时,系统会崩溃。 崩溃调用堆栈: Lpuart_Uart_Ip_IrqHandler → Dma_Ip_SetLogicChannelCommand → SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_05 → OsIf_SuspendAllInterrupts() → vPortEnterCritical() ← 从 ISR 调用 → CRASH 我发现的根本原因是: 在 FreeRTOS OsIf 模式中,OsIf_SuspendAllInterrupts() 映射到 vPortEnterCritical(),这不是 ISR 安全的。 Mcl/DMA SchM 独占区是在 ISR 上下文中进入的,这与 FreeRTOS 关键部分的实现不兼容。 我找到的解决方法(但不能用于生产): 手动修补 OsIf_Internal.h,将 SuspendAllInterrupts 映射回"cpsid i" - 这是一个生成文件,将在 RTD 再生时被覆盖。 我的问题: 这是 RTD [RTD_4_0_0_HF02] 中的已知问题吗?它在较新的RTD版本中修复了吗? 参考:恩智浦社区也报告了类似的问题:https://community.nxp.com/t5/S32K/RTD-4-0-0p01-FlexCAN-with-FreeRTOS-asserts-in/m-p/1778228 Re: OsIf FreeRTOS mode causes vPortEnterCritical called from ISR context when UART DMA int 您好, 据我所知,FreeRTOS 上不正确的 SuspendInterrupts 抽象在 RTD500 中得到了修复。 请参阅 RTD 版本说明中的 ARTD-111453 项目。 BR, Petr
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OsIf FreeRTOS mode causes vPortEnterCritical called from ISR context when UART DMA int Environment: - MCU: S32K324 (dual-core Cortex-M7) - RTD version: [S32K3_RTD_4_0_0_HF02_D2407_ASR_REL_4_7_REV_0000_20240725/ S32DS 3.5] - FreeRTOS version: [FreeRTOS Kernel V10.5.1] - OsIf mode: changed from OsIf_BareMetal → OsIf_FreeRTOS (required by IPCF component) Problem: After switching OsIf to FreeRTOS mode, the system crashes when UART Lpuart DMA interrupt fires. Crash call stack: Lpuart_Uart_Ip_IrqHandler → Dma_Ip_SetLogicChannelCommand → SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_05 → OsIf_SuspendAllInterrupts() → vPortEnterCritical() ← called from ISR → CRASH Root cause I identified: In FreeRTOS OsIf mode, OsIf_SuspendAllInterrupts() maps to vPortEnterCritical(), which is not ISR-safe. The Mcl/DMA SchM exclusive areas are entered inside ISR context,  which is incompatible with FreeRTOS critical section implementation. Workaround I found (but not acceptable for production): Manually patching OsIf_Internal.h to map SuspendAllInterrupts back to "cpsid i" — this is a generated file and will be overwritten on RTD regeneration. My questions: Is this a known issue in RTD [RTD_4_0_0_HF02]? Is it fixed in a newer RTD release? Reference: Similar issue reported at NXP community: https://community.nxp.com/t5/S32K/RTD-4-0-0p01-FlexCAN-with-FreeRTOS-asserts-in/m-p/1778228 Re: OsIf FreeRTOS mode causes vPortEnterCritical called from ISR context when UART DMA int Hi, as far as I know incorrect SuspendInterrupts abstraction over FreeRTOS was fixed in RTD500. See ARTD-111453 item in RTD release note. BR, Petr
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[i.MX95 EVK REV A1][LF 6.6.52_2.2.2] Ported DMS demo: CPU works, NPU fails Hi NXP team, I am using an i.MX95 EVK REV A1 with BSP LF 6.6.52_2.2.2. I am currently evaluating the DMS demo on i.MX95. The DMS demo I am using was ported from the following source in branch lf-6.12.49_2.2.0: nxp-demo-experience-demos-list / scripts / machine_learning / dms Because my platform is i.MX95 EVK REV A1, I need to stay on LF 6.6.52_2.2.2 and cannot move to a newer BSP. Current status: - When I select CPU, the ported DMS demo runs normally. - When I switch to NPU, the camera preview is shown, but the DMS inference does not function correctly. This suggests that the DMS application flow itself is basically working, and the issue is likely related to Neutron/NPU model conversion or model compatibility. Environment: - Board: i.MX95 EVK REV A1 - BSP: LF 6.6.52_2.2.2 - eIQ Toolkit: v1.14.0 (Ubuntu 20.04 installer) - Conversion flow used: neutron-converter --input .tflite --target imx95 --use-python-prototype --output _converted.tflite What I confirmed: 1. The neutron-tuning environment itself is working. 2. mobilenet_v1_1.0_224_quant.tflite can be converted successfully. 3. The converted MobileNet model can run successfully on target with: /usr/bin/tensorflow-lite-2.16.2/examples/benchmark_model \ --graph=mobilenet_v1_1.0_224_quant_converted.tflite \ --external_delegate_path=/usr/lib/libneutron_delegate.so 4. The benchmark result shows that the Neutron delegate is actually being used successfully on target. However, DMS-related models fail during conversion: 1. face_detection_ptq.tflite - Fails in neutron_weights.py -> gen_add_params() - Error: IndexError: list index out of range 2. face_landmark_ptq.tflite - Fails in scheduling_if.py -> create_tile() - Error: TypeError: 'NoneType' object is not subscriptable - It seems related to network_node['padTLBR'][0] 3. iris_landmark_ptq.tflite - Fails with the same create_tile() / padTLBR NoneType issue I also tried: - --exclude-operator-types ADD but these DMS-related models still fail. Since: - the ported DMS demo works in CPU mode, - MobileNet can be converted and executed successfully on NPU, - only the DMS-related models fail during neutron-tuning conversion, my current understanding is that the board runtime/delegate environment is functional, and the problem is specific to the DMS model conversion path. My questions are: 1. Are face_detection_ptq.tflite, face_landmark_ptq.tflite, and iris_landmark_ptq.tflite officially supported by i.MX95 neutron-tuning on LF 6.6.52_2.2.2? 2. Is there any known limitation for these DMS-related models on i.MX95 EVK REV A1 / LF 6.6.52_2.2.2? 3. Is there any patch, updated neutron-tuning package, or pre-converted DMS Neutron models available for this BSP? 4. For i.MX95 EVK REV A1 with LF 6.6.52_2.2.2, is the DMS demo expected to run on NPU, or CPU only? Any suggestions would be appreciated. Thank you. Re: [i.MX95 EVK REV A1][LF 6.6.52_2.2.2] Ported DMS demo: CPU works, NPU fails Hi @ChuckYang  You can try L6.12.20, which is the last version to support the A1 chip. However, even with L6.12.20, certain detection models still cannot produce correct results due to design issues with the chip’s internal NPU. Therefore, the ultimate solution is to use the B0 chip. Best Regards, Zhiming Re: [i.MX95 EVK REV A1][LF 6.6.52_2.2.2] Ported DMS demo: CPU works, NPU fails Hi Zhimin, Thanks for your feedback. I followed your suggestion and tried BSP 6.12.20 on the i.MX95 A1 EVK. Here is my current test result on BSP 6.12.20: 1. I ported the DMS demo to the BSP 6.12.20 environment. 2. I used the DMS demo to download the following four original models: - face_detection_ptq.tflite - yolov4_tiny_smk_call.tflite - face_landmark_ptq.tflite - iris_landmark_ptq.tflite 3. Then I used neutron-converter.exe from eIQ Toolkit v1.17.0 to convert these models for i.MX95. The converter version I used is: eIQ_Toolkit_v1.17.0 MCU_SDK_25.06.00 + Linux_6.12.20_2.0.0 4. All four models can be converted successfully. 5. I also tested the converted model on the EVK by using benchmark_model with the Neutron delegate. The benchmark_model test can finish successfully, and the log shows that the EXTERNAL delegate can be created. 6. However, when I replaced the DMS demo models under: /opt/gopoint-apps/downloads/ and ran the DMS demo again, the result was still the same: - CPU mode can work. - NPU mode still does not work properly. - The DMS detection result is not updated correctly when NPU mode is selected. I attached the following two logs for your reference: - neutron-converter.log - benchmark_model.log Could you help confirm whether my test result matches the A1 internal NPU design issue you mentioned? In other words, for the i.MX95 A1 chip, even with BSP 6.12.20 and the converted models, is the DMS demo NPU mode not expected to work correctly for these detection models? If so, is the recommended workaround for A1 to use CPU mode only, and the final solution for correct DMS NPU acceleration is to use the i.MX95 B0 chip? Thanks. Re: [i.MX95 EVK REV A1][LF 6.6.52_2.2.2] Ported DMS demo: CPU works, NPU fails @Zhiming_Liu  Sorry, I forgot to mention you in my previous reply. Could you please help check the test results above? Thank you.
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How should the PTN3460I be started? Currently, there are some issues with the PTN3460I prototype. I am unable to identify this chip through the IIC method. Could it be that there are problems with the startup method or process? The LCD screen is selected as LVDS single bus, 24 bpp, VESA data packing. The dual-channel in CFG1 has been changed to single-channel. Also, the HPDRX pin on the chip, which is directly connected to the EDP-HPD pin on the CPU (after level conversion), does there need to be any other logic inversion? Re: How should the PTN3460I be started? Hello Zhaozhiling Good day! I have 3 observations that I would like to discuss with you 1.- Is the PTN3460I working as a slave or a master? 2.- Could you try removing the RST_N capacitor? I want to verify that the charging time doesn't interfere with the device startup and cause a mid-process reset.   3.- The investment in HPDRX isn't necessary, but could you graph it? I want to see the signal in HPDRX at startup. Given that the HPDRX pin is internally connected to GND through an integrated pull-down resistor (> 100 k), the DP source will see HPDRX pin as LOW indicating that the DisplayPort receiver is not ready when the device is not powered. This helps avoid raising false events to the source. After power-up, PTN3460I continues to drive HPDRX pin LOW until completion of internal initialization. After this, PTN3460I generates HPD signal to notify DP source and take corrective action(s). I will be waiting for your response Have a great day and best of luck.
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ocpp stack on iMX93 Hello NXP Community,  We are planning to use iMX93 on a fast charger product, where we need to use free version of OCPP 1.6 and upgradable (in future).  Does NXP provide such support on iMX93 ?  Re: ocpp stack on iMX93 Hi, Please refer to the EVSE MPU platform, a development kit for fast charging. https://www.nxp.com/design/design-center/development-boards-and-designs/EV-CHRG-STN-MPU Best Regards, Zhiming
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iMX93 上的 ocpp 堆栈 您好,恩智浦社区, 我们计划在快速充电器产品上使用 iMX93,我们需要使用免费版的 OCPP 1.6,并可升级(将来)。 恩智浦是否在 iMX93 上提供此类支持? Re: ocpp stack on iMX93 您好, 请参阅 EVSE MPU 平台,这是一个用于快速充电的开发套件。 https://www.nxp.com/design/design-center/development-boards-and-designs/EV-CHRG-STN-MPU 致敬, Zhiming
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