使用 NXP 控制三相感应电动机 大家好，我打算使用 NXP Devkit 之一构建一个新的三相交流感应电机驱动器。我将使用无传感器磁场定向控制技术。到目前为止，我一直在考虑使用 NXP MPC5744P Devkit，但我需要您的帮助，这是否是一个好的选择？我还需要找到一个示例 SIMULINK 模型来帮助我。

usb8997 (Murata LBEE5XV1YM) Firmware Crash on Scan — Reproducible on Multiple Driver Stacks (moal/ml Hello NXP team, We're encountering a consistent and reproducible crash on the Murata LBEE5XV1YM module (Marvell usb8997 chipset) during scan operations, and would appreciate your insights or access to alternate firmware/debug builds. Environment Overview Chipset: Marvell usb8997 (Murata LBEE5XV1YM) Firmware: nxp/usbusb8997_combo_v4.bin Kernel: 5.15.0-136-generic Drivers tested: Custom out-of-tree moal.ko / mlan.ko In-kernel default mwifiex_usb Platform: x86_64 Ubuntu (USB host, no hub) Issue Summary The module crashes and resets (USB disconnect) immediately after initiating a Wi-Fi scan. This happens: With both minimal and full scans (e.g., iw dev ... scan freq 2412) On both moal/mlan and mwifiex_usb stacks Regardless of BT being disabled (fully tested) With power management settings already adjusted (autosuspend=-1, power/control = on) The crash only occurs when issuing a scan, otherwise the firmware boots and interfaces initialize cleanly. Key Log Snippet Crash immediately follows scan start: wlan: wlx9c50d1e343a4 START SCAN DNLD_CMD: 0x107 (scan request) ... Card is removed: -71 usb 3-5: USB disconnect, device number X mlan_shutdown_fw..... Debug Steps Taken Verified firmware loads correctly and interface comes up (wlx...) Disabled BT (crash still occurs) Tested both default (mwifiex) and MOAL driver stacks → same issue Scan fails even with restricted frequency scan (scan freq 2412) Regulatory domain forced to US (iw reg set US) → crash still occurs Crash is always triggered during scan cmd (0x107) drvdbg=0xffffffff set for full trace (no obvious root violation surfaced) USB power management verified: not in autosuspend; persistent power Ask Could you confirm if this is a known firmware issue with usb8997_combo_v4.bin? Is there a stable or debug version of firmware we can test (with scan stability improvements)? Are there known workarounds or module parameter changes that can mitigate this scan crash? Below is how i load my driver: // load the driver sudo insmod mlan.ko sudo insmod moal.ko fw_name=mrvl/usbusb8997_combo_v4.bin cal_data_cfg=none cfg80211_wext=0xf drv_mode=2 drvdbg=0xffffffff PFA: 1. driver_file.zip (which has mlan.ko and moal.ko) 2. dmesg_log.txt and detailed_dmesg_log.txt (with drvdbg=0xffffffff) 3. fw bin = usbusb8997_combo_v4.bin We're currently aiming to identify the root cause (RC) and resolution (RCA) as soon as possible, since this issue is currently blocking our integration of the Murata LBEE5XV1YM module into our platform. We truly appreciate your support and guidance on this — thank you in advance! Regards, RS Re: usb8997 (Murata LBEE5XV1YM) Firmware Crash on Scan — Reproducible on Multiple Driver Stacks (moa Noted, thanks! Re: usb8997 (Murata LBEE5XV1YM) Firmware Crash on Scan — Reproducible on Multiple Driver Stacks (moa Dear @rikins , See below, please! 1. Driver on github Here is the document for the driver on github. https://www.nxp.com/docs/en/release-note/RN00104.pdf the driver supports the following soc and interfaces: So you can see the driver doesn't support 8997 usb, but it supports SDIO for wifi and UART for Bluetooth on 8997, also support PCIe for WiFi and UART for Bluetooth on 8997. 2. Steps to get the driver on github ① Driver code # git clone https://github.com/nxp-imx/mwifiex.git # cd mwifiex # git tag …… android-15.0.0_1.0.0 automotive-11.0.0_2.1.0 …… automotive-14.0.0_2.1.0-imx95-er automotive-14.0.0_2.3.0 …… lf-5.15.71-2.2.1 lf-5.15.71-2.2.2 lf-6.1.1-1.0.0 lf-6.1.22-2.0.0 lf-6.1.36-2.1.0 lf-6.1.55-2.2.0 lf-6.1.55-2.2.1 lf-6.1.55-2.2.2 lf-6.6.23-2.0.0 lf-6.6.3-1.0.0 lf-6.6.36-2.1.0 lf-6.6.52-2.2.0 Assume you are using linux kernel 6.6.52. #  git checkout lf-6.6.52_2.2.0 ② Firmware & wifi_mod_para.conf https://github.com/nxp-imx/imx-firmware/tree/lf-6.6.52_2.2.0/nxp --FwImage_8997,           --->pcieuart8997_combo_v4.bin, PCIe wifi & uart bluetooth firmware together. --FwImage_8997_SD         --->sdiouart8997_combo_v4.bin, SDIO wifi & uart bluetooth firmware together. The driver doesn't support sdio wifi & sdio for bluetooth. Thanks! Regards, weidong Re: usb8997 (Murata LBEE5XV1YM) Firmware Crash on Scan — Reproducible on Multiple Driver Stacks (moa Hi @weidong_sun , Thanks for your input. we'll follow the said instructions for usb8997. I appreciate it!! Doubt: Is this only specific to usb? I hope pcie and sd will work fine. Please lmk about the working steps of sd8997 for arm arch. What I have tried is: 1. cloned the https://github.com/nxp-imx/mwifiex.git repo. 2. cross compiled it for my toolchain. (SD8997=y) 3. Use sdsd8997_combo_v4.bin (PFA) Are the above steps correct? Please lmk if i have overlooked anything. Regards, RS Re: usb8997 (Murata LBEE5XV1YM) Firmware Crash on Scan — Reproducible on Multiple Driver Stacks (moa Dear @rikins , It is not feasible to use default driver in linux Kernel. you have 2 ways to get NXP 88W8997 driver: 1.. Getting mass market driver from github. But usb driver for 88W8997 is not for mass market, so driver on github doesn't support your application. 2. Downloading driver from nxp website. I checked USB drivers on website,  the following driver covers 5.15.x kernel version. NXP_L_USB-USB-8997-U16-X86-W8997-W16.197.121.p1-16.26.121.p1-MXM5X16505.p7.2_V4-GPL.zip Link is : https://www.nxp.com/products/wireless-connectivity/wi-fi-plus-bluetooth-plus-802-15-4/2-4-5-ghz-dual-band-2x2-wi-fi-5-802-11ac-plus-bluetooth-5-3-solution:88W8997?ticket=ST-5832-7we6ff1kJNj4Xpc8-xPWOW35Dtc-www.nxp.com#myDocument The driver is Secure File,  customer needs to following these 2 steps to get it. --NDA is required. --Applying for access rights After NDA is done, begin to apply for access rights like this: www.nxp.com--login---My NXP Account---Secure Files--fill out information--submit--wait for approval from product manager. Thanks! Regards, weidong

NXP FreeRTOS library hi, i wanna build a library using NXP FreeRTOS. so let me know about the method to make a library with my function. (like myLibrary.h and myLibarary.a) thanks. using software configuration 1) S32DS.3.5_b220726_win32.x86_64.exe 2) SW32_S32DS_3.5.8_D2311 package 3) SW32_S32DS_OfflineDevPack_3.5.0_D2207 package 4) SW32K3_RTD_4.4_3.0.0_P01_D2303_DS_updatesite package 5) NXP FreeRTOS 10.0.5 package *System Clock : use default clock (peripheral - os - freertos - General option) Re: NXP FreeRTOS library Hi @jwjung  For guidance on creating and adding a library in S32 Design Studio. I recommend taking a look at the following links, which provide detailed instructions that might be useful for you: How to create a lib file and add it to another project with S32DS HOWTO: Add a static library file into S32DS GCC project Check them out and see if they help! If it is not quite what you are looking for or you have more questions, just let me know.  BR, VaneB

How to create copy of existing RTD project How to create copy of existing RTD project in the same workspace with different name in S32DS for S32 Re: How to create copy of existing RTD project In Project Explorer of S32DS, you can directly copy-paste the required project and it will open a window to select new name: You can also rename the .mex file.

FRDM-MCXA153 Full Speed USB Hi, i tried running an USB example named "dev_cdc_vcom_bm" on FRDM-MCXA153 board, where it creates a virtual COM port, and echos back the characters sent though terminal using that specific VCOM port.  i can see the VCOM appeared in device manager has a default name "USB Serial Device" as shown in the image attached, but i need to change this default name to a custom name, using example code usb files itself,  but not in device manager settings. Please let me know the steps required to do this name change of VCOM , or any changes to be done in usb example driver files . Thanks. Development Board MCXA USB Re: FRDM-MCXA153 Full Speed USB thank you for clearing the doubt Re: FRDM-MCXA153 Full Speed USB Hello @Gurunath  I don't think this can be changed in USB stack.  This is determined by the USB drive on PC. BR Alice Re: FRDM-MCXA153 Full Speed USB Thank you for the solution . It would be great help to me if u can let me know if there is a way to do the same thing using usb stack code for frdm-mcxa153 in MCUXPRESSO IDE? . Re: FRDM-MCXA153 Full Speed USB Hello @Gurunath  We need to change the driver configuration to change name. My PC is Win10, I will show the steps  about how to change this default name to a custom name on my side. Step1. Right click "USB Serial Device" on Device Manager of PC. Step2, Choose "Driver key" under Details view. Copy the Value. Step3,  Open and run Registry as Administrator. Step4, Search the "value" copied in step2. Step5, change name as below: Step6, Reset board. Show as below. If your PC is another system, you can also google like " how to change USB device name on xxx system". BR Alice

LPC845断电 大家好， 我正忙于使用 LPC-845 定制电路板来开发遥控器。 但是，我无法让系统进入设备说明书中规定的消耗电量的模式。 在断电模式下，电流不会低于 500 uA。 因此我拿 LPC845-BRK 板进行测试（没有连接外围设备，并且在 JP1 跳线上很容易测量） 仍然没有运气，尝试了一切（参见附件的源代码）来查看是否忘记了什么。 断电时为 500 uA，深度断电时为 320 uA。 那么我是不是忘记了什么？ 此致， 短剑。

Where do I enter a "post-build" step (script) when using MCUXpresso for VS Code? I converted a project from the MCUXpresso IDE to MCUXpresso for VS Code.   I have everything working except for the "post-build" steps... In MCUXpresso, post-build steps can be specified in Properties->C/C++Build-?Settings->BuildSteps Where is the equivalent in the VS Code version? Thanks!  Re: Where do I enter a "post-build" step (script) when using MCUXpresso for VS Code? Thanks!! Re: Where do I enter a "post-build" step (script) when using MCUXpresso for VS Code? Hi, We did not implement this to be automatically done yet. We'll add it in a future release. Till then, you can work around the issue by adding a custom command with post build step (in CMakeLists.txt) like in the example below: ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND echo ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME})   Some other example, if you import from SDK a multicore project, core1 is generating a bin from an executable file in a similar post build command: ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/core1_image.bin) Regards, Cristian

FS26 Not Entering Standby & Initialization Fails – FS_STATE Hello NXP Support, I’m working with the following example from your knowledge base: RTD Example: FS26 WKUP with PGOOD and EXTWAKE using a S32K3X8EVB My goal is to put both the FS26 and the S32K3X8 controller into standby mode. While the controller successfully transitions to standby, the FS26 remains in the same state and does not follow. Additionally, the function call: eReturnValue |= Sbc_fs26_InitDevice(); returns not_ok, and the initialization process fails. Upon debugging, I found that Sbc_fs26_GetDeviceState() is returning 0x14 as the FS_STATE value. According to the FS26 datasheet, I couldn't find any documentation clearly explaining the meaning of this value, particularly bit 4 (i.e., 0x14 = 0b10100). Could you please clarify what bit 4 represents in the FS_STATE register? It's not mentioned in the register description section of the datasheet. I also came across this related post that seems to touch on a similar issue, but there is no clear resolution provided: FS26 FS_STATES & SPI Communication Could you please assist with the following: Why is the FS26 not transitioning to standby mode alongside the S32K3X8? What does the FS_STATE value 0x14 indicate, specifically the significance of bit 4? What are the possible reasons for Sbc_fs26_InitDevice() returning not_ok? Any guidance or clarification would be greatly appreciated, especially regarding the undocumented FS_STATE bits. Re: FS26 Not Entering Standby & Initialization Fails – FS_STATE Thank you for your response. I checked the suggested solution, but it was still showing the same issue. On further debugging, I found that the system was entering the INVALID_FS state and was not updating any configurations from the peripherals. I reviewed the default register values and identified the SBC_FS26_FS_GRL_FLAGS_ADDR register, which indicated an overvoltage fault. Upon checking the SBC_FS26_FS_OVUV_REG_STATUS_ADDR register, I saw that it was a VMON_EXT overvoltage condition. After adjusting the circuit connection and changing the resistance values, the issue was resolved. The system now transitions properly into the FS_Init state, and other operations are working as expected. Thanks again for your support. Re: FS26 Not Entering Standby & Initialization Fails – FS_STATE You can try to change green circled as 'no effect on RSTB and FS0B' this in S32DS: disabled watchdog period No monitoring the FCCU function Re: FS26 Not Entering Standby & Initialization Fails – FS_STATE 1. Before entering standby mode, what state is the FS26 in? How are you attempting to transition it into standby mode? I’m using the S32K358 development board, which includes the FS26 with the default configuration. I’m currently testing the example code provided by NXP[mentioned link in the post]. However, the Sbc_fs26_InitDevice() function is returning NO_OK, indicating the initialization is failing. As a result, the FS26 is not transitioning to the FS_INIT or any other operational state. When I read the FS_STATE register, I’m getting 0x14.   2. What does the FS_STATE value 0x14 indicate, particularly the significance of bit 4? If this value doesn’t match any entry in the table shown in your screenshot, does it still have any defined meaning? Also, why does the register use 4 bits when all documented FS states seem to be covered within 3 bits? The table mentions “Actual State of the Fail-Safe State Machine,” so is bit 4 indicating a special fault condition or an undocumented state? Re: FS26 Not Entering Standby & Initialization Fails – FS_STATE HI  Why is the FS26 not transitioning to standby mode alongside the S32K3X8?[gw]before enter into standby mode,what's the mode of FS26? how did you operate it enter into standby mode? What does the FS_STATE value 0x14 indicate, specifically the significance of bit 4? [gw]If no match the table value in your post picture, there is meaningless for this result. What are the possible reasons for Sbc_fs26_InitDevice() returning not_ok?[gw]I should know answer in my quesitons1 reply. Re: FS26 Not Entering Standby & Initialization Fails – FS_STATE @YvanR Can you please have a look.

S32K344 - LPSPI および DMA 構成 NXPのエキスパートの皆さん、こんにちは! 私はEVKのループバックでSPI通信を開発し始めています。 SPI が Tx と Rx (マスターとスレーブの両方) の DMA で構成された例はありますか。 どうもありがとうございます！ 日時:S32K344 - LPSPIおよびDMAの構成 サポートしてくれてありがとう、 このトピックを終了します。3番目の質問については、送信者と受信者を指定できる半二重モードが答えだと思います。 どうもありがとうございます！ 日時:S32K344 - LPSPIおよびDMAの構成 ハード faul ハンドラは、main.c の 220 行目のタイプミスが原因で発生しました。 Lpspi_Ip_AsyncTransmit(&MASTER_EXTERNAL_DEVICE, TxMasterBuffer, RxMasterBuffer, NUMBER_OF_BYTES, TIMEOUT); コールバックでTIMEOUTを変更しましたが、LSPI間でデータが交換されません。 エラーをありがとう、そして申し訳ありません。 Re: S32K344 - LPSPI and DMA configuration 基本的なLPSPI + DMAのサンプルを提供していただきありがとうございます。S32K344MINI-EVBで6.0.0 RTDを使用するように、あなたのプロジェクトを修正しました。lpspi2の代わりにlpspi1を使用しました。lpspi0はArduinoヘッダーを介してlpspi1に接続されています。また、USBデバッグケーブル経由で経過時間を出力するためにlpuart6を追加しました。

Add validation to u-boot cmd setenv Hello All, I want to add a validation rule to a custom variable I'm defining in the u-boot environment. Let's call it foo, and the only values foo should accept are null or ttyLP0,115200. My u-boot environment is protected, so only specific variables are whitelisted. foo will be whitelisted. I was able to achieve this for fw_setenv by creating patch for libubootenv under src/fw_printenv.c for the Linux user-space: root@localhost:~# fw_setenv foo woof Error: invalid value for "foo": woof root@localhost:~# root@localhost:~# fw_setenv foo null root@localhost:~# fw_printenv | grep foo foo=null Now, I'm trying to figure out how to do this for u-boot-imx setenv. I looked into the cmd/nvedit.c function env_set and applied the same logic, but that did not work. Am I in the right place for setenv, or is there different code for setenv? Any help will be highly appreciated.  Cheers,  i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Security Yocto Project Re: Add validation to u-boot cmd setenv Correct function was _do_env_set Re: Add validation to u-boot cmd setenv @Bio_TICFSL  I was able to find the right function and patch it through with my validation rule. Correct function was _do_end_set in cmd/nvedit.c. Autoboot in 3 seconds => setenv current_console woof ## Error: invalid value for "current_console": woof => setenv current_console null => printenv current_console current_console=null Thank you for your support. Re: Add validation to u-boot cmd setenv @Bio_TICFSL  Thank you for the feedback and the links. Maybe I was not clear enough, but what I'm looking for is the C-code implementation of setenv so I can add my validation rule. So when a user executes from the u-boot prompt: => setenv foo 'woof' It should reject it with an error. It should only accept null or ttyLP0,115200 as input values, or it should reset the value back to its original state. Similar to environment variables serial# and ethaddr, which you cannot reset. You can setenv and saveenv, but on the next reset, it will set back to its original value. As I explained in my first post, I did add the code in cmd/nvedit.c function env_set, but I'm not sure if this is the right function for setenv or if there is another function call. I hope I have made my request clearer now. What I'm trying to achieve is a way to enforce validation rules directly within the setenv function in the u-boot code. Thank you for your assistance. Re: Add validation to u-boot cmd setenv Hello, You must saveenv the variables, but please check this page> https://docs.u-boot.org/en/latest/usage/environment.html https://community.nxp.com/t5/i-MX-Processors/U-boot-Environment-Variables-Source-Code/m-p/974719 Regards

i.MX8ULP用eMMC使用に関するお問い合わせ i.MX8ULP Single Boot Modeのブートイメージの保存にeMMCを使用したいのですが。 ブートイメージを保存するeMMC領域を除いて、特定の空のメモリ領域があると思います。 特定の空のメモリ領域をアプリケーションのデータを保存する領域として使用できますか? eMMCは、データ保存用のフラッシュメモリだけでなく、ブートイメージ保存用のメモリも同時に使いたいです。

s32k3 basic secure boot, how's the root of trust？ 从文档中看是修改IVT的BOOT_SEQ，进入安全启动。那如果别人再修改flash中的IVT，去掉BOOT_SEQ，是否就可以绕过安全启动，从bootloader开始就是篡改的代码了？ Based on the documentation, it seems that modifying the BOOT_SEQ in the IVT enables secure boot. However, if someone else modifies the IVT in the flash memory and removes the BOOT_SEQ, could they bypass secure boot and start running tampered code from the bootloader? 回复：s32k3基本安全启动，信任根怎么样？ HSE 提供以下功能： IVT 可以基于“BOOT_DATA_SIGN”服务保护 IVT 内容免遭未经授权的更改，其工作方式类似于 BSB 模式。计算身份验证标签并将其附加到 IVT 的末尾。要启用 IVT 身份验证，必须将一次性可编程 HSE 系统属性 IVT_AUTH 设置为 1。'

fs23 が LPOFF の入力に失敗する FS23がLPOFFモードに入るように制御するために、S32K312を使用してSPI経由でFS23と通信しています。次のように、SPI を介して LPOFF コマンドを送信しました。 まず、SBC_FS23_M_SYS_CFG_ADDRレジスタの値を読み取ります。 Sbc_fs23_ReadRegister(1, SBC_FS23_M_SYS_CFG_ADDR, &M_Sys_Cfg_RxData); 次に、SBC_FS23_M_SYS_CFG_ADDRレジスタの読み取り値を書き込み、LPOFFスリープモードのSBC_FS23_M_GO2LPOFF_MASKを0x0040(1<<6)に設定しました。 Sbc_fs23_WriteRegister(1, SBC_FS23_M_SYS_CFG_ADDR, M_Sys_Cfg_RxData |SBC_FS23_M_GO2LPOFF_MASK、&pu16RxData_LDT); しかし、FS23はLPOFFモードに入らず、再度レジスタ値を読み込んでも変化していませんでした。SPI通信が正常に機能していることを確認できます。外部ウェイクアップ ソースが接続されていません コンフィギュレーションに問題があるのか、それともコンフィギュレーションが必要な他のレジスタがあるのか、教えてください。 日時:fs23がLPOFFに入るのに失敗する SPIがレジスタへの書き込みに失敗したため、この状況につながったためであるべきだとわかりました。ただし、fs23 は実際には通常モードであり、ウォッチドッグ タイマーも無効になっています。しかし、SPIを介してデータを読み取るのに問題はなく、データの書き込みも正常に返されます。 日時:fs23がLPOFFに入るのに失敗する M_IOWU_FLGレジスタ 日時:fs23がLPOFFに入るのに失敗する どのレジスタに入っているか教えていただけますか? 日時:fs23がLPOFFに入るのに失敗する 1.M_SYS_CFGレジスタの値は21507(0101010000000011)です。 2.表記値は21571(0101010001000011)です。 書き込みが成功したかどうかを確認する 3.To、再読み取りする値も21507(0101010000000011)です。 この問題は何日も私を悩ませてきました。何か指導をお願いします。 日時:fs23がLPOFFに入るのに失敗する きっとノーマルモードになっていると思いますので、レジスタSBC_FS23_M_SYS_CFG_ADDR(0x05)に書き込んでLPOFFモードに入りたいです。私の手順は次のとおりです。 ステップ1:SPIを介してレジスタSBC_FS23_M_SYS_CFG_ADDR(0x05)の値を読み取ります。 ステップ2:この値とSBC_FS23_M_GO2LPOFF_LPOFF(0x0001U << SBC_FS23_M_GO2LPOFF_SHIFT)の間でビットごとのOR演算を実行し、結果をSBC_FS23_M_SYS_CFG_ADDR(0x05)に書き戻してfs23をスリープモードにします。 日時:fs23がLPOFFに入るのに失敗する M_STATESレジスタ値12295(バイナリ表現:0011000000000111)について、bit13は1でノーマルモードを示します。 M_SYS_CFGレジスタの値は 21507 (0101010000000011) ですが、正常に変更されていません。 Re: fs23 fail to enter LPOFF 本当に通常モードですか？LPOFFモードに入るためにどのようなコマンドを送信しましたか？ Re: fs23 fail to enter LPOFF M_SYS_CFGレジスタを「xxxx x000 0100 0011」と書きます。試してみてください。「x」は任意の値を表します。 日時:fs23がLPOFFに入るのに失敗する ステップ1:SPIを介してレジスタSBC_FS23_M_SYS_CFG_ADDR(0x05)の値を読み取ります。 [gw]读出来的值是多少这个寄存器？ ステップ2:この値とSBC_FS23_M_GO2LPOFF_LPOFF(0x0001U << SBC_FS23_M_GO2LPOFF_SHIFT)の間でビットごとのOR演算を実行し、結果をSBC_FS23_M_SYS_CFG_ADDR(0x05)に書き戻してfs23をスリープモードにします。 [gw]写进去 M_SYS_CFG register 的值是多少？写过以后有没有再读一下验证写成功有否？

IMXRT1052 XIP 暗号化の問題 専門家に聞いてもいいですか:RT1052 + XIP暗号化方式?ヒューズを燃やさずにチップのUIDをキーとして使用する場合、イメージを暗号化して生成するにはどのソリューションを選択すればよいですか?ヒューズを燃やした後、チップが再利用できなくなるのが心配だからです。暗号化のための良い方法があるかどうか尋ねてもいいですか。また、工場にとっても大量生産を促進することは有益です。 Re:IMXRT1052 XIP暗号化の問題 こんにちは： MFGTOOLはUSBのみをサポートし、UARTをサポートする製品ソフトウェアを持っていますか?

How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk As per the calculation the BCLK frequency  required is 2304000Hz. I seem to be getting the FXCOMCLK7 clkin(23.04Mhz) as a multiple of BCLK required. But MCLK also has to be multiple of BCLK. But MCLK seem to be not using the fractional clock divider output. Please share some inputs to configure the clock correctly Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk The noise sound issue is resolved after updating the Dma input buffer to the I2S. I was using same address as DMA source address. Updated it to a ring buffer as in SDK example to resolve the issue. Thanks Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk 2 channels. I think I am able to generate the clocks properly. MCLK is 46.08 Mhz, Bclk is 2.304 Mhz(Verified with DSO). Audio is playing with small noise in the output sound. Could you share some inputs to debug. Do we need to update any setting for the codec when we update the the sampling rate to 48 khz in 24 bit mode. I have used sdk example lpcxpresso55s69_dev_audio_speaker_freertos as reference Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk Hello @dawnpaul100  Please tell me how many channels does your I2S have? BR Alice

Questions about the internal SRAM of S32G Hi， I recently tested the bootloader to boot multi-core programs and found that the bootloader will move the complete bin file of each M7 core from QSPI to internal SRAM and then execute it. However, I noticed that the internal SRAM of S32G2 is only 8M, and the space allocated to each M7 core in LD is about 1M. Question: If my M7 core program is very large, such as 10M, how should I operate it? thanks， Re: Questions about the internal SRAM of S32G Hi chenyi,     As we know, if multi-core is enabled, it takes a long time for A-core to boot Linux. During the startup of Core A, if Core M collects 100MB of data that requires saving, how should this be handled?      I'm having this problem right now.S32G QSPI issue - NXP Community Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. In common,  the 8M of SRAM should be bigger enough to run a M7 application, I suggest checking the code to reduce the size. Regarding to XIP, yes, it is theoretically supported,  but there are no example or some documentations about XIP on S32G. It's not easy and not common to implement XIP from NOR flash on S32G,  the S32G didn't have internal nor flash, so the cpu can not directly access the nor flash. you could use a bootloader to initialize the QSPI controller and DDR controller at first and then let cpu to execute the application stored in Qflash or DDR on running time. I hope it will help.  BR Chenyin Re: Questions about the internal SRAM of S32G hi, 已解决: S32G2xx M7 execute code from external flash ? - NXP Community I saw this document introducing an XIP(eXecute-In-Place) mechanism that can execute code from external flash. Do you have any relevant materials or demos? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for you reply. As per my understanding, there is not formal sample/document regarding to this topic, you may reference the ddr init code from A53 side if willing to initialize the DDR for M7 side. Sorry for your inconvenience. BR Chenyin Re: Questions about the internal SRAM of S32G hi， Do you have any relevant demos or materials within NXP? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. Yes, I think both method may work for your situation, but as far as I know , most customers do not use DDR from M core side, it is  one option to solve your specific case. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， What do you mean, if the M core wants to execute a large image, there are two options: 1. M7 first transfers a portion of the code to the internal SRAM for initializing DDR. After initializing DDR, the complete code is transferred to DDR for execution; 2. The M7 core waits first, and after the A core initializes the DDR, it moves the M7 core image to the DDR and executes it; Is that so? Re: Questions about the internal SRAM of S32G Hello, @youke  Thank for the reply. If the large size image is indeed caused by code(for example, large libs linked) and cannot be resized via linker file, then it cannot be directly loaded to the SRAM to run.  if so, I think you may have to initialize the DDR for running the code. But, unlike A53 side, the DDR is not by default enabled from sample code/bootloader from M7 side. BR Chenyin Re: Questions about the internal SRAM of S32G hi, Thank you for your reply Because I have written too much code, the compiled file is very large. Based on your answer, S32G2 does not support M7 core images exceeding 8MB because they cannot be copied to internal SRAM for execution. Is that correct? Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. I am not sure why your images are so large, since they have been far larger than the 8M ram size(24 M in total). One possible method is to check the linker file, for example,  edit it to make it to 1-2M size each. Then re-build 3 images, note that do not overlap the address of each other. If the big size of image is because multi-libs linked(large sized libs), then edit the linker file may not work for the case from my understanding. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， We will use three M7 cores to run separate programs here, with each core having an image size of approximately 8M, totaling 24M, Because the internal SRAM of S32G2 is only 8MB, how should I plan the LD file thanks, Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your post. In common, the actual size of the M7 image would not be that so big, if so, I suggest modify the linker file to change the address range of each part, thus resize the image.  BR Chenyin

LS1043A消費電力 「Core benchmark use cases」では、i.MX 93のアプリケーションノートAN13917、i.MX 8MのAN12778と同様に、LS1043Aプロセッサの消費電力を測定していますか? Re:LS1043A消費電力 この情報については、LS1043Aデータシートの表10を使用できると思います-ありがとう。

IMX8MP : common MDC and MDIO pins for FEC and eQOS (two Ethernet PHY) Hello, We have a custom board based on IMX8M plus. We are using two different Ethernet Phy (DP83867) ,   1)eQOS 2)FEC these both Phy are using common MDIO (AH29) and MDC(AH28) pins. Is it possible to use common MDIO and MDC pins for FEC and eQOS ? If yes, what changes are required ? Please guide us for the same. Thanks and Regards, Ishan  Re: IMX8MP : common MDC and MDIO pins for FEC and eQOS (two Ethernet PHY) Hi, Thank you for your interest in NXP Semiconductor products, The change required would be to add another phy sub-node to the proper MDIO node, for example, if the i.MX 8M Plus FEC module is used, this would be the rework: &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; snps,force_thresh_dma_mode; snps,mtl-tx-config = <&mtl_tx_setup>; snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; }; &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rgmii-id"; phy-handle = <&ethphy1>; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; realtek,clkout-disable; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; realtek,aldps-enable; realtek,clkout-disable; }; }; }; Regards

我如何知道时钟是否已经启用？ 如果我需要初始化 ADC 和 QDC，并且它们都使用 XBARA，则“CLOCK_EnableClock(kCLOCK_Xbar1);”被调用两次。 kCLOCK_Xbar1 启用两次会有问题吗？在我尝试启用该模块之前，是否有一个函数可以用来了解该模块是否已经启用？ 回复：我如何知道时钟是否已启用？ RT1042

S32k144 CSEC エラー状態 こんにちは、チーム: AN5401 から、 CSEC コマンドの実行中に ny エラーが発生した場合 に"Error Bits" フィールドにエラーが報告されることを知っています が、チップへの影響を確認したいのですが。 たとえば、カウンター値を増やさずにキーを更新すると、エラービットは「CSEC_KEY_UPDATE_ERROR」になり、キーは使用できなくなりますか、それとも何であり、フラッシュモジュールの使用に影響しますか? よろしくお願いいたします COR Re:S32k144 CSECエラー状態 他のエラービットも同じですか?CSEC のエラーはフラッシュモジュールやオリジナル KES に影響しますか?