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Vector Packet Processing(VPP) IPSEC Implementation in LSDK 20.12 The VPP platform is an extensible framework that provides out-of-the-box production quality switch/router functionality. This document introduces Vector Packet Processing(VPP), creating VPP IPsec configuration scripts, building VPP v20.05 in LSDK 20.12, executing VPP IPsec on LS1046ARDB and LS2088ARDB platforms
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How to compile and execute custom applications on a Layerscape board This topic explains steps to compile and execute Hello World program (in C) on a Layerscape board. Similarly, you can execute other custom applications on your board. Create a Hello World program in C.  Copy this file (.c) on a Ubuntu machine (using WinSCP). Run the following command to convert the .c file into a binary file. $ aarch64-linux-gnu-gcc <.c file> -o For example: $ aarch64-linux-gnu-gcc Hello_World.c -o Hello_World Note: You can use this command in the same directory in which .c file is present or provide path of this file. Connect to the board console on which you want to execute the custom application via terminal and boot the board with LITB. Note: It is suggested to boot the board with Tiny Linux for executing custom application.  => tftp 0xa0000000 lsdk2004_yocto_tiny_LS_arm64.itb Using e1000#0 device TFTP from server 192.168.3.1; our IP address is 192.168.3.142 Filename 'lsdk2004_yocto_tiny_LS_arm64.itb'. Load address: 0xa0000000 Loading: ################################################################# ################################################################# ##################################################### 4.3 MiB/s done Bytes transferred = 37030212 (2350944 hex) => bootm 0xa0000000#lx2160ardb ## Loading kernel from FIT Image at a0000000 ... Using 'lx2160ardb' configuration Trying 'kernel' kernel subimage Description: ARM64 Kernel Created: 2021-02-03 6:01:29 UTC Type: Kernel Image Compression: gzip compressed Data Start: 0xa00000d0 Data Size: 14086432 Bytes = 13.4 MiB When Tiny Linux boots, enable Ethernet to download the HelloWorld program on the board. To see the available networks. root@TinyLinux:~# ifconfig -a eth0 Link encap:Ethernet HWaddr 68:05:ca:2b:2c:ca BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:114 Memory:90460c0000-90460e0000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) sit0 Link encap:UNSPEC HWaddr 00-00-00-00-31-00-6C-6F-00-00-00-00-00-00-00-00 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Enable the Ethernet connection. # ifconfig netmask up For example: root@TinyLinux:~# ifconfig eth0 192.168.3.121 netmask 255.255.255.0 up Set the gateway IP and ping the server to test the connection. # route add default gw # ping For example: root@TinyLinux:~# route add default gw 192.168.3.1 root@TinyLinux:~# ping 192.168.3.1 PING 192.168.3.1 (192.168.3.1): 56 data bytes 64 bytes from 192.168.3.1: seq=0 ttl=64 time=0.479 ms 64 bytes from 192.168.3.1: seq=1 ttl=64 time=0.204 ms Download the HelloWorld binary file on your board. For example: root@TinyLinux:~# scp [email protected]:/tftpboot/LX2160ARDB/HelloWorld . Execute the HelloWorld application. root@TinyLinux:~# ./HelloWorld Hello, World!
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UART Emulation Using the FTM or TPM Introduction Even with the prevalence of universal asynchronous receiver/transmitter (UART) peripherals on microcontrollers (MCUs), bit banged UART algorithms are still used.  The reasons for this vary from application to application.  Sometimes it is simply because more UARTs are needed than the selected device provides.  Maybe application or layout restrictions require certain pins to be used for the UART functions but the device does not route UART pins to the required package pins.  Maybe the application requires a non-standard or proprietary UART scheme. Whatever the reason, there are applications where a bit banged UART is used and is typically a pure software implementation (a timer is used and the MCU core controls a GPIO pin directly).  A better alternative may be to use Flextimer (FTM) or Timer/PWM Module (TPM) to take advantage of the features of these peripherals and possibly offload the CPU.  This document will explain and provide a sample application of how to emulate a UART using the FTM or TPM peripheral.  A Kinetis SDK example (for the TWR-K22F120M and FRDM-K22F platforms) and a baremetal legacy code example (for the FRDM-KL26Z) are provided here. UART protocol Before creating an application to emulate a UART, the UART protocol and encoding must be understood. The UART protocol is an asynchronous protocol that typically includes a start bit, payload (of 7-10 data bits), and a stop bit but does allow for many variations on the number of stop bits and what/how to transfer the data.  For this document and application example, the focus will be UART transmission that follows 1 start bit, 8 data bits, 1 stop bit, no parity, and no flow control.  The data will be transmitted least significant bit (LSB) first.  The following image is a block diagram of this transmission. However, this doesn't specify what the transmission looks like electrically. The figure below shows a screenshot of an oscilloscope capture of a UART transmission.  The data transmitted is 0x55 or a "U" in the ASCII representation. Notice that the transmission line is initially a logic high, and then transitions low to signal the start of the transmission.  The transmission line must stay low for one bit width for the receiver to detect it.  Then there are 8 data bits, followed by 1 stop bit.  In the case shown above, the data bits are 0x55 or 0b0101_0101.  Remember that the transmissions are sent LSB first, so the screenshot shows 1-0-1-0-1-0-1-0.  The last transition high marks the beginning of the stop bit and the line remains in that state until the start of the next transmission.  The receiver, being asynchronous, does not require any type of identifying transition to mark the end of the stop bit. FTM/TPM configuration The first question many may ask when beginning a project like this is "How do I configure the FTM/TPM when emulating a UART".  The answer to this depends on the aspect of this problem you are trying to solve.  Transmitting and receiving characters require two different configurations.  Transmission requires a configuration that manipulates the output pin at specific points in time.  Receiving characters requires a configuration that samples the receive pin and measures the time between pin transitions.  The FTM and TPM have the modes listed in the following table: The FTM and TPM have four different modes that manipulate an output:  Output compare (no pulse), Output compare (with pulse), Edge-aligned PWM, and Center-aligned PWM.  Neither PWM mode is ideal for the requirements of the application.  This is because the PWM modes are designed to produce a continuous waveform and are always going to return to the initialized state once during the cycle of the waveform.  However, the UART protocol may have continuous 1's or 0's in the data without pin transitions between them. The output compare mode (high-true or low-true pulse modes) is designed to only manipulate the pin once, and only produces pulses that are one FTM/TPM clock cycle in duration.  So this is obviously not desirable for the application.  The output compare mode (Set/Clear/Toggle on match) is promising.  This mode manipulates the output pin every cycle.  There are three different options:  clear output on match, set output on match, and toggle output on match.  Neither "clear output on match" nor "set output on match" are ideal as either would require configuration changes during the transmission of a character.  The "toggle output on match", however, can be used and is the selected configuration mode for this sample application. To receive characters, there is only one mode that is intuitive:  "the input capture mode".  This mode records the timer count value on an edge transition of the selected input pin.  Similar to the output compare mode chosen for the transmit functionality, the input capture mode has three sub-modes:  capture on rising edge, capture of falling edge, and capture on either edge.  It is clear from the descriptions that capture on either edge should be selected. Transmit encoding The selection of the FTM/TPM mode is moderately intuitive, but using this mode to emulate a UART transmission is not.  There are two issues that make this a little tricky. 1) The output pin is initialized low. However, the UART protocol needs the pin to begin in a logical high state. 2) The pin transitions on every cycle provided the channel value is less than the value of the MOD register. Due to continuous strings of 1's or 0's, it is necessary to have periods where the pin does not transition. Both of these points have workarounds. Output pin initialization For the first issue, the channel interrupt is first enabled and the channel value register is loaded with a value much less than the value in the MOD register.  Then in the channel interrupt service routine, the pin is sampled to ensure that it is in the logic high state and the channel interrupt is disabled (and will not be re-enabled throughout the life of the application).  The code for this interrupt service routine is as follows. Output pin control For the second issue, a method of not transitioning the pin value while allowing the timer to continue counting normally is necessary.  The Output Compare mode uses the channel value register to determine when the pin transition occurs.  If a value greater than MOD is written to the channel value register, the channel value will never match the count register and thus, a pin transition will never occur.  So, when a series of continuous 1's or 0's need to be transmitted, a value greater than the value in the MOD register can be written to the channel value register to keep the output pin in its current state. However, when a value greater than MOD is written to the channel value register, no channel match will occur (which means channel interrupts will not occur).  So the timer overflow interrupt must be used to continue writing values.  This requires the updates to be output pin to be planned ahead of time and makes the transmission algorithm a little tricky.  The following diagram displays when which values should be written to the channel value register at which points in time to generate the appropriate pulses. Writing a function to translate a number into the appropriate series of MOD/2 and MOD+1 values can be a little tricky. To do this, we must first notice that MOD/2 needs to be written when changes on the transmission pin are need and MOD+1 needs to be written when pin transmissions are not desired.   So, what logical function can we use to determine when a change has happened?  XOR is the correct answer.  So what two values need to be XOR'd together?  One value is obviously the value that we want to send.  But what is the second value?  It turns out that the second value is a shifted version of the value that we want to send.  Specifically, the second value is the desired value to send shifted to the left by one.  (You can think of it as sort of a "future" value of the desired value).  The following pictures show how to determine the queue to use for the transmission. Receive decoding The receive functionality has an advantage over the transmit functions in that it is possible to use DMA for the reception of characters.  This is because the receive function takes advantage of the input capture functionality of the FTM / TPM and therefore can use the channel match interrupt.  The example application provided with this document implements a DMA method and a non-DMA method for reception. First, the non-DMA method will be discussed. Before discussing the specifics of gathering the input pulse widths, some details of the receive pin need to be discussed. Detecting the start bit The receive pin needs to be able to determine when the start of the packet transmission begins.  To do this, the receive pin is configured as an FTM / TPM pin. At the same time, the GPIO interrupt functionality is configured on the same pin for a falling edge interrupt.  The GPIO interrupt capabilities are enabled in any digital mode, so the GPIO interrupt will still be able to be routed to the Nested Vector Interrupt Controller (NVIC).  The pin interrupt is used to start the FTM / TPM clock when a new character reception begins. In the GPIO interrupt for this pin, the FTM / TPM counter register is reset and the clock to the FTM / TPM is turned on.  The code for the GPIO interrupt service routine is shown below.  Receiving characters without DMA Now, when receiving characters and not using DMA, the first thing to understand is that the Interrupt Service Routine (ISR) will be used and it will mainly be used to record the captured count values.  The interrupt service routine also tracks the current receive character length and resets the counter register.  This is so that the values in the receive queue reflect the time since the last pin transition.  The interrupt function for the non-DMA application is shown below. Notice that the first two actions in the ISR are resetting the count register, and clearing the channel event interrupt flag.  Then the channel value is stored in the receive pulse width array (this is simply an array that holds the receive pulse widths of the current character being received).  Next, recvQueueLength, the variable which holds the current length of the character being received, is updated to reflect the latest character length.  The next step is to determine if the full character has been received.  This is determined by comparing recvQueueLength to the RECV_QUEUE_THRESH, which is the threshold as determined by multiplying the number of expected bits by the expected bit width plus another bit width (for the start bit).  If the recvQueueLength is greater than the RECV_QUEUE_THRESH, then a semaphore is set, recvdChar, to indicate that a full character has been received.  The FTM / TPM clock is turned off, and the pin interrupt functionality of the receive pin is enabled.  The final step in the interrupt routine is to increment the receive queue index, recvQueueIndex.  This variable points to the current entry in the receive queue array. Using DMA to receive characters When using DMA, the receive FTM / TPM interrupt is much different. The interrupt routine simply needs to clear the channel interrupt flag, stop the FTM / TPM timer, disable the DMA channel, and set the received character semaphore.  The character is then decoded outside of the interrupt routine.  The interrupt function when using DMA is shown below: Decoding the received pulse widths Once the array of pulse widths has been populated, the received character needs to be translated into a single number.  This varies slightly when using DMA and when not using DMA. However, the basic principle is the same.  The number of bits in a single entry is determined by dividing by the expected bit width and this is translated into a temporary array that contains 1's and 0's, and then that is used to shift in the appropriate number of 1's and 0's into the returned char variable.  A temporary array is needed because the values are shifted into the UART LSB first, so the bit must be physically flipped from the first entry to the last.  There is no logical operation that will do this automatically. The algorithm to perform this translation is shown below.  In this algorithm, note that recvPulseWidth is the array that contains the raw count value of the pulse width.  The array tempRxChar holds the decoded character in reverse order and rxChar is a char variable that holds the received character. Conclusion This document provides an overview of the UART protocol and describes a method for creating a software UART using the timing features of the FTM or TPM peripheral.  This method allows for accurate timing and while not relying entirely on the CPU and the latency associated with the interrupt and the GPIO pins.  The receive function is open to further optimization by using DMA, which can provide further unloading of the CPU. Kinetis Hardware Support Kinetis K Series MCUs Kinetis L Series MCUs Kinetis V Series MCUs
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MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 此MQX演示重新使用标准 MQX web_hvac 演示,使用 GT202 Wi-Fi 模块,设置为 SoftAP 模式。此示例展示了 MQX RTCS、DHCP 服务器和 Web 服务器在Kinetis MCU中运行,并采用 Atheros 驱动程序。客户端将能够连接到软接入点 (SoftAP),获取 IP 地址,然后使用 Web 浏览器查看 web_hvac 网页。用户指南包含在 ZIP 文件中。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 此MQX演示重新使用标准 MQX web_hvac 演示,使用 GT202 Wi-Fi 模块,设置为 SoftAP 模式。此示例展示了 MQX RTCS、DHCP 服务器和 Web 服务器在Kinetis MCU中运行,并采用 Atheros 驱动程序。客户端将能够连接到软接入点 (SoftAP),获取 IP 地址,然后使用 Web 浏览器查看 web_hvac 网页。用户指南包含在 ZIP 文件中。 通信基础设施 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 我遇到了同样的问题:这取决于您安装哪个“补丁”......您没有带有 FRDMK22 补丁的文件(FSLMQX4.1_PATCH_GT202_3.0.2CS.exe 和 Setup_MQX4.1_GT202_3.0.2CS.exe)但我有这个带有 QCA4004.MQX.exe 补丁的文件)。 如果有人能分享所需的确切补丁(名称和链接)以及应用它们的顺序,那就太完美了! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 对我来说,目前还没有,即使经过了很多小时(几天......) 该演示与 IAR 和 FRDM K22 完美兼容,甚至与 .bin 兼容重建(throughput_demo)。 但之后,FRDM K64、MQX4.1 和 CW10.6 就没有任何进展了…… 如果有人有更好的结果,请分享:smileywink: 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 大家好, 你们中有人成功地使用带有 FRDM-K64F 板和 Kinetis Studio 环境的 GT-202 使这个示例工作吗? 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好,克里夫 我想在我的项目中包含一个 GT202 模块,但是遇到了问题。我正在使用 FRDMK64F 板和 MQX 4.1。我使用开发环境Kinetis Design Studio 3.0。您的移民运气好吗?你能在这个过程中帮助我吗? 谢谢克里夫 凯文·卡塞尔 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,托马斯 您是否按照用户指南中的步骤添加了 Qualcomm Wi-Fi 模块所需的 MQX 补丁? 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,克里夫, 你自己有取得什么进步吗?我发现自己也处于类似的境地。令人沮丧的是,直接与 Kinetis 开发板接口、运行 Freescale 操作系统的开发板尚未移植到 Kinetis Development Studio 中使用。 Larry 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,chinniwhites, 抱歉,我不清楚在哪里可以找到 web_hvac。web_hvac 演示是 MQX v4.1.1 及更早版本中包含的标准 MQX 演示。它位于 \demo\web_hvac。按照安装 GT202 PDK 的说明进行操作时,一步是安装 MQX v4.1.0。完成该步骤后,web_hvac demo 将包含在安装中。 当您安装 GT202 PDK 时,它不会修改 web_hvac 演示。它仍然是MQX安装中提供的原始演示。之前我解释过,此页面上的 SoftAP 演示基于 web_hvac 演示,然后进行了修改以使用 GT202 模块和 SoftAP 功能。如果您想查看 GT202 的更新 web_hvac,您可以使用此 SoftAP 演示作为示例。 由于此页面位于 DemoLab 社区空间,因此 MQX 支持团队不会注意到此处发布的评论。如果您对此 SoftAP 演示有任何疑问,请告诉我。如果您有其他有关 MQX 的问题,最好在https://community.freescale.com/community/mqx中创建新的讨论 谢谢! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,克里夫, 看起来您指的是KSDK v1.1.0<>以下。Kinetis 软件开发套件 (KSDK) 是一个驱动程序、堆栈和 RTOS(如 MQX)库。Kinetis Design Studio (KDS)<> 是我们用于构建 Kinetis 应用程序的工具链。下面引用的示例位置是 KSDK 的一部分。 web_hvac 示例来自 MQX 与 KSDK 集成之前的 MQX 安装。目前是 MQX v4.1.1 或更早版本。当您按照 GT202 PDK 的安装说明进行操作时,您会发现 web_hvac 演示安装在 \Freescale_MQX_4_1\demo\web_hvac。我相信有计划将 web_hvac 演示移植到 KSDK 的 MQX,但它并不包含在最新的 KSDK v1.1.0 中。 然而,您应该知道GT202驱动程序尚未移植到KSDK。GT202 驱动程序和 PDK 是使用 MQX v4.1.0 开发的。如果您选择将 GT202 与 KSDK 一起使用,则需要移植驱动程序并使用 KSDK SPI 和 GPIO 外设驱动程序。或者,如果您使用 MQX v4.1,GT202 驱动程序已经为您移植。 谢谢! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,克里夫, 是的,这个 SoftAP 演示项目使用 IAR,因为 GT202 MQX 示例项目使用 IAR。我不知道其他工具链的 GT202 MQX 示例项目。 但如您所知,MQX 包含一个用于 KDS 的 FRDM-K64F BSP 项目。您可以修改该项目并将 Atheros 驱动程序添加到 GT202 的 BSP。您可以使用 FRDM-K22F 的 GT202 示例 BSP 作为参考。为了集成驱动程序,还需要对提供的 BSP 文件进行一些更改。与 MQX 安装中的原始 FRDM-K22F BSP 文件相比,您可以找到对 GT202 FRDM-K22F BSP 文件所做的更改。然后在您的 K64 BSP 中进行类似的更改。 SoftAP 应用程序示例基于 MQX 中包含的 web_hvac 演示。该演示还包含针对 FRDM-K64F 的 KDS 项目。因此,您的应用程序可以从该演示项目开始,然后从 SoftAP 演示中复制源文件。使用 BSP 中的 GT202 驱动程序,您可以构建此 SoftAP 应用程序。 希望有帮助。谢谢 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,chinniwhites, 在 MQX 中,您可以在 BSP 中启用多个 ENET 设备。但我不知道有哪个例子可以证明 GT202 和有线以太网的兼容性。 我建议您在 MQX Space 中发布一个新问题,以便 MQX 支持人员能够了解并做出回应。 https://community.freescale.com/community/mqx 谢谢! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 这确实很合适。我希望尽快在 IoTT 上线它!iot.freescale.com
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Landzo:スパイダーマンショーとソリューションブリーフィング <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> LandzoのLan Zhouによる発表 深センのDwF Kinetis MCUs Based on ARM® Technology (2015年1月27日)で発表 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> LandzoのLan Zhouによる発表 深センのDwF Kinetis MCUs Based on ARM® Technology (2015年1月27日)で発表
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RD56F801XACIM: Design of an ACIM Vector Control Drive Reference Design using the 56F801X Overview Features General: General Benefits: Performance: Communications: Visual Interface: Block Diagram Board Design Resources Overview This drive application allows vector control of an AC Induction Motor (ACIM) running in a closed-speed loop without a speed/position sensor at a low cost and serves as an example of AC induction vector control drive design using an NXP ®  56F8013 with Processor Expert ®  software support. ACIM is ideal for appliance and industrial applications This design uses sensorless FOC to control an ACIM using the 56F8013 device, which can accommodate the sensorless FOC algorithm The motor control system is flexible enough to implement complex motion protocols while it drives a variable load. The system illustrates the features of the 56F8013 in motor control Features General: The motor control algorithm employs Stator-Flux-Oriented Control (SFOC) Power stage switches are controlled by Space Vector Pulse Width Modulation (SVPWM) No position information devices or stator flux measurement are used, a sensorless speed method is employed The motor is capable of forward and reverse rotation and has a speed range from 50rpm to 3000rpm The user controls motion profiles, rotation direction, and speed. The RS-232 communication supports further R&D by enabling the easy tuning of control parameters The motor drive system is designed to create minimal acoustic noise Active power factor correction which reduces the negative effects of the load on the power grid in conducted noise and imaginary power Design is low cost General Benefits: Improved End System Performance Energy savings Quieter operation Improved EMI performance System Cost savings Enhanced Reliability Performance: Input voltage: 85 ~265VAC Input frequency: 45 ~65HZ Rating bus voltage: 350V Rating output power: 500W Switch frequency of PFC switch: 100KHZ Switch frequency of inverter: 10KHZ Power factor: >95% Efficiency: >90% Communications: RS232 port for communication with optoisolation Visual Interface: Multi-segment LED indicators Block Diagram Board Design Resources Legacy Designs
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RD56F8300LCSM: Low-Cost Soft Modem Reference Design using the NXP DSC Overview Features Block Diagram Board Design Resources Overview This reference design shows the simplicity of a soft modem design, how few resources of the processor it takes, and how well it performs on USA average lines. This design omits the standard telecommunications Codec, instead of using PWM for output and ADC for input. Since both peripherals are readily available on one 56F8300/100 series device, along with more processing power than required from the single core, the design is a true one-chip, one-core system that includes telecommunications ability with room for even more system functionality. Ideal for advanced motion control, home appliances, medical monitoring, fire and security systems, power management, smart relays, and POS terminals. Features Hybrid architecture facilitates implementation of V.21 and V.22bis modem, control, and signal processing functions in one chip Consumes only 7.5 MIPS for the modem function - Only 15K words of Flash for the complete modem application and test harness High-performance, secured Flash memory eliminates the need for external storage devices Extended temperature range allows for operation of non-volatile memory in harsh environments Flash memory emulation of EEPROM eliminates the need for external non-volatile memory 32-bit performance with 16-bit code density On-chip voltage regulator and power management reduces overall system cost Off-chip memory expansion capabilities allow for glueless interfacing with the additional memory of external devices, without sacrificing performance Boots directly from Flash, providing additional application flexibility High-performance PWM with programmable fault capability simplifies design and promotes compliance with safety regulations PWM and ADC modules are tightly coupled to reduce processing overhead; only one of each is used by the modem General purpose input/output (GPIO) pins support application-specific needs Simple in-application Flash memory programming via Enhanced OnCE or serial communication Block Diagram Board Design Resources Legacy Designs Re: RD56F8300LCSM: Low-Cost Soft Modem Reference Design using the NXP DSC When purchasing ducting material online, it's essential to verify the specifications to ensure they meet your project needs. Look for detailed product descriptions, including dimensions, materials, and temperature ratings.
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RD56F80PMSVC: Sensorless PM Motor Drive for H-axis Washer Reference Design Using MC56F80xx Overview Features Block Diagram Board Design Resources Overview This reference design is for a sensorless permanent magnet (PM) motor drive single-chip solution based on the NXP® DSC56F80XX digital signal controller (DSC). An electronically controlled three phase PM motor provides a unique feature set with the higher efficiency and power density This application presents a motor control technique of PM motor without a need to use a rotor position transducer This technique particularly targets horizontal axis (H-axis) washing machine with belt drive in fractional horsepower range A designer reference manual provides a detailed description of the application, including the design of the hardware and the software Features Designed to fit into consumer and industrial applications MC56F80XX digital signal controller 3-phase AC/BLDC High Voltage Power Stage Board 1-phase line input 110/230VAC 50/60Hz Apliance PM motor Initial rotor position detection Full torque at motor start-up Field weakening Application based on C-callable library functions (GFLIB, GDFLIB, MCLIB, ACLIB) Current control loop Speed control loop with Field weakening Flash: ~ 6KB, RAM ~ 1.5KB FreeMASTER based control pages Block Diagram Board Design Resources Legacy Designs
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RDDSCSHSSR: Sensorless High-Speed SR Motor Drive for Vacuum Cleaners Reference Design using an MC56F8013 Overview Features Block Diagram Design Resources Overview The Sensorless High-Speed SR Motor Control Reference Design based on the NXP® low-cost MC56F8013 digital signal controller (DSC) deals with a 2-phase switch reluctance (SR) motor sensorless drive for vacuum cleaners and other air movement applications. The application is a speed-open loop SR drive without any position or speed sensor needs Uses a sensorless control method based on current peak detection and a patented start-up algorithm (Patent No. US6448736 B1) The control technique allows the SR motor more than 100 000 RPM The application is primarily for vacuum cleaners, although it can be used for any application with a high-speed drive (50 000 RPM) Features High-speed 2-phase SR motor sensorless control based on a current peak detection Designed for vacuum cleaner applications Capable of running SR motors at more than 100.000 RPM (tested with SR motor designed for 60 000 RPM) Single direction rotation enabled by asymmetric of 2-phase SR motor Speed open loop Start-up from any position using alignment and patented algorithm (Patent No. US6448736 B1) Start-up time and maximum speed depends on SR motor parameters Manual interface and FreeMASTER control page for monitoring, control and tuning Block Diagram Design Resources Legacy Designs
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K-70およびK-24コネクティビティ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
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Unified-Threat Management (UTM) Overview Use Cases Block Diagram Products Overview NXP has a broad portfolio of software and processors for security. Regarding software, NXP has complete Turnkey solutions or optimized software components; Regarding processors, NXP has scalable solution from 1xA53 to 16xA72. LS1043A is a good candidate for Low-end UTM, it comes with the option for 5 Gbps single pass cryptographic offload and 10 Gbps data path parse, classification and distribution which helps in delivering flows to cores for additional security processing. Use Cases Network security is a large, growing market. UTM Key System Features are as following: Enterprise FW features Antivirus Content filtering Spam filtering Block Diagram Products Category MPU Product URL Layerscape LS1043A Reference Design Board  Product Description The LS1043A reference design board (RDB) is a computing, evaluation, and development platform that supports the Layerscape LS1043A architecture processor. Category Wi-Fi Product URL 88W8997: 2.4/5 GHz Dual-Band 2x2 Wi-Fi® 5 (802.11ac) + Bluetooth® 5 Solution  Product Description The 88W8997 is the industry’s first 28nm, 802.11ac wave-2, 2x2 MU-MIMO combo solution with full support for Bluetooth 5. Category Temperature Sensor Product URL SA56004X: SMBus-Compatible, 8-Pin, Remote/Local Digital Temperature Sensor  Product Description The NXP Semiconductors SA56004X is an SMBus compatible, 11-bit remote/local digital temperature sensor with over-temperature alarms. Category Power Management Product URL MC34VR500: Multi-Output DC/DC Regulator  Product Description The NXP® MC34VR500 power management solution for network processor systems is a high-efficiency, quad buck regulator with up to 4.5 A output and five user-programmable LDOs. Category RTC Product URL PCF85063TP: Tiny Real-Time Clock/calendar  Product Description The PCF85063TP is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption. An offset register allows fine-tuning of the clock. Category Transceiver Product URL 1 NTS0101: Dual supply translating transceiver; open drain; auto direction sensing  Product Description 1 The NTS0101 is a 1-bit, dual supply translating transceiver with auto direction sensing, that enables bidirectional voltage level translation. Product URL 2 NTS0302JK: 2-bit dual supply translating transceiver; open drain; auto direction sensing  Product Description 2 The NTS0302 is a 2-bit, dual supply translating transceiver family with auto direction sensing, that enables bidirectional voltage level translation. Product URL 3 NTS0304E: 4-bit dual supply translating transceiver; open drain; auto-direction sensing  Product Description 3 The NTS0304E is a 4-bit, dual supply translating transceiver family with auto-direction sensing, that enables bidirectional voltage level translation. Block Diagrams Communications Infrastructure
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当前APK.apk <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Android 传感器融合 APK <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Android 传感器融合 APK 传感器融合
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3-Phase Hall Sensor PMSM Driver for E-Bike and Sensorless Solution for HV Motor-Based on KE02 Description Block Diagram Products Related Documentation Training Related Demos from Communities Description A bicycle with an integrated electric motor and a rechargeable battery, making it an eco-friendly, zero-emission vehicle ideal for smart cities. An important feature of an E-Bike is that it must be reliable and can be used for long periods. Block Diagram Products Category Name 1: Microcontroller Product 1 URL 1 https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/ke-series-cortex-m4-m0-plus/kinetis-ke02-20-mhz-entry-level-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KE02 Product 1 Description 1 The Kinetis KE02 includes a powerful array of analog, communication and timing and control peripherals with specific flash memory size and the pin count. The K02 acts as a low-power, high-robustness, and cost-effective microcontroller with one 6-channel FlexTimer/PWM and two 2-channel FlexTimer/PWM. Product 2 URL 1 Arm® Cortex®-M4|Kinetis® K64 120 MHz 32-bit MCUs | NXP  Product 2 Description 1 Kinetis ®  K64-120 MHz, 256 KB SRAM Microcontrollers (MCUs) based on Arm ®  Cortex ® -M4 Core Category Name 2: Gate driver Product 1 URL 1 https://www.nxp.com/products/power-management/motor-and-solenoid-drivers/bldc-h-bridge-stepper/3-phase-brushless-motor-pre-driver:GD3000 Product 1 Description 1 The GD3000 is a gate driver IC for three-phase motor drive applications providing three half-bridge drivers, each capable of driving two N-channel MOSFETs. Category Name 3: LED Driver Product URL 1 https://www.nxp.com/products/power-management/lighting-driver-and-controller-ics/ic-led-controllers/16-channel-fm-plus-ic-bus-57-ma-20-v-constant-current-led-driver:PCA9955BTW Product Description 1 The PCA9955B is an I2C-bus controlled 16-channel constant current LED driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber (RGBA) LEDs in amusement products. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 31.25 kHz with a duty cycle that is adjustable from 0 % to 100 % to allow the LED to be set to a specific brightness value. Category Name 4: Logic USB Type-C Configuration Channel Product URL 1 https://www.nxp.com/products/interfaces/usb-interfaces/usb-type-c-true-plugn-play/usb-pd-phy-and-cc-logic/cc-logic-for-usb-type-c-applications:PTN5150 Product Description 1 PTN5150 is a small thin low power CC Logic chip supporting the USB Type-C connector application with Configuration Channel (CC) control logic detection and indication functions. The PTN5150 enables USB Type-C connector to be used in both host and device ends of the Type-C cable Category Name 5: Current-Limited Power Switch Product URL 1 https://www.nxp.com/products/power-management/load-switches/usb-pd-and-type-c-current-limited-power-switch:NX5P3290UK Product Description 1 The NX5P3290 includes under-voltage lockout, over-temperature protection, and reverse current protection circuits to automatically isolate the switch terminals when a fault condition occurs. Category Name 6: Secure Product 1 URL 1 A71CH | Plug and Trust for IoT | NXP  Product Description 1 Plug and Trust - The fast, easy way to deploy secure IoT connections Category Name 7: NFC Product 1 URL 1 PN5180 | Full NFC Forum-compliant frontend IC | NXP  Product Description 1 Full NFC Forum-compliant frontend IC Category Name 8: GPIO Expander Product 1 URL 1 PCAL6534 | Level translating GPIO Expander | NXP  Product Description 1 Ultra-low-voltage, level translating, 34-bit I2C-bus/SMBus I/O expander   Category Name 8: NFC smartcard Product 1 URL 1 https://www.nxp.com/products/rfid-nfc/mifare-hf/mifare-desfire/mifare-desfire-ev2:MIFARE_DESFIRE_EV2_2K_8K Product Description 1 Secure, contactless multi-application IC with an enhanced feature set for Smart City applications Related Documentation Document URL Title https://www.nxp.com/docs/en/application-note/AN10439.pdf Wafer-level chip-scale package https://www.nxp.com/docs/en/application-note/AN5322.pdf AN5322, TPMS wheel location introduction and main concepts Training Training URL https://community.nxp.com/docs/DOC-341509 Related Demos from Communities URL Kinetis Microcontrollers  MCUXpresso SDK  MCUXpresso Software and Tools  UAV Speed Control with Kinetis KV5x Cortex-M7 MCU and GD3000 Motor Pre-Drivers    Block Diagrams Smart City
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RT10xx optimization for LCD performance.pdf The attached document describes how to optimize LCD display performance on RT10xx platform. The content include RT10xx configuration and Emwin setting with LCD parameters. Products Product Category NXP Part Number URL MCU i.MX RT1060 i.MX RT1060 MCU/Applications Crossover MCU | Arm® Cortex®-M7, 1MB SRAM | NXP  MCU i.MX RT1050 i.MX RT1050 MCU/Applications Crossover MCU| Arm® Cortex-M7, 512KB SRAM | NXP  SDK Software Software Development Kit https://mcuxpresso.nxp.com/en/select    Tools NXP Development Board URL MIMXRT1060-EVK i.MX RT1060 Evaluation Kit | NXP  MIMXRT1050-EVK i.MX RT1050 Evaluation Kit | NXP  Was this helpful to you?
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HOWTO: Create An ISP Project From Example in S32DS for S32 Platform S32DS contains many example projects from which you can learn how S32DS can be used with the help of the Vision SDK to develop vision applications. The example projects contain generated and hand-written code, which utilize the Vision SDK to demonstrate a workflow using S32DS. In this document, the procedure for creating a project from one of the provided ISP examples through to execution on the EVB is detailed. This project was run using S32DS version 3.2 and VSDK version 1.5.0.   1) Launch S32DS 2) Select 'File -> New -> S32DS Project from Example' 3) Select 'isp_h264dec_single_stream' project    In this particular project, the ISP graph diagram is included. If you wish to view it, go to the Project Explorer panel and expand 'isp_h264dec_single_stream_graph'. Then double click on 'ISP data flow : h264dec_single_stream'. The ISP graph diagram will appear in the editor panel. 4) If not in the C/C++ Perspective, switch over by clicking on the icon showed below (Hovering over the correct icon should display 'C/C++'). The current perspective is displayed on the top bar. 5) Select isp_h264dec_single_stream: A53 in the Project Explorer panel 6) Build project for A53  7) Start a debug session using method as described in HOWTO Create A53 Linux Project in S32DS for Vision, beginning at step 9. 😎 Click Resume  The program takes the input H264 encoded image img_1280x960.h264 located in the /home/root/vsdk/data/common folder on the Linux BSP and outputs it on the display The output image should look like below. New Project Wizard - Project Management and Settings SDKs
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视频 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 使用 TAD 工具
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RT1060 AN12781 Lockアプリケーションを実行 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> これは、Embedded Wizzard GUIアプリケーションと推論エンジンとしてのニューラルネットワークモデルを実行するための i.MX RT1060評価キット機能のデモを目的とした簡単なビデオです。 (マイビデオで視聴) インダストリアル スマートシティ スマートホーム
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Example_MPC5777C-External_SRAM-test-S32DS.Power.2017.R1 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/ 全般
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BSP Security Maintenance NXP Webinar: April 23, 2020
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S32DSやMatlab、Simulinkなどのさまざまな開発環境からFreeMASTER UIを使用して組み込みアプリケーションを強化するためのヒント <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
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