Currently, there are some issues with the PTN3460I prototype. I am unable to identify this chip through the IIC method. Could it be that there are problems with the startup method or process? The LCD screen is selected as LVDS single bus, 24 bpp, VESA data packing. The dual-channel in CFG1 has been changed to single-channel. Also, the HPDRX pin on the chip, which is directly connected to the EDP-HPD pin on the CPU (after level conversion), does there need to be any other logic inversion?
Hello Zhaozhiling
Good day!
I have 3 observations that I would like to discuss with you
1.-
Is the PTN3460I working as a slave or a master?
2.-
Could you try removing the RST_N capacitor? I want to verify that the charging time doesn't interfere with the device startup and cause a mid-process reset.
3.- The investment in HPDRX isn't necessary, but could you graph it? I want to see the signal in HPDRX at startup.
Given that the HPDRX pin is internally connected to GND through an integrated pull-down resistor (> 100 k), the DP source will see HPDRX pin as LOW indicating that the DisplayPort receiver is not ready when the device is not powered. This helps avoid raising false events to the source. After power-up, PTN3460I continues to drive HPDRX pin LOW until completion of internal initialization. After this, PTN3460I generates HPD signal to notify DP source and take corrective action(s).
I will be waiting for your response
Have a great day and best of luck.