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codewarrior v8.8 + codewarrior tap の問題 MPC8323 フラッシュをプログラムするために使用しました:codewarrior v8.8 + codewarrior tap(パッチ 8.8.6 がインストール済み)、問題はありません。 しかし最近、新しいコードウォリアータップを購入しました。フラッシュをCANできません。ついに新しいのは rev H で、古いのは rev G だと思います。 MPC8323 をプログラムする方法、codewarrior tap rev H で codewarrior v8.8 を使用する方法を教えてください。 ありがとうございます。 Re: codewarrior v8.8 + codewarrior tap issue 親愛なる@zbxggs様、 最後の質問について社内チームアプリに問い合わせたところ、バージョン H とバージョン G は同じなので心配する必要はないとの回答でした。SO、MPC をフラッシュするために実行する必要がある手順は、どちらのバージョンでも同じです。 保証手続きを開始するには、CW TAP を購入した人にいただくか、発生しているエラー ログをに確認してください。 BR LFGP Re: codewarrior v8.8 + codewarrior tap issue こんにちは。CodeWarrior Tap H バージョンを使用したい場合、バージョン 8.8 を置き換えるにはどのバージョンの CodeWarrior を使用すればよいですか? Re: codewarrior v8.8 + codewarrior tap issue 親愛なる@zbxggs Windows 7 を使っていますか? 使わなければなりません。 問題の手がかりを得るために CCS ログを共有してください。また、新しい CW TAP の写真も共有してください (両側でお願いします)
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S32K312_RTD400_SPD104_IAR 私が使用しているチップはS32K312+RTD400+SPD104です プロジェクトを iar にインポートして実行しようとしましたが、コンパイル中に未定義のセクションがいくつか報告されました。icfファイルとstartup_cm7.sを変更してみましたが、コンパイルは可能でしたが、ログをデバッグすると依然としてエラーが報告されました。 添付ファイルは、これまでに変更した icf ファイルです。SRAM の割り当てにもいくつか変更を加えました。int_sram_shareable_size を 0 に、int_sram_size を 64 KB に設定しました。何か問題があるかどうかは分かりません。 また、起動ファイルやその他のファイルも同時に変更する必要がありますか? プロジェクト全体はかなり大規模です。可能であれば、プロジェクト全体を送信できるようにメールアドレスを教えていただけますか? この問題の解決にご協力ください。どうもありがとうございます。 Re: S32K312_RTD400_SPD104_IAR こんにちは@Neo1096さん、 どのバージョンの IAR コンパイラを使用していますか? SPD は、リリース ノートに従って、IAR v.8.50.10 (セーフティ バージョン) とのみ互換性があります。 メールに関してはチケットを作成してください。 そこでプロジェクトを非公開で共有CAN。 BR、ダニエル
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USB 3.0 Device Mode on i.MX8M Plus Not Entering SuperSpeed Despite DWC3 Driver Loaded Hello, I am working with the NXP i.MX8M Plus EVK board and have configured the USB controller in peripheral (device) mode. The DWC3 driver loads correctly without errors, but my USB connection does not seem to enter USB 3.0 SuperSpeed mode. Instead, it falls back to USB 2.0 speeds. Here are some key details about my setup: USB port: Type-A (no CC pin available) USB mode in device tree: dr_mode = "peripheral" USBx_VBUS pin is connected via a 30kΩ resistor to the 5V VBUS line for VBUS detection. I have verified that the USB 3.0 differential pairs (TX+/TX-, RX+/RX-) are routed with matched lengths and proper impedance. The host device supports USB 3.0 and uses certified USB 3.0 cables. Despite the above, the device does not detect or connect at SuperSpeed rates. I have checked the kernel logs and see the DWC3 driver initializing, but no mention of SuperSpeed enumeration. The lsusb -t command only shows USB 2.0 speeds. Could you please advise on what I might be missing in hardware or software configuration? Any pointers on debugging steps, device tree settings, or necessary signal checks would be greatly appreciated. Thank you very much for your help! Best regards, Re: USB 3.0 Device Mode on i.MX8M Plus Not Entering SuperSpeed Despite DWC3 Driver Loaded Hello, The MX8MP has an errata related to immediate wakeup from deep sleep when a USB device is connected, specifically ERR050689: USB: USB3 device immediate wakeup in low power mode according to the NXP Community.  This errata describes a scenario where the device wakes up instantly from deep sleep when a USB device is connected and the USB hub's wakeup flag is set.  The solution to this errata may involve modifying the code related to the TCPC (Type-C Port Controller) driver in u-boot, specifically by disabling the PD (Power Delivery) function of USB1 according to NXP Community.  In some cases, the USB 3.0 device may prevent the system from entering sleep mode.      Regards
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SEGGER J-LinkとS32DS IDEを使用したS32K144 MCUのデバッグ問題 もちろんだよ、ゴーサム!コミュニティ グループ (NXP フォーラム、Stack Overflow、組み込みシステム グループなど) に投稿できる、質問の明確で技術的なバージョンは次のとおりです。 こんにちは、皆さん 私はS32K144に取り組んでおり、現在カスタム MCAL ドライバを開発しています。開発には、 SEGGER J-Link デバッガーとS32 Design Studio (S32DS)を使用しています。 コードをデバッグしようとすると、レジスタとメモリのアクセスに関連するエラーと警告が連続して発生します。主なエラー メッセージは次のとおりです。 ERROR: Cannot read register 26 (FAULTMASK) while CPU is running ERROR: Cannot read register 27 (CONTROL) while CPU is running ... ERROR: Cannot read register 64 (FPS31) while CPU is running WARNING: Failed to read memory @ address 0xDEADBEEE 観察: これらのエラーは、ターゲットの実行が開始されるとすぐに表示されます。 CPU が実行モードの間は、デバッガーはシステム レジスタや浮動小数点レジスタにアクセスできないようです。 メモリ警告は無効なアドレスを指しています: 0xDEADBEEE。 現在の設定: MCU: NXP S32K144 (ARM Cortex-M4F) IDE: S32 Design Studio デバッガ:SEGGER J-Link(SWDモード、1MHz) アプリケーション: ベアメタル、カスタム MCAL ドライバの開発とテスト デバッグモード: GDBサーバー経由でコネクテッドし、S32DS経由でフラッシュ/デバッグ 質問: CPU の実行中にこれらのレジスタ アクセス エラーが発生するのはなぜですか? 実行中にレジスタの読み取りを許可する設定はありますか、それとも CPU を停止する必要がありますか? 0xDEADBEEE でのメモリ アクセスの根本的な原因は何でしょうか? これは、NXP ドライバまたは MCAL の初期化されていないポインターに使用される一般的なデフォルト値ですか? 低レベルの MCAL ドライバを開発するときに、これらのデバッガーの制限を処理するための推奨される方法はありますか? S32K1xx MCU、MCAL 開発、または SEGGER J-Link ツールに携わったことがある方からの助言をいただければ幸いです。さらにログや設定の詳細が必要な場合はお知らせください。 よろしくお願い申し上げます。 Re: Debugging Issue with S32K144 MCU Using SEGGER J-Link and S32DS IDE こんにちは@Gowtham_768さん、 追加の回答で申し訳ありませんが、以下の情報の確認にご協力ください。 ボードに接続しようとするのは今回が初めてですか、それとも以前デバッグして接続できたことはありますか? S32DS v3.6を使用していますか?そうでない場合、どのバージョンですか?また、SDKs または RTD ドライバを実装しているかどうか、またそのバージョンも教えてください。 CPU の実行中にレジスタアクセスエラーが発生するのはなぜですか? 実行中にレジスタの読み取りを許可する設定はありますか? それとも CPU を停止する必要がありますか? CPUを停止する必要があります。 0xDEADBEEE でのメモリ アクセスの根本的な原因は何でしょうか?これは、NXP ドライバや MCAL の初期化されていないポインターに使用される一般的なデフォルト値でしょうか? 0xDEADBEEE 値は主にエラーを示します。これは標準的なメモリ位置ではなく、メモリセクションが初期化されていないかエラーがあることを示すために使用される値です。あなたのCASE、MCUに接続できないとだけ表示されると思います 低レベルの MCAL ドライバを開発するときに、これらのデバッガーの制限を処理するための推奨される方法はありますか? 最初に言うべき、そして最も明白なことは、接続が正しいことを再確認することです。以前は接続できたのに今は接続できない場合は、接続を妨げている原因がいくつか考えられます。 大量消去を実行する際に、デバイスはセキュリティ機能を使用していました。 デバイスは保護されています。 フラッシュ構成フィールドが侵害されました。 この問題の詳細については、次のアプリケーション ノートを確認してください。 AN12130: S32K1xx MCU 向け量産フラッシュプログラミングのベストプラクティス – アプリケーションノート よろしくお願いします、 ジュリアン
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MIFARE DESFire additional access rights What are additional access rights and how they are coded for MIFARE DESFire cards? I just now they should be in 0xFFFF form, but what it means and what additional rights it gives? Getting Started
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MPC5748G FLASH write process power interruption Hello, when I was using MPC5748G-176 to write FLASH program, I accidentally power off, resulting in I can not write FLASH later. Is the chip locked? How to unlock or force erase? 回复: MPC5748G FLASH write process power interruption I have solved this problem by erasing FLASH with PKGPPCNEXUSSTARTER
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PFE performance is lower compared to GMAC on S32g3 RDB3 We are trying to measure the performance of PFE and GMAC on S32G3 using udp communication. Test setup: Board 1 : RDB3 with BSP43  Board 2: RDB3 with BSP43 Both RBD connected using ethernet cable and measured. Buffer size: 64 bytes Tried with simple UDP client server application. udp_client running in Board1 and ,udp_server running in Board2. It is simple ping pong udp test and measures the round-trip time of udp packets. We tried four combinations and results were attached for those combinations. ETH<->ETH, ETH<->PFE2, PFE2<->ETH, PFE2<->PFE2 From the results we could find that PFE to PFE communication is very less performance compared to other combination. We are expecting PFE communication should be higher compared to GMAC. Re: PFE performance is lower compared to GMAC on S32g3 RDB3 Hello @kamal_n, Thanks for your patience, the internal team has shared the following: " When not using L2-Bridge configuration (using PFE as a normal network interface) the latency of PFE is worse than GMAC theoretically. It is because PFE will try to check the configuration to see if the packets hit the rules and it takes time to do it. The advantage of PFE is that it can be used as a switch or router, which offloads the CPU. The classic scenario is that you could send frames from PC1 to EMAC1 and PFE will forward it to EMAC0 or EMAC2 according to your configuration. In this case, CPU does not participate in forwarding and latency would be definitely short than the case that CPU handle the forwarding.  "  To configure PFE bridging, please check the PFE_S32G_A53_LNX_UserManual.pdf, which you can find in FlexNet packed in PFE-DRV_S32G_A53_LNX_1.9.0_DOC.zip. In particular check sections: 3 Build Procedure 2.10 FCI use cases for Linux Please let me know if you encounter any problem while configuring the PFE bridging. Re: PFE performance is lower compared to GMAC on S32g3 RDB3 Hello @kamal_n, I was able to reproduce your results, I only tested with PFE-PFE and GMAC-GMAC, getting similar results, PFE has a lower performance compared to GMAC. I was not able to find anything clear in the documentation, I will share this topic with the internal team and wait for their feedback. Thanks in advance for your patience. Re: PFE performance is lower compared to GMAC on S32g3 RDB3 Hello @kamal_n, Thanks for all the details, please allow me some time to replicate your tests and confirm I see the same behavior, at the same time I will search more information regarding the latency of PFE in linux. Thanks for your patience. Re: PFE performance is lower compared to GMAC on S32g3 RDB3 Hi @alejandro_e , Please find below details 1. MAC configuration RGMII 2. Attached printenv results as file 3. 1000Base-T port used with RGMII for GMAC0 and PFE_MAC2 4. No changes done specific to SJA1110 and we are not using SJA1110  5. No network specific changes done from our side. We have tested using buffer size of 64 bytes and tried also 1024 bytes. Can you suggest the size of buffer to note difference in performance in PFE. Thanks in advance. Re: PFE performance is lower compared to GMAC on S32g3 RDB3 Hello @kamal_n, Thanks for reaching out to us. Could you give me more details regarding the test? Please share the following: The used configuration for each MAC interface (SGMII or RGMII) the output of the following command in u-boot: => printenv The exact  of the RDB3 ports you are using in each test for both boards. Any change related to the SerDes (in case of SGMII) in your setup Any change change related to the SJA1110 in your setup Any change related to network in Linux in your setup Thanks in advance
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我们可以通过 IMX8MP 板上的 OTA 更新来更新 uboot 镜像吗 你好,团队、 我目前正在研究固件升级程序,还想包括一项更新 U-启动 的配置。 根据恩智浦的文档: 恩智浦BootROM始终从固定偏移量(imx-boot)启动。 因此,bootROM 无法根据标志在多个 imx-boot 启动映像(例如 imx-boot_a 和 imx-boot_b)之间切换。 为了解决这个限制,我计划将 U-Boot 启动映像移到启动分区,在 imx-boot 中只保留最少的 SPL 代码。然后,SPL 将从所选分区加载相应的 U-Boot 启动映像。 我目前正在查看 mkimage 代码,以了解 U-Boot 是如何代码包到 imx-启动 中的,但是到目前为止我还没有找到明确的解释。 请确认这种方法在当前架构下是否可行? 或者,作为固件升级(例如 OTA)的一部分,还有其他推荐的更新U-启动的方法吗? 谢谢 Jyo Re: Can we update uboot image over OTA update on IMX8MP board imx8mp 支持次映像启动,但这与你提到的应用程序不同,更多详细信息,你可以参考第 13.2 章如何为附带文件的二次启动创建镜像,参见第 4.3 章 i.MX 系列芯片有两个复制的引导加载程序的辅助启动,但仍然不建议升级引导加载程序。 Re: Can we update uboot image over OTA update on IMX8MP board 你好@joanxie 感谢您的回复。 我的主要目标是使用双分区方案通过OTA支持U-启动更新。 为此,U-启动 需要位于单独的偏移量,并且 SPL 应该能够选择要更新的固件映像(U-启动_A 或 U-启动_B)。 请确认 SPL 是否有可能跳转到不同的偏移量(U-Boot_A 或 U-Boot_B)。 Re: Can we update uboot image over OTA update on IMX8MP board 随附的 AN 将为您提供更多有用信息,请参阅
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OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D Hi. It uses DDR3L. I used the configuration file "MX7D_DDR3_register_programming_aid_v1_2.xlsx" and "/mx7dsabresd/imximage.cfg" in u-boot as references. At the end of the setup, I read DDRC_STAT, but OPERATING_MODE remains Init. How do I get to Normal mode? I think this mode probably doesn't become Normal, so reading 0x80000000 causes the computer to freeze. Best regards. Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D Hi Pengyong_zhang. Thanks. First, since I was using the same Micron DDR3, I wrote the code according to the "i.MX7D DDR Controller Configuration Spreadsheet." However, I was unable to access the DDR. At the time, I was unaware that initialization had not yet finished. Next, I found the SABRE board settings in u-boot, changed it to this code and tried it. However, this was also not accessible. I confirmed that initialization had not yet finished. Below is the write code. DDRC_MSTR : 0x01040001 DDRC_DFIUUPD0: 0x80400003 DDRC_DFIUUPD1: 0x00100020 DDRC_DFIUUPD2: 0x80400004 DDRC_RFSHTMG: 0x00400046 DDRC_MP_PCTRL_0: 0x00000001 DDRC_INIT0: 0x00020083 DDRC_INIT1: 0x00690000 DDRC_INIT3: 0x09300004 DDRC_INIT2: 0x00000000 DDRC_INIT4: 0x04080000 DDRC_INIT5: 0x00200004 DDRC_RANKCTL: 0x0000033F DDRC_DRAMTMG0: 0x09081109 DDRC_DRAMTMG1: 0x0007020D DDRC_DRAMTMG2: 0x03040407 DDRC_DRAMTMG3: 0x00002006 DDRC_DRAMTMG4: 0x04020205 DDRC_DRAMTMG5: 0x03030202 DDRC_DRAMTMG8: 0x00000803 DDRC_ZQCTL0: 0x00800020 DDRC_ZQCTL1: 0x02000100 DDRC_DFITMG0: 0x02098204 DDRC_DFITMG1: 0x00030303 DDRC_ADDRMAP0: 0x0000001F DDRC_ADDRMAP1: 0x00080808 DDRC_ADDRMAP5: 0x04040404 DDRC_ADDRMAP6: 0x0F040404 DDRC_ODTCFG: 0x06000604 DDRC_ODTMAP: 0x00000001 SRC_DDRC_RCR: 0x00000000 I read DDRC_STAT here, but it was not set to Normal. Best regards. Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D Hi patterson123. I appreciate the specific advice. I'll try again following your advice and will get back to you with the results. Best regards. Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D The user wants a short paragraph summarizing the detailed response about their DDR initialization issue. I need to extract the key points from the previous response: * **The Problem:** The DDR controller's `OPERATING_MODE` is stuck in `Init` mode, meaning memory initialization failed. * **The Cause:** This usually happens due to an incomplete initialization sequence or incorrect register values. * **The Solution:** The user must ensure their code correctly initiates the training sequence by setting the `DDRC_MSTR` register. They should then poll the `DDRC_STAT` register, waiting for the `OPERATING_MODE` to transition to `Normal`. Double-checking the register values from the programming aid is also a critical step. I'll combine these points into a single, concise paragraph. Your DDR controller's `OPERATING_MODE` is stuck in `Init` because the memory initialization sequence has failed to complete. This is most often caused by an incomplete code sequence or incorrect register values. To fix it, ensure your code correctly initiates the memory training by writing the appropriate value to the `DDRC_MSTR` register. You must then poll the `DDRC_STAT` register, waiting for the `OPERATING_MODE` to transition to `Normal`, which signals a successful initialization. Double-checking your timing and calibration register values against the provided programming aid is also a critical step. Re: OPERATION_MODE of DDRC_STAT remains at Init and does not become Normal on i.MX7D Hi @tamotsu  What changes did you make to the code?and How do you read the register value? B.R
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Questions about the IW612 test content(UM11717) Question about UM11717 1.Is PRBS the same as PRBS9, which means pseudorandom binary sequence of order 9?   (UM11717 P.87, 89) 2.Please tell me the specifics of Whitening (UM11717 P.87-90 ) 3.There is an error in the example for the receive antenna number setting command. Is this a mistake? (UM11717 P.51-59, 61, 64-66) Example 10 0 2 2 // Set both TX and RX to antenna 2 (p. 27) → 10 2 2 4.If I input the Tx/Rx command sequences for 802.11b, g, a, n, ac, and ax in order, will I get the correct count? Also, I don't know when the counting starts, so please let me know. (UM11717 P.51-60)
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i.MX RT1064 + TI DP83825I PHY Integration Issue We are using the i.MX RT1064 controller from NXP in our project. For Ethernet connectivity, we selected the DP83825I PHY from Texas Instruments. In MCUXpresso IDE, we tested the Ethernet example for EVK-MIMXRT1064, which uses the KSZ8081 PHY. With the KSZ8081, Ethernet link and auto-negotiation work correctly. However, with the DP83825I PHY, the link and auto-negotiation do not function as expected. We are looking for guidance to resolve this issue with the DP83825I and i.MX RT1064 integration. Re: i.MX RT1064 + TI DP83825I PHY Integration Issue Hello Unfortunately, there is no specific driver for DP83825I PHY. To make that specific phy work on your board, you will need to implement that driver. The SDK contains the drivers for DP83848; you can refer to that driver, only modifying specific components for DP83825I.  BR, Omar
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SPI Flash expansion from 16M to At 64Mbytes, the read data is inconsistent with the original data. In the NXP RT1172 MCU's built-in 16MByte SPI Flash environment, using the NXP GUI Guider to generate "Image to C File" data, the screen displays normally using the NXP GUI Guider's image function or by programmatically loading image data into a drawing app. Furthermore, reading and writing the image data loaded by the drawing app, as shown in the log messages, correctly correspond to the "Image to C File" data. However, when the memory is expanded to 64MBytes, as soon as the 16MByte address space is exceeded, why does the "Image to C File" data not correspond correctly when using the forced addressing write method (.ld) or the direct addressing method (NXP GUI Flash Tool) in the NXP MCUXpresso IDE window? The following is related information: NXP MCUXpresso IDE Windows Version: v11.8.0 [Build 1165] [2023-07-26] NXP GUI Guider Version: GUI-Guider-1.6.1-GA MCU: NXP RT1172 MCU SDK Version: 2.14.0 Manage Linker Script: evkmimxrt1170_lvgl_guider_cm7_v8_Debug.ld (Original: Checked, unchecked, and addressing set outside the 16MBytes) Screen Size: 728x1280 Image Data: PNG file, 720x1280, 24-bit data Conversion Settings: Bin or C, ARGB8565 or ARGB8888, or CF_TRUE_COLOR or CG_TRUE_COLOR_ALPHA , any setting is fine as long as it displays correctly. LVGL related settings: #define LV_COLOR_DEPTH 16 (Color depth: 1 (1 byte per pixel), 8 (RGB332), 16 (RGB565), 32 (ARGB8888)) i.MX-RT1170  回复: SPI Flash expansion from 16M to At 64Mbytes, the read data is inconsistent with the original dat Unfortunately, there is no example for this however I can guide you. Besides defining a larger flash size on the linker file it is important to consider that the FCB also increases the flash size, this can be updated on the flexspi_nor_config file increasing the flash size only if only that parameter is different between the flash. If an error rises and it seems unable to erase the flash to return to normal operation, then you will need to enter Serial Download mode so the flash can be erased. Unfortunately, there are no examples for this. BR, Omar 回复: SPI Flash expansion from 16M to At 64Mbytes, the read data is inconsistent with the original dat I already know how to disable the automatic .ld mode and switch to manual editing, and I'm already running the process. However, there seem to be many issues with converting the SPI Flash from 16MBytes to 64MBytes. First, could you provide any suggestions or information regarding the following: 1. Are there any example programs for expanding the 16MBytes to 64MBytes size for the NXP RT1172/RT1176? 2. If there are errors in the initial SPI Flash environment setup and the void BOARD_ConfigMPU(void) internal configuration, an error interrupt message may appear during the programming process. During this time, even using debug mode, I can't clear the SPI Flash and restore the system to normal operation. Are there any other ways to avoid this problem? 3. Are there any example programs or practical assistance for establishing a 64MBytes SPI Flash environment and building the SPI Flash programming format (boot and program content)? The following is the expected build. The main stages of the 64MByte SPI Flash project include: The first stage covers initializing the SPI Flash environment. The second stage covers configuring the .ld file and void BOARD_ConfigMPU(void) . The third stage covers how to allocate 64MBytes of memory. Re: SPI Flash expansion from 16M to At 64Mbytes, the read data is inconsistent with the original dat If you are manually editing the linker script then you need to uncheck the "managed linker script" box so the modified values on the .ld are not overwritten. BR, Omar
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S32G FCCU fault reaction Hi Deer NXP expert:       In S32GxxSM chapter 1.3.11,it describe the R1、R2 and R3 fault-reaction type.       When comes to R3,it recommend to ’initiates a chip functional reset‘,which can be achieved by assert NCFS_CFGa=1b.       But R2 also  recommend to ’then initiates a chip functional reset‘,which confuse me that how to achieve it?Should I assert NCFS_CFGa=1b same as R3,or assert a functional reset in fault interrupt?         If i need to assert a functional reset in fault interrupt,please introduce how to achieve it in detail,thanks a lot! Re: S32G FCCU fault reaction Hello, @Hi-rain4  Thanks for the post. From the S32G safety manual, for R2, it is suggested using the fault interrupt handler to store information about the fault in memory and then initiates a chip reset. The S32 SAF microcontroller error management (eMCEM) component provides a fault interrupt handler. For details,  I suggest directly reading the corresponding code and document within eMCEM module in SAF. BR Chenyin
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How to obtain download permissions The account does not have permission to download latest driver and Labtool for 8987 #Driver package: https://www.nxp.com/webapp/Download?colCode=SD-WLAN-UART-BT-8987-LNX_6_12_20-IMX816.92.21.p151&appType=license #Labtool package : https://www.nxp.com/webapp/sps/download/license.jsp?colCode=MFG-W8987-MF-WIFI-BT-BRG-FC-VS20131.1.0.196.0-16.8&appType=file1&DOWNLOAD_ID=nul Re: How to obtain download permissions You may contact the local DFAE for help you this.
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Driver V.2 dynamic startup failed - driver Init provided no flash parameters MIMXRT1060 - EVK (board - MIMXRT1862DVL6A) Have configured SW7 as 0010. Connected jumper to J7 and J1(5-6). J42 is not connected by jumper and the board is powered on via J41. We are trying to flash the application but are facing this error while flashing : Driver V.2 dynamic startup failed - driver Init provided no flash parameters Development Board MCXA Power Re: Driver V.2 dynamic startup failed - driver Init provided no flash parameters Thanks for your interest in NXP MIMXRT series! Please help me try the method mentioned in this thread:https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/RT-board-recovery-for-debugger-connect-issues/ta-p/1635260 Best regards, Gavin
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MK82FN256xxx15_qspi_alias example linker error When compiling the frdmk82f_hello_world_qspi_alias sample project with MCUXpresso IDE v11.9.1_2170, the linker returns the following error: MK82FN256xxx15_qspi_alias_mcux.ld:103: syntax error. The "MK82FN256xxx15_qspi_alias_mcux.ld" file is attached. (Zip Compressed) How can I fix the problem at linker file line 103? /* * for exception handling/unwind - some Newlib functions (in common * with C++ and STDC++) use this. */ .= ORIGIN(m_flash);  /*  ---> line 103 <--- */ .ARM.extab : ALIGN(4) { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_flash Re: MK82FN256xxx15_qspi_alias example linker error Hello @opetrone , Thanks for your post. This is a syntax error, please modify the 103 line from: .= ORIGIN(m_flash); to . = ORIGIN(m_flash); There's a missing space here.  Then you will find it can build successfully: Hope it can help you. BRs, Celeste -------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! --------------------------------------------------------------------------------------------------------------------
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RD-BESSK358BMU 的调试问题 你好,恩智浦: 目前,我想使用恩智浦 S32K3 BESS Application Version 0.8.0 Demo 代码(我什么都没改)闪存和调试 RD-BESSK358BMU EVB,但遇到了一些问题,第一次调试可以,第二次调试就失败了。(我可以提供其他简单的示例代码)。 出现这个问题后,我甚至无法使用 j-flash 工具擦除图像。您有这方面的经验吗? 附件是控制台日志。 谢谢! BR, BillWen Re: Debug problem on RD-BESSK358BMU 您好,Robin_Shen: 真的非常感谢您的帮助。我会联系我们代理商的 FAE。 谢谢 BR,BillWen Re: Debug problem on RD-BESSK358BMU 私人请联系 FAE。 Re: Debug problem on RD-BESSK358BMU 您好 Robin_Shen: 是的,谢谢您的帮助,我可以在删除 R228 后擦除图像。 最后一个问题,从哪里可以获得 BESS s32k358 的最新版本软件?这个版本是私密的还是公开的?还是我只能从代理商的FAE那里得到它? 谢谢 BR,BillWen Re: Debug problem on RD-BESSK358BMU 是的。你需要重新设计 EVB 板(移除 R228)。 如果您有示波器或逻辑分析仪,则应该能够测量 RESET S32K3 的低电平信号。 Re: Debug problem on RD-BESSK358BMU Hi Robin_Shen: 对不起,我不明白您的意思。你的意思是我需要重做 EVB 板(移除 R228)然后我才能使用 j 闪存擦除镜像? 感谢 BR、BillWen Re: Debug problem on RD-BESSK358BMU 由于这个旧固件有问题,FS26 一直在 RESET S32K358。恐怕您需要断开 R228,重新下载 S32K358 的程序。 很抱歉给您带来不便! Re: Debug problem on RD-BESSK358BMU Hi Robin_Shen: 问题是我现在无法删除,我不知道该怎么做。你有什么建议吗? 感谢 BR、BillWen Re: Debug problem on RD-BESSK358BMU 嗨,BillWen、 请联系 FAE 以获取已修复此问题的最新August_2024_Release 版本。 祝好, Robin ------------------------------------------------------------------------------- 注: - 如果本帖回答了您的问题,请点击"ACCEPT AS SOLUTION" 按钮。谢谢! - 我们会在最后一次发帖后的 7 周内跟踪主题,之后的回复将被忽略 如果您以后有相关问题,请另开新主题并参考已关闭的主题。 -------------------------------------------------------------------------------
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[i.MX8Mmini] Could you please advise how to change the SDIO speed? We are running on i.MX8Mmini-EVK using LF_v6.6.52-2.2.0_images_IMX8MMEVK. In this environment, we are connecting the WLAN module via SDIO. We are experiencing issues with SDIO communication failing at high and low temperature environment. To avoid this issue, we want to change the SDIO speed from "SDR104 mode (208 MHz) (1.8V)" to "DDR50 mode (50 MHz) (1.8V)" or "HS mode (25MHz) (3.3V)". Could you please advise how to change the SDIO speed? Best Regards, Re: [i.MX8Mmini] Could you please advise how to change the SDIO speed? glad to hear this, this thread will be closed soon, any further questions, pls contact us again Re: [i.MX8Mmini] Could you please advise how to change the SDIO speed? Dear joanxie-san, Sorry for our reply overdue. We were able to change the SDIO speed with your advice. We were able to confirm the expected behavior. We appreciate your support. Best Regards, Re: [i.MX8Mmini] Could you please advise how to change the SDIO speed? Dear joanxie-san, Thank you for your support. We will try the steps your advised. Best Regards, Re: [i.MX8Mmini] Could you please advise how to change the SDIO speed? I don't know why the reply was gone, I post again  you can refer to this try to add  sd-uhs-sdr50 in the dts file and set the max-frequency in the dts https://github.com/nxp-imx/linux-imx/blob/b586a521770e508d1d440ccb085c7696b9d6d387/Documentation/devicetree/bindings/mmc/mmc-controller.yaml also can try to set sdhci-caps-mask = <0x00000003 0x00000000>; in the dts to force the mode to the DDR50
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i.MX93、i.MX94、i.MX95 のピン互換性 こんにちは、 i.MX 9 シリーズの使用を検討していますが、i.MX93 は i.MX94 や i.MX95 とピン互換性があるかどうかを知りたいです。 そうでない場合、i.MX94 と i.MX95 はピン互換性がありますか? ありがとうございます グレッグ
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SENT TX using FlexIO on S32K324 Hi everyone, I am trying to implement the SENT procotol on S32K324. There is an example for SENT RX on FlexIO inside the IDE: But, I do not see SENT TX. I want to use FlexIO for this. Is there any example project on this topic? I would appreciate this. Thanks in advance. Re: SENT TX using FlexIO on S32K324 Hi @ilx123, Usually, the SENT signal is usually transmitted by an external sensor and received by the MCU, those are the only demos we provide. However, you can use the eMIOS component if you want to implement the SPC Protocol. Here are some community related posts:  SPC and SENT protocol with S32K344 - NXP Community SENT TX emulation using FLEXIO or EMIOS - NXP Community Best regards, Julián
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