Inline ECC: What it does and how to implement it (Japanese blog) Inline ECC (Inline Error Correction Code) is a type of mechanism that detects and corrects bit errors that occur in memory or storage in real time. Enabling the inline ECC function on a DDR controller like the i.MX 8M Plus reduces DDR access performance, but by using approximately one-eighth of the DDR capacity as the ECC area, there is no need to add dedicated memory to store the ECC (reducing BOM costs).
This article explains the functionality of inline ECC and introduces how to implement it.
1. i.MX 8M Plus Inline ECC function
The i.MX 8M Plus DDR Controller supports inline ECC to protect the system from soft errors (DRAM bit flips caused by alpha rays, neutrons, etc.). By storing 8 bits of ECC (Error Correcting Code) for every 64 bits of data, it can correct single-bit errors and detect double-bit errors.
Since there is no dedicated memory for storing ECC, approximately 1/8 of the DDR capacity is used as the ECC area.
Since the 32-bit data bus is shared between data and ECC, enabling the Inline ECC function will reduce DDR access performance.
1.1.SEC (Single-bit Error Correction)
SEC is a DDR controller function that detects single-bit errors and corrects them to the correct value.
Fig. 1 Schematic diagram of SEC
1.2.DED (Double-bit Error Detection)
DED is a feature of the DDR controller that detects double-bit errors.
Fig. 2 Conceptual diagram of DED
Note:
In reality, SEC and DED are detected in a 64-byte aligned data area (plus 8 bytes of ECC), not 8 bytes.
2. Inline ECC memory mapping (outline)
The method for setting Inline ECC memory mapping varies depending on the DDR capacity.
2.1.DDR densities are powers of two (binary-aligned densities )
For example, in the case of 1, 2, 4, 8, 16GB,
The lower address 7/8 of the DDR is used as the data area, and the upper address 1/8 is used as the ECC area. The ECC area is generally not accessible.
The data area is divided into up to eight regions: Regions 0 to 6 and Other Regions. ECC functionality can be enabled or disabled for each region.
Regions 0 to 6 all have the same capacity, and are set to 1/8, 1/16, 1/32, or 1/64 of the DDR capacity. The remaining regions are all Other regions.
The following is the memory mapping when the capacity of Regions 0 to 6 is set to 1/8. In this case, there is no Other region.
Fig. 3 Memory Mapping Example (1/8)
Below is the memory mapping when the capacity of Regions 0 to 6 is set to 1/16.
Fig. 4 Memory Mapping Example (1/16)
2.2.DDR densities that are not a power of two (non-binary-aligned densities)
For example, in the case of 3, 6, or 12 GB (the i.MX 8M Plus LPDDR4 EVK is 6 GB, so this applies to this case).
Divide the entire DDR into thirds with a capacity that is a power of two.
For 3GB, 1GB x 3
For 6GB, 2GB x 3
For 12GB, 4GB x 3
For the lower address area divided into three parts, make the settings as follows : 2.1. When the DDR capacity is a power of 2 .
The settings for the two upper address areas of the three-part division are the same as the settings for the lower address area.
Below is the memory mapping when 1/8 is set.
Fig. 5 Example of memory mapping when DDR capacity is not a power of 2 (1/8)
3. Setting with DDR Register Programming Aid
Configure Inline ECC using DDR Register Programming Aid (DDR RPA).
Note:
Please prepare a DDR RPA that can run the DDR stress test with Inline ECC disabled (and that can also be verified to run u-boot).
Inline ECC does not function properly with i.MX8MP LPDDR4/DDR4 RPA v6 or earlier due to a bug. Please use at least v7 or later. Unless there are special circumstances, please use the latest version of DDR RPA. (As of September 2024, the latest version is v9.)
lpddr4_timing.c for i.MX 8M Plus EVK included in U-Boot of Linux BSP and ddr4_timing.c Although it appears to work at first glance because it contains the define CONFIG_IMX8M_DRAM_INLINE_ECC , there is a problem with the Inline ECC settings and it does not work properly. Even if you are testing with the EVK, please generate lpddr4_timing.c/ddr4_timing.c using DDR RPA and DDR Tool.
3.1.Enable Inline ECC
In the DDR RPA Register Configuration sheet, set the Inline ECC item to Enable.
3.2.Memory Mapping
3.2.1.DDR densities are powers of two (binary-aligned densities)
If the DDR capacity is a power of 2, use the ECC_Config_BinaryAligned sheet.
Specify the capacity of Region 0 to 6. (1/8, 1/16, 1/32, or 1/64)
Enables or disables ECC for Regions 0 to 6 and Other Regions (either PROTECTED or UNPROTECTED).
This is an example when the capacity of Regions 0 to 6 is set to 1/8.
Fig. 6 DDR RPA settings (1/8)
This is an example when the capacity of Regions 0 to 6 is set to 1/16.
Fig. 7 DDR RPA settings (1/16)
3.2.2.DDR densities that are not a power of two (non-binary-aligned densities)
If the DDR capacity is not a power of 2, use the ECC_Config_nonBinaryAligned sheet (this is the case for the i.MX 8M Plus LPDDR4 EVK, which is 6GB).
Specify the capacity of Region 0 to 6. (1/8, 1/16, 1/32, or 1/64)
ECC Enables or disables ECC for Regions 0 to 6 in Memory Region 0 and other regions (either PROTECTED or UNPROTECTED).
ECC Memory Region 1/2 will automatically be set to the same settings as ECC Memory Region 0.
This is an example when the capacity of Regions 0 to 6 is set to 1/8.
Fig. 8 DDR RPA Settings (1/8)
This is an example when the capacity of Regions 0 to 6 is set to 1/32.
Fig. 9 DDR RPA settings (1/32)
4. Testing with DDR Tool and generating lpddr4_timing.c/ddr4_timing.c
You can use the DDR Tool to check the operation of the settings made in DDR RPA.
If the DDR stress test passes, generate lpddr4_timing.c/ddr4_timing.c to be incorporated into U-Boot.
5. Inline ECC implementation in U-Boot
5.1.Replacing lpddr4_timing.c/ddr4_timing.c
lpddr4_timing.c Or replace ddr4_timing.c with the files generated by DDR RPA and DDR Tool.
uboot-imx/board/freescale/imx8mp_evk/lpddr4_timing.c
uboot-imx/board/freescale/imx8mp_evk/ddr4_timing.c
5.2.Adding Config
Add CONFIG_IMX8M_DRAM_INLINE_ECC=y to your U-Boot config file .
Add Listing 1 to uboot-imx/configs/imx8mp_evk_defconfig
CONFIG_IMX8M_DRAM_INLINE_ECC=y
Note:
The U-Boot config file imx8mp_evk_inline_ecc_defconfig was added in Linux BSP 5.4, but is not properly maintained and is therefore deprecated. When testing with an EVK, it is safer to add the config to imx8mp_evk_defconfig and use it.
5.3.Changing the Linux reserved area¶
Access to the ECC area from software is prohibited. Therefore, the device tree is dynamically modified so that the Linux kernel (and other system software) treats the ECC area as a reserved area. The default is hard-coded to match the DDR capacity of the EVK (6GB for LPDDR4, 4GB for DDR4), so the code must be modified if the DDR capacity is different from that of the EVK.
Use function ft_board_setup in uboot-imx/board/freescale/imx8mp_evk/imx8mp_evk.c to change the ECC area to match the actual DDR capacity. For example, for DDR4, the start address and size of the ECC area are hard-coded assuming a DDR capacity of 4GB.
Listing 2: DDR4 capacity hardcoded to 4GB
phys_addr_t ecc_start = 0x120000000;
size_t ecc_size = 0x20000000;
If the actual DDR capacity is 2GB, 1/8 (256MB) of the upper addresses from physical addresses 0x40000000 to 0xc0000000 is reserved as an ECC area.
Listing 3 Example of changing DDR capacity to 2GB
phys_addr_t ecc_start = 0xb0000000;
size_t ecc_size = 0x10000000;
imx8mp_evk.c If you are not using it, you will need to add processing equivalent to the ft_board_setup function.
5.4.Relocation support
If the DDR capacity is 2GB or less and OPTEE is not installed, U-Boot tries to relocate to the highest address of DDR, but it overlaps with the ECC area, so it hangs up during relocation. To avoid this, add imx8mp_evk.h Reduce the ECC area capacity (1/8) from the DDR capacity definition PHYS_SDRAM_SIZE .
Listing 4 uboot-imx/include/configs/imx8mp_evk.h
-#define PHYS_SDRAM_SIZE 0x80000000
+#define PHYS_SDRAM_SIZE 0x70000000
5.5.Exclude access processing to the ECC area
If there is other code in U-Boot that accesses the ECC area, you need to exclude access to the ECC area. For example, if a memory test accesses the entire DDR area, change it so that it does not access the ECC area.
Reference: https://github.com/nxp-imx/uboot-imx/blob/lf-6.1.55-2.2.0/configs/imx8mp_evk_defconfig#L10-L11
6. Operation check on Linux
6.1.Check the startup log
Make sure the EDAC driver is installed when Linux starts. (EDAC = Error Detection and Correction) The EDAC driver for i.MX 8M Plus is linux-imx/drivers/edac/synopsys_edac.c .
Listing 5 Checking the startup log
root@imx8mp-lpddr4-evk:~# dmesg | grep EDAC
[ 0.116733] EDAC MC: Ver: 3.0.0
[ 1.874689] EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (INTERRUPT)
6.2.Checking memory mapping
Use the command cat /proc/iomem to confirm that the ECC area is set to reserved as configured in 5.3. Changing the Linux reserved area . The following is an example for the i.MX 8M Plus LPDDR4 EVK (DDR capacity 6GB).
Listing 6 Checking memory mapping
root@imx8mp-lpddr4-evk:~# cat /proc/iomem | grep reserved
...
b0000000-bfffffff : reserved
...
130000000-13fffffff : reserved
...
1b0000000-1bfffffff : reserved
6.3.Checking when an ECC error occurs
According to application note AN13566 - ECC on i.MX 8 Series , the DDR Controller in i.MX 8M Plus does not have the function to intentionally generate ECC errors.
3.2.9 ECC error injection through software
The ECC error injection is a useful optional feature for system-level software validation. Unlike the Sideband ECC, there is no dedicated hardware support for it. However, errors can be injected through the software by unlocking the ECC region through the “ECC_REGION_PARITY_LOCK” register and overriding ECC parity bits. When the corresponding addresses are read from a protected memory region, ECC errors are generated as correctable or uncorrectable, depending on the type of error introduced.
NOTE: ECC data poisoning is not supported by the DDR controller. The reference manual will be updated to remove this functionality.
Therefore, we unlock the ECC area and modify the ECC area from the core to simulate an ECC error and perform the test. The basic idea is as follows:
Write the 8-byte value 0xffffffff_ffffffff to DataAddr. The DDRC writes to DDR and also writes 1 byte of ECC at the same time.
Unlocks the ECC region, allowing the core to access the ECC region.
Obtain the address of the ECC byte corresponding to DataAddr and read one byte of the ECC.
Write the inverted value 0xffffffff_fffffffe to DataAddr. The ECC 1 byte is also updated.
ECC 1 byte, ECC read in 3. Writes back the byte value.
Locks the ECC region, prohibiting access to the ECC region from the core.
The value of DataAddr is read. At this time, since the ECC is inconsistent, Single-bit Error Correction is activated and the corrected 8-byte value, 0xffffffff_ffffffff, is read. A Correctable Error interrupt is also notified to the core.
Note:
Since this involves accessing the DDR, the test must be performed in a non-cache area.
Fig. 10 SEC (Single-bit Error Correction) test method¶
DED (Double-bit Error Detection) debugging can be done in the same way.
7.Reference materials
Application Note: AN13566 - ECC on i.MX 8 Series
Application Note: AN13616 - Validating i.MX 8 Inline ECC Engine Functionality (contact your NXP representative to obtain this document)
i.MX 8M Family DDR Tool Release - NXP Community
i.MX 8M Plus DDR Register Programming Aids (RPA) - NXP Community
8.Caution
This document is a reference for using NXP products.
For official specifications, please refer to the product manual and application notes.
Actual operation may differ from the contents described due to differences in various conditions, such as the version of the software used.
Not all functions have been verified, so please be sure to verify and test the product to suit your intended use.
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We are currently unable to respond to comments in the " Comment " section of this post . We apologize for the inconvenience, but when making inquiries, please refer to " How to contact NXP with technical questions ( Japanese blog ) " . (If you are already an NXP distributor or have a relationship with NXP , you may contact the person in charge directly. ) Inline ECC (Inline Error Correction Code) is a type of mechanism that detects and corrects bit errors that occur in memory or storage in real time. Enabling the inline ECC function on a DDR controller like the i.MX 8M Plus reduces DDR access performance, but by using approximately one-eighth of the DDR capacity as the ECC area, there is no need to add dedicated memory to store the ECC (reducing BOM costs).
This article explains the functionality of inline ECC and introduces how to implement it. i.MX Processors Japanese Blog
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