Recently, I was programming the ADC (iMXRT1062 - Teensy 4.1) to implement an acquisition sequence with a hardware trigger generated by FlexPWM, considering the information from the i.MX RT1060 Processor Reference Manual, Rev. 3, 07/2021.
I observed two issues that might be confirmed by the community and perhaps updated in the next version of the manual.
The first refers to the configurations for routing the trigger on XBAR1. According to Table 4-5 - XBAR1 Input Assignments, page 62 of the manual, the trigger signals FlexPWM4_SM2_TRIG0 and FLEXPWM4_PWM2_OUT_TRIG1 are associated with the XBAR1_IN53 input, but my code only worked using the XBAR1_IN54 input. The code is available at https://ernane-aac.github.io/Teensy-4.1--How-to-Configure-the-ADC-System/.
The second problem concerns the sample interval configuration in the ADC_ETC_TRIG0_COUNTER register when the user decides to use bit B2B=0. The manual establishes the interval delay as: Interval_delay = (SAMPLE_INTERVAL+1)*(PRE_DIVIDER+1)*ipg_clk, so there are different combinations of SAMPLE_INTERVAL and PRE_DIVIDER that meet the application's needs. In this case, considering PRE_DIVIDER=0, SAMPLE_INTERVAL should be 271 or higher, but the code did not work for PRE_DIVIDER=0. If we change it to PRE_DIVIDER=1 and SAMPLE_INTERVAL=136, the code works. Note that the code works for any combination with PRE_DIVIDER=1 or higher, but does not work for PRE_DIVIDER=0. There seems to be something beyond a mere explanation of the function of these bits presented in the manual. The code is the same as presented at https://ernane-aac.github.io/Teensy-4.1--How-to-Configure-the-ADC-System/, just change from B2B (comment) to sample interval (uncomment sample interval and pre-divider definition).
Let me know if anyone gets a different result.
Hi @Ernane ,
Thank you so much for your interest in our products and for using our community.