i.MX 8M Plus LPDDR4 EVK - enabling eMMC boot0/boot1 Board: i.MX 8M Plus LPDDR4 EVK (MIMX8ML8DVNLZAA), IMX8MPEVKHUG rev 0 HAB: fused OPEN (SRK not burned, deliberately, still evaluating) I am implementing bootloader-update redundancy for a RAUC-based A/B update system and want to use the eMMC's hardware boot0/boot1 partitions (BOOT_PARTITION_ENABLE) the way many i.MX8M designs do — write the new bootloader to the inactive boot partition, flip which one is active, and rely on the ROM to fall back to the other if the newly-active one fails. I specifically want to avoid burning any BOOT_CFG/efuses for this. What I have observed on the EVK, using mmc-utils built from the poky/oe-core mmc-utils recipe: - mmc extcsd read /dev/mmcblk2 reports PARTITION_CONFIG with BOOT_PARTITION_ENABLE already set to boot0 (value 0x08). - boot0 (/dev/mmcblk2boot0) contains a valid-looking image (correct IVT tag at offset 0), but it does not match my currently deployed bootloader. - boot1 (/dev/mmcblk2boot1) is completely empty (all zero). - A byte-exact comparison confirms the board is actually booting from the raw eMMC user area at the standard 32 KiB offset (content matches my currently deployed imx-boot exactly) — not from boot0, despite PARTITION_CONFIG indicating boot0 is enabled. So on this board, EXT_CSD's BOOT_PARTITION_ENABLE appears to have no effect on the ROM's actual boot source. Per IMX8MPEVKHUG section 2.2, the EVK's SW4 switch only selects the coarse boot device class (eMMC vs SD vs QSPI vs NAND vs fuses vs USB serial download) — there is no switch position for the eMMC boot-partition sub-mode. Questions: 1. Is there a supported way to select "ROM boots from eMMC boot0/boot1 hardware partition" on the LPDDR4 EVK specifically, without setting BT_FUSE_SEL=1 / burning BOOT_CFG efuses — e.g. a jumper, resistor option, or alternate SW4/SW1101 combination not documented in IMX8MPEVKHUG rev 0? Or is this hard-strapped on this board's PCB to always boot from the eMMC user area regardless of EXT_CSD state? 2. If BOOT_CFG efuses are the only way to enable eMMC boot-partition mode: are the BOOT_CFG fuse banks that control this independent of the SRK-hash fuses used for HAB? I want to understand whether enabling eMMC boot-partition redundancy via fuses would force me to also commit to closing HAB (SRK burn) at the same time, or whether these are separable decisions. 3. For a custom board design (not the EVK) using the i.MX 8M Plus with eMMC, what is the recommended way to make eMMC boot0/boot1 redundancy available from first bring-up — i.e., what needs to be true in the BOOT_CFG GPIO strapping / PCB design so this is a day-one option rather than something that requires a later fuse commitment? Any pointers to the specific Reference Manual section covering the BOOT_CFG bit definitions for eMMC boot-partition selection (beyond the SW4 device-class bits already covered in IMX8MPEVKHUG) would also be appreciated. Thank you! Re: i.MX 8M Plus LPDDR4 EVK - enabling eMMC boot0/boot1 FYI for i.Mx8 UM at chapter 5.8.2.2.1 High Level eMMC Boot Flow The SCU ROM supports 4 eMMC boot scenarios: 1. In this scenario, the "eMMC fast boot" fuse is blown. The primary and secondary image container set are both in the boot partitions, and BOOT_PARTITION_ENABLE = 1 or 2. 2. In this scenario, the "eMMC fast boot" fuse is blown. The primary and secondary image container set are both in the User Area, and BOOT_PARTITION_ENABLE =7. 3. In this scenario, the "eMMC fast boot" fuse is not blown. The boot mode is Normal Boot, and the primary and secondary image container set are both in the User Area. 4. In this scenario, the "eMMC fast boot" fuse is not blown. The boot mode is Normal Boot, and the primary and secondary image container set are both in the boot partitions, and BOOT_PARTITION_ENABLE = 1 or 2. Re: i.MX 8M Plus LPDDR4 EVK - enabling eMMC boot0/boot1 Thanks for the pointer — though I believe chapter 5.8.2.2.1 describes a different chip family. The "SCU ROM" eMMC boot flow is specific to the i.MX8QuadMax/QuadXPlus/DualXPlus, which have a dedicated System Controller Unit (separate Cortex-M4 boot subsystem). The i.MX8M Plus has no SCU — its boot ROM runs directly on a Cortex-A53 — so the BOOT_PARTITION_ENABLE=1/2/7 scenarios in that chapter don't apply here. For i.MX8M Plus, redundancy appears to be handled via the Primary/Secondary Image mechanism in the i.MX8M Plus Reference Manual (Figure 6-1): the ROM boots from the device selected by BT_FUSE_SEL/BOOT_CFG, and on failure falls back to a Secondary Image at the IMG_CNTN_SET1_OFFSET fuse offset — on the same boot device, not a separate boot0/boot1 partition. This matches what I'm seeing on the LPDDR4 EVK: BOOT_PARTITION_ENABLE=1 is set in EXT_CSD, but the ROM ignores it and boots from the raw user-area offset regardless. So my questions remain, scoped to i.MX8M Plus: 1. Is there any non-efuse way on the LPDDR4 EVK (jumper, resistor, or undocumented SW1101/SW4 position) to select eMMC boot0/boot1 as the boot source, or is that purely a BOOT_CFG strap/BT_FUSE_SEL decision? 2. Are the BOOT_CFG fuse banks independent of the SRK-hash fuses for HAB, or does committing to BOOT_CFG-via-fuse also force HAB closure? 3. For a custom board design, what BOOT_CFG strapping is needed at layout time to keep hardware boot-partition redundancy available without a later fuse commitment? Happy to be corrected if I'm misreading which part chapter 5.8.2.2.1 actually applies to. Re: i.MX 8M Plus LPDDR4 EVK - enabling eMMC boot0/boot1 The fuses bits between Boot CFG and SRK Hash are separable. It seems there is the extra boot step needed if the SRK Hash burned, which is comparing the hash values from your boot image and fuse bits burned. Re: i.MX 8M Plus LPDDR4 EVK - enabling eMMC boot0/boot1 Thanks for your information. Does IMX8MMEVKBHUG i.MX 8M Mini LPDDR4 EVKB Board Hardware User's Guide provide any useful information, Boot mode and Boot device configurations chapter? Re: i.MX 8M Plus LPDDR4 EVK - enabling eMMC boot0/boot1 You can refer to the https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/iMX-secondary-boot-collection/ta-p/1916915 i.MX8MP eMMC Secondary Boot.zip These demos and articles cover more advanced secondary boot scenarios, but they also include the basics—such as how to write the bootloader to Boot 1 or Boot 2, and how to enable Boot 1 or Boot 2. These should be exactly what you need. i.MX8MP_emmc_boot_part_secondary_boot.uuu FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} ${part} 0 boot 1 FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 boot 2 FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 2 0 i.MX8MP_emmc_boot_part_secondary_boot.uuu uuu_version 1.2.39
SDPS: boot -f imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk-LF_v6.6.3-1.0.0
SDPV: delay 1000
SDPV: write -f imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk-LF_v6.6.3-1.0.0 -skipspl
SDPV: jump
#FB: ucmd setenv emmc_dev 1
FB: ucmd setenv part 1
FB: ucmd setenv boot_offset 0x0
FB: ucmd setenv fastboot_dev mmc
FB: ucmd setenv mmcdev ${emmc_dev}
FB: ucmd if test ${part} != 7; then mmc dev ${emmc_dev} ${part}; else mmc dev ${emmc_dev}; fi
FB: ucmd setenv fastboot_buffer ${loadaddr}
FB: download -f imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk-LF_v5.15.71-2.2.0
#FB: download -f imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk-LF_v6.6.3-1.0.0
FB: ucmd echo ${fastboot_bytes}
FB: ucmd setexpr blks ${fastboot_bytes} / 0x200; setexpr blks ${blks} + 1
FB: ucmd mmc write ${loadaddr} ${boot_offset} ${blks}
# Secondary boot
FB: ucmd setenv part 2
FB: ucmd if test ${part} != 7; then mmc dev ${emmc_dev} ${part}; else mmc dev ${emmc_dev}; fi
#FB: download -f imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk-LF_v5.15.71-2.2.0
FB: download -f imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk-LF_v6.6.3-1.0.0
FB: ucmd echo ${fastboot_bytes}
FB: ucmd setexpr blks ${fastboot_bytes} / 0x200; setexpr blks ${blks} + 1
FB: ucmd mmc write ${loadaddr} ${boot_offset} ${blks}
FB: ucmd setenv part 1
FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi;
FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} ${part} 0
FB: done
View full article
