MCTPTX1AK324 + CAN-FD 500/5000 Hi, I am currently working with two different development boards: S32K312EVB-Q172  and MCTPTX1AK324 I am trying to communicate with those at CAN-FD 500/5000 kbps. To calculate the bit timings I am using the CAN Bit Timing calculation v2.1.xlsm provided by NXP. For the S32K312 at CAN Clk 60MHz with the TJA1043TKY this is working fine. But on the other board with the S32K324 at CAN Clk 80MHz and the TJA1044GT I always get Bus errors when I try to set the FD rate higher than 4mbps. The TJA1044 is supposed to work up to 5mbps. What could be the problem there? I am using a short (30cm) untwisted cable to connect an IXXAT USB-to-CAN FD compact with an additional 120 Ohm resistor. 500/4000, 1000/4000 work fine, but as soon as I go up to 500/5000 or 1000/5000 FD frames result in errors. Here is an example of a bit timing calculation that I tried (I think I tested all possible configurations) Any suggestions? Thanks & best regards, grol Re: MCTPTX1AK324 + CAN-FD 500/5000 Hi Petr, I have found the TDC setting (I must have been blind before...): With this enabled and set according to the calbulator it works fine. Thanks for your support! Best regards, grol Re: MCTPTX1AK324 + CAN-FD 500/5000 Hi, you wrote messages sent from the IXXAT are read correctly by the controller, but registers show error during reception and IXXAT shows detected error during transmission. Can be CAN bit timing issue. Also be sure both have ISO CANFD protocol used. For transmission on MCU side a TDC must be definitely enabled with proper TDCOFF set. Not sure for EB but in S32DS CT this is available in FdBaudrateConfig setting   BR, Petr Re: MCTPTX1AK324 + CAN-FD 500/5000 I forgot to mention: messages sent from the IXXAT are read correctly by the controller Re: MCTPTX1AK324 + CAN-FD 500/5000 Hi @PetrS, Thanks for the quick reply. Do you really use enhanced CAN FD timing and registers as shown in pictures? Yes, but I also tried with normal mode settings, with the same result (works up to 4mbps). Did you set TDC as well? Check the setting in debugger. TDC is disabled according to the debugger. This is an AUTOSAR project (SW. Version: 4.0.0 P14_HF01_D2406), the FlexCan is configured in Tresos, is the TDC configurable there? What errors are detected on S32K324? Check ECR, ESR1 registers. Here is the top part of the FlexCAN in the debugger showing some errors: The IXXAT on the other end (there are no other nodes) reports the following: And is configured with the same sample point: A recommendation could be to measure TXD/RXD/CAN lines with scope to see real signals. I don't have a scope available right now, but could probably organize one for next week or so. Any more ideas what I could try until then? Thanks! Best regards, grol Re: MCTPTX1AK324 + CAN-FD 500/5000 Hi, all connected nodes should use same bitrate and sample times, so ensure that. Do you really use enhanced CAN FD timing and registers as shown in pictures? Did you set TDC as well? Check the setting in debugger. What errors are detected on S32K324? Check ECR, ESR1 registers. A recommendation could be to measure TXD/RXD/CAN lines with scope to see real signals. BR, Petr

iMX93 A核M核无法同时激活 我使用make SOC=iMX9 REV=A1 flash_singleboot_m33命令将flash.bin编译到芯片中。在uboot阶段，M core的调试口有打印信息，但是进入linux系统之后，M core的调试口没有打印信息。 回复：iMX93 A核M核无法同时激活 参考用户指南，请将参数“clk_ignore_unused”添加到 uboot bootargs 中，如下所示 “setenv mmcargs'setenv bootargs ${jh_clk} console= ${console} root= ${mmcroot} clk_ignore_unused”

iMX93 Aコア Mコアは同時にアクティブ化できません make SOC=iMX9 REV=A1 flash_singleboot_m33コマンドを使用して、flash.binをチップにコンパイルします。uboot フェーズでは、M コアのデバッグ ポートには情報が印刷されていますが、Linux システムに入った後、M コアのデバッグ ポートには情報が印刷されません。 Re:iMX93AコアMコアは同時にアクティブ化できません ユーザーガイドを参照して、次のようにパラメータ「clk_ignore_unused」をubootbootargsに追加してください "setenv mmcargs 'setenv bootargs ${jh_clk} console=${console} root=${mmcroot} clk_ignore_unused"

MPC5646C RAM read using BAM Hi, I am trying to read the internal RAM using the BAM module, via the UART The problem is that there is a repeating pattern in the received file, that doesn't look correct. This is the code i am using. #define RAM_BASE 0x40000000 #define RAM_SIZE 256*1024 #define RAM_END RAM_BASE + RAM_SIZE int main(void) { int32_t i = 0, r = 0; uint32_t word = 0x00; InitHW(); InitializeUART(kBaud500000); /* Start the other core */ SSCM.DPMBOOT.R = (unsigned long)__start_p1; SSCM.DPMKEY.R = (unsigned long)0x00005AF0; SSCM.DPMKEY.R = (unsigned long)0x0000A50F; for (;;) { for (i = RAM_BASE; i < RAM_END; i+= 4) { word = *(uint32_t*) i; uart_print_int(word); } delay_100ms(1); } } the pattern i am getting is: 00 00 20 7E 04 00 00 00 20 4E 04 00 00 00 10 0E 00 00 00 00 00 00 04 00 00 03 30 00 04 00 00 09 F0 DC 0F F0 F5 00 00 00 04 00 00 00 50 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 02 60 00 00 00 00 00 70 CA 04 00 00 09 F0 D0 04 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 20 7E 04 00 00 00 20 4E 04 00 00 00 10 0E 00 00 00 00 00 00 04 00 00 03 30 00 04 00 00 09 F0 DC 0F F0 F5 00 00 00 04 00 00 00 50 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 02 60 80 00 00 00 00 70 CA 04 00 00 09 F0 D0 04 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 20 7E 04 00 00 00 20 4E 04 00 00 00 10 0E 00 00 00 00 00 00 04 00 00 03 30 00 04 00 00 09 F0 DC 0F F0 F5 00 00 00 04 00 00 00 50 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 02 70 00 00 00 00 00 70 CA 04 00 00 09 F0 D0 04 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 20 7E 04 00 00 00 20 4E 04 00 00 00 10 0E 00 00 00 00 00 00 04 00 00 03 30 00 04 00 00 09 F0 DC 0F F0 F5 00 00 00 04 00 00 00 50 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 02 70 80 00 00 00 00 70 CA 04 00 00 09 F0 D0 04 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 20 7E 04 00 00 00 20 4E 04 00 00 00 10 0E 00 00 00 00 00 00 04 00 00 03 30 00 04 00 00 09 F0 DC 0F F0 F5 00 00 00 04 00 00 00 50 F0 00 00 Is this supposed to be normal, or i am getting something wrong. Its a new processor, an empty one, isn't it supposed to be empty. Re: MPC5646C RAM read using BAM Hi @BorisB  RAM memory contains random data after power on. It must be initialized:  It's done in startup code like this: stmw instruction is used - it writes all GPR core registers to RAM in a loop. That's the reason why you can see such pattern in the RAM. Regards, Lukas

RT685 duty cycle changes during I3C communication Hi @kerryzhou  according to the frequency configuration shown in below picture. the duty should be 50%. push-pull hign is 40ns  push pull low is also 40ns. but I find the actual duty cycle is not  always 50% in push-pull mode, somrtimes it is 75%. you could check the below timing capture.push-pull hign is 60ns  push pull low is also 20ns. could you please explain this duty cycle changing phenomenon? Thanks Best Regards, Melanie  Re: RT685 duty cycle changes during I3C communication HI Kerry, Thanks for your suggestion. It is difficult to capture timing sequence by Oscilloscope. Re: RT685 duty cycle changes during I3C communication Hi @melanie ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.    From your test result picture, it is from the logic analyzer, please also use the Oscilloscope  to test the I3C wave, whether still find the duty change issues? As in the logic analyzer, some interference in the signal bus may also influence the test result, then, oscilloscope will be the true result.    Please check it again with oscilloscope, thanks.    If you still have issues about it, please kindly let me know. Best Regards, Kerry

LPC5536 SDK 2.15.100 Ladies and Gentlemen, I'd like to inform You, that something is wrong with the SDK for LPC5536. Version 2.15.100 (today the newest) doesn't compile, when I create a whole new C project in MCUXpresso. I saw some error message during project creation, but I didn't make a screenshot. After the project succesfully created, there's a "virgin" source code which doesn't compile. Some includes are missing: stdio.h, pin_mux.h, LPC5536.h. Excuse me, I'm focusing on my own project, I couldn't make a deeper study to this failure. I tried to construct a new project more times, and I saw always the same symptom. With 2.14, it is OK, everything works properly. LPC55xx Re: LPC5536 SDK 2.15.100 Hello @Bela1  Thanks for your reporting. I created a new project based on MCUXpressso IDE v11.9.0, SDK2.15. Not find the issue after compile. I attached the steps. BR Alice

S32K344-How to get the wakeup source Hello I use S32K344 to test the wakeup function. I configured two wakeup sources: RTC and Port. How can I get the wakeup source? BestRegards, Simon Re: S32K344-How to get the wakeup source Hi @Simon-Liu., You can use the EIF of WISR and WISR_64 to distinguish which one is causing it. Refer to the following community post, where an example from the Low Power Management demos were tested: Solved: S32K3 how can I get wake-up source - NXP Community. The chapter 48.1.4 (WKPU wake-up source connectivity) from the S32K3xx's Reference Manual goes over the wake-up source mapping to WKPU. Best regards, Julián

S32M244 pflash 0x0-0x10无法读取/擦写/编程 芯片型号为S32M244，在某次尝试用jlink烧录报错后，后续无法对sector0进行擦除烧写，尝试对flash内容进行整片回读也出错，最后按照存储段的形式去读取，发现0x10之后的内容可以正常读取，仅从0x0开始的16个字节进行读取时会报错 上图为尝试烧录但是因不明原因失败时报的错误，后续可以连接芯片，但是无法再次烧录 检查内核状态发现内核处于halted状态，此时尝试回读flash，发现除了0x0-0x10之外的地址范围都可以正常读取，一旦尝试从0x00000000开始读取flash就会报错 我想请教一下： 1.可能是什么原因导致这种情况，连续尝试烧录3块板子都出现了这个问题 2.出现这个问题是否有恢复的方法 Re: S32M244 pflash 0x0-0x10无法读取/擦写/编程 Hi@Helloyt 我建议你不要再对新的板子进行相同的尝试了，从你的描述上来看，这可能是你的调试接口电路，调试器可能存在问题，至少在S32K244上，这块地址没有什么限制。 我也尝试使用J-Flash V9.6K进行了几次回读和写入，我在我们的EVB上没有这样的问题。 如果是硬件的损坏，这可能无法回复，但是先排查下你们的调试接口电路，你们的J-LINK，如果有别的调试器可以进行一些新的尝试。  

NT3H2111 Capability Container byte2, LAST_NDEF_BLOCK How should they be configured       1. The range of LAST_NDEF_BLOCK is from 1h to 37h, and the corresponding NFC page range is from 4h to DCh. Based on the given information, the calculated byte size is D9 * 4. This means that from the starting page to the last page corresponding to LAST_NDEF_BLOCK, the entire data area contains D9 NFC pages (each NFC page is 4 bytes) 2. According to NFC Forum Type 2 Tag specification, the value of byte 2 of the CC multiplied by 8 equals the data area byte size. the data area byte size as D9 * 4  (D9 * 4) / 8 = 217 / 2 = 108.5. As byte 2 of the CC is an 8 - bit data (1 byte), its value should be an integer.  it becomes 108 in decimal, and converting it to hexadecimal gives 6C. So, according to the specification, the CC should be set to  :Byte0:0xe1 , Byte1:0x10  Byte2:0x6c Byte3:0x00  right？ 回复： NT3H2111 Capability Container byte2, LAST_NDEF_BLOCK How should they be configured   I found out why: the NDEF data area contains data in non-NDEF format   回复： NT3H2111 Capability Container byte2, LAST_NDEF_BLOCK How should they be configured after set CC and LAST_NDEF_BLOCK the session bytes FEh: 0~7 byte value: 0, 0x37, 0xf8, 0x48, 0x8, 0x1, 0x0, 0x0 the i2c block0 0~15 value:  0x4, 0xa9, 0x35, 0x12, 0xf0, 0x71, 0x80, 0x0, 0x44, 0x0, 0x0, 0x0, 0xe1, 0x10, 0x6c, 0x0 Not clear why the TagInfo cannot detect NDEF information   

LPC55S28-EVK b2b I2C communication Dear all, I'm using LPC55S28-EVK configured as slave to receive I2C data coming from master. I'm using SDK example i2c_interrupt_b2b_transfer_slave. It works but I don't know how to detect if received data is write or read command. As you know I2C read or write command depends on the LSB of address. How to tetect it ? Thank you very much for your help and cooperation regards Re: LPC55S28-EVK b2b I2C communication Hi @Marconi_  In I2C protocol, the LSB of the address byte is used to determine whether the command is a read or write operation. If the LSB is 0, it's a write operation; if it's 1, it's a read operation. When you receive an interrupt indicating that data has been received, you can check the LSB of the address byte to determine whether it's a read or write operation. Here's a simple example: void I2C0_IRQHandler(void) { // Address match event occurred uint8_t address = I2C0->ADDR; // Check the LSB to determine read (1) or write (0) if (address & 0x01) { // Read command (LSB is 1) // Perform actions for read command } else { // Write command (LSB is 0) // Perform actions for write command } } Hope this will help you. BR Hang

LPC55S28-EVK b2b I2C通信 皆様、 マスターからのI2Cデータを受信するためのスレーブとして構成されたLPC55S28-EVKを使用しています。 私はSDKの例のi2c_interrupt_b2b_transfer_slaveを使用しています。 それは動作しますが、受信したデータが書き込みコマンドか読み取りコマンドかを検出する方法がわかりません。 ご存知のように、I2Cの読み取りまたは書き込みコマンドはアドレスのLSBに依存します。それをどのようにテテクトしますか? ご協力いただき、誠にありがとうございました よろしくお願いします。

LPC55S28-EVK b2b I2C通信 尊敬的各位， 我正在使用配置为从机的 LPC55S28-EVK 来接收来自主机的 I2C 数据。 我正在使用 SDK 示例 i2c_interrupt_b2b_transfer_slave。 它可以工作，但我不知道如何检测接收到的数据是写入命令还是读取命令。 如您所知，I2C 读取或写入命令取决于地址的 LSB。如何检测它？ 非常感谢您的帮助和合作 此致问候

从 SPI NOR 闪存中的其他位置启动 T1022 大家好， 我有一个定制的 T1022 子板，其中处理器从存储在 SPI NOR Flash 中的 uboot 启动。我计划在所述 NOR 闪存中存储多个 uboot，以便处理器根据安装该子板的母板启动。所以我的问题是： 1）可以这样做吗？（目前我已经尝试在不同位置之间复制 uboot，但是速度太慢了） 2) 根据.cmm文件中，uboot总是存储在位置0，这是为什么呢？我们可以将这个位置改变到某个地方，以便它向用户询问 uboot 的位置吗？ 欢迎就此提出任何建议。 感谢并致意 苏维克 回复：从 SPI NOR 闪存中的其他位置启动 T1022 不客气。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 好的。谢谢你的帮助。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 因为您必须从 IFC NOR 获取不同的 RCW，所以您必须操纵通向 IFC NOR 的地址线。示例 - IFC NOR 分为多个虚拟银行，并且我们选择特定银行有其逻辑。您可以为此浏览一次硬件设计指南。因此，您需要一个 CPLD 或一个外部控制器来切换 IFC NOR 中的存储体。因此，PBL 可以使用该逻辑获取不同银行中存在的不同 RCW。所以这需要修改硬件设计。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 正在调查。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 好的 。谢谢。我明白了方法。 最后一个问题。我们如何确保 PBL 从 IFC NOR 的不同位置获取？我找不到任何可以设置获取位置的字段。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 您想更改子板的 gpio 和 serdes 配置吗？那么您必须在子板的 IFC NOR 上保留 3 个不同的 RCW。 RCW 由 PBL 获取。Uboot 比 PBL 阶段晚，因此 Uboot 无法处理此问题 回复：从 SPI NOR 闪存中的其他位置启动 T1022 会回到你身边 回复：从 SPI NOR 闪存中的其他位置启动 T1022 在这种情况下，我们必须将 IFC NOR FLASH 保留在母板上，而不是子卡上。我说得对吗？ 如果我们将 NOR 闪存保留在子卡上，我们如何确保 RCW 从不同的分区加载？可以将分区位置写入存储在 SPI 闪存中的 uboot 上吗？ 回复：从 SPI NOR 闪存中的其他位置启动 T1022 因此，您需要的是：- RCW 具有 gpio 和 serdes 配置。因此，根据 3 个父卡的不同，您需要 3 个具有所需配置的不同 RCW。 上电复位时，PBL[预引导加载程序] 会从所需的非易失性源（IFC NOR、eSDHC、NAND 闪存）之一获取此 RCW，并加载此配置。一种可能的解决方案是使用 IFC NOR 作为源。 IFC NOR 将在 3 个不同的内存分区中存在 3 个不同的 RCW。 父卡必须设计成 当子板连接到父卡 A 时，RCW 将从 IFC NOR 中的分区 A 获取。 当子板连接到父卡 B 时，RCW 将从 IFC NOR 中的分区 B 获取。 第三张家长卡也是如此。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 将与 AE 团队讨论。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 当您说“您可以使用该特定的 DTB 加载映像”时，您的意思是父卡保留各自的 DTB，并在处理器启动时加载存储在父卡中的 DTB 吗？如果我的理解正确，那么如果 DTB 能够更改 SERDES 配置，这可能是一种可行的解决方案。 就我而言，考虑一个父卡 A，其中我们需要 SRDS_PRTCL 为 0x86，另一个父卡 B，其中 SRDS_PRTCL 需要为 0x81，并且我们有一个单处理器子卡。我们如何确保处理器按照每个主板的 SRDS_PRTCL 启动。我认为，dtb 提取是在 uboot 执行后开始的。但我需要根据母卡更改 uboot。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 你能不能制作3个不同的设备树二进制文件，根据父卡的不同，分别配置不同的GPIO？这样，当需要时，你就可以用特定的DTB加载你的镜像了。 这 3 个父卡是由同一个应用处理器构建的吗？ 回复：从 SPI NOR 闪存中的其他位置启动 T1022 知道了。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 请参阅 AE 团队的以下更新。 关于 NOR 闪存中的多个 Uboot。您能否告诉我们更多关于为什么需要在 NOR 闪存中安装 2 个 Uboot 的要求？“处理器根据安装该子板的母板启动”——请详细说明。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 我已将此案例上报给 AE 团队，现在正在等待他们的反馈。 回复：从 SPI NOR 闪存中的其他位置启动 T1022 与 AE 团队讨论。

Libraries support options in DS Hi, I am trying to use print trace to debugger console with the function of printf in S32G-VNP-RDB3 project. Noticed that "newlib Debugger Console" should be chosen for the item of  Libraries support in Target Processer page. But in my project, there is such a option with console. What else should be set?  Re: Libraries support options in DS Got, thanks! Re: Libraries support options in DS Hi @Liuliyuan,  Thank you for contacting NXP Support. Based on the following community post Semihosting printf with S32G274A - NXP Community By now, "printf" using the S32 Debugger is an unsupported feature. Therefore, we suggest you use a UART interface to implement a "printf" capability. I hope this information will be helpful. Have a great day!

difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello ,  I was going through the Gold VIP user manual "GoldVIP-S32G3-1.11.0-User-Manual.pdf", Here i dnt understand the significance of GoldVIP Real-time Bootloader image (Slot A) (Slot B),or GoldVIP Real-time Gateway application image (Slot A) (Slot B). what are these different slots , i can see when this software is flashed to Nor flash it will be using Slot A in both the case .  I don't see anywhere the slot 2 is used what is the exact use case of this slot 2 Regards Karthik Mallya M GoldVIP Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello @Bio_TICFSL  Thank you for the response , To be clear my quetion is in current GoldVIP-S32G3-1.11.0 package ,is this space is in use or not ?, because even we will not load any application to this area while flashing  we are using only Slot A  i am asking becasue i am planning to use this area for other memory allocation like NvM area, before doing that i wanted to confirm Regards Karthik  Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello, There is no linker because we have no any example of it, but you can modify current linker file and add a memory through QSPI or a sensor, etc. Regards Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello @Bio_TICFSL , Could you Brief me what kind of application ,because I don't see any linker assignment for these slot Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello, The SLOT B it uses for application. Regards

SPI NORフラッシュの他の場所からT1022を起動する 皆さん、こんにちは。 私はカスタムT1022子ボードを持っており、プロセッサはSPI NORフラッシュに保存されているubootから起動します。上記のNORフラッシュに複数のubootを保存して、この子ボードがマウントされている親ボードに従ってプロセッサが起動するようにする予定です。だから私の質問は: 1) 可能ですか?(現在、場所間でubootをコピーしてみましたが、遅すぎます) 2) .cmm によるファイルの場合、uboot は常に 0 の場所に格納されます。それはどうしてですか。この場所をどこかで変更して、ユーザーにubootの場所を尋ねることはできますか? これに関する提案は大歓迎です。 よろしくお願いいたします。 スービック Re:SPI NORフラッシュの他の場所からT1022を起動します どういたしまして。 Re:SPI NORフラッシュの他の場所からT1022を起動します よろしくお願いします。 Re:SPI NORフラッシュの他の場所からT1022を起動します IFC NORとは異なるRCWをフェッチする必要があるため、IFC NORに向かうアドレス行を操作する必要があります。例 - IFC NORは仮想銀行に分割されており、特定の銀行を選択するためのロジックがあります。これについては、ハードウェア設計ガイドを一度確認できます。そのため、CPLDまたはIFC NORでバンクを切り替えるための外部コントローラーが必要になります。そのため、異なるバンクに存在する異なる RCW は、そのロジックを使用して PBL でフェッチできます。そのため、ハードウェア設計の変更が必要です。 Re:SPI NORフラッシュの他の場所からT1022を起動します 偵知。 Re:SPI NORフラッシュの他の場所からT1022を起動します わかりました。ありがとうございます。道筋がわかりました。 最後の質問。PBL が IFC NOR の別の場所からフェッチされるようにするには、どうすればよいですか?フェッチ場所を設定したフィールドが見つかりませんでした。 Re:SPI NORフラッシュの他の場所からT1022を起動します チャイルドボードのGPIOとSERDESの構成を変更したいですよね?次に、子ボードのIFC NORに3つの異なるRCWを保持する必要があります。 RCWはPBLによって取得されます。UbootはPBLステージより遅れて来るため、Ubootはこれを処理できません Re:SPI NORフラッシュの他の場所からT1022を起動します あなたに戻ってきます Re:SPI NORフラッシュの他の場所からT1022を起動します この場合、IFC NOR FLASHを子カードではなく親ボードに保持する必要があります。私は正しいですか? 代わりに子カードにNORフラッシュを保持している場合、RCWが異なるパーティションからロードされるようにするにはどうすればよいでしょうか。パーティションの場所は、SPIフラッシュに保存されているubootに書き込むことができますか? Re:SPI NORフラッシュの他の場所からT1022を起動します だからここにあなたが必要とするものがあります:- RCW には gpio と serdes の設定があります。したがって、3つの親カードに応じて、目的の構成を持つ3つの異なるRCWが必要です。 パワーオン リセット時に、PBL[Pre-bootloader] は、目的の不揮発性ソース [IFC NOR、eSDHC、NAND フラッシュ] の 1 つからこの RCW をフェッチし、このコンフィギュレーションをロードします。考えられる解決策の1つは、IFC NORをソースとして使用することです。 IFC NORには、3つの異なるメモリパーティションに3つの異なるRCWがあります。 親カードは、次のように設計する必要があります。 子ボードが親カードAに接続されている場合、RCWはIFC NORのパーティションAからフェッチされます。 子ボードが親カードBに接続されている場合、RCWはIFC NORのパーティションBからフェッチされます。 3枚目の親カードも同様です。 Re:SPI NORフラッシュの他の場所からT1022を起動します AEチームと話し合います。 Re:SPI NORフラッシュの他の場所からT1022を起動します 「その特定のdtbでイメージをロードできる」と言うとき、親カードはそれぞれのdtbを保持し、プロセッサが起動すると親カードに保存されているdtbをロードするということですか?私が理解したことが正しければ、dtbがserdesの設定を変更することができる場合、これは可能な解決策の代替手段になる可能性があります。 私の場合、親カードAがあり、SRDS_PRTCLが0x86である必要があり、別の親カードBがあり、SRDS_PRTCLが0x81する必要があり、プロセッサの子カードが1つあるとします。プロセッサが各ボードのSRDS_PRTCLsに従って起動することをどのように確認できますか。私の意見では、dtbのフェッチはubootが実行された後に開始されます。ただし、親カードに従ってubootを変更する必要があります。 Re:SPI NORフラッシュの他の場所からT1022を起動します 親カードによってGPIO構成が異なる3つの異なるデバイスツリーバイナリを作成することはできませんか?また、必要に応じて、その特定のdtbで画像をロードできます。 これらの3つの親カードは、同じアプリケーションプロセッサで構築されていますか? Re:SPI NORフラッシュの他の場所からT1022を起動します わかりました。 Re:SPI NORフラッシュの他の場所からT1022を起動します AEチームからの以下の最新情報をご参照ください。 NORフラッシュ内の複数のUbootについて。NORフラッシュに2つのUbootが必要な理由について、要件についてもう少し詳しく教えてください。「プロセッサは、この子ボードがマウントされている親ボードに従って起動します」 -- これについて詳しく教えてください。 Re:SPI NORフラッシュの他の場所からT1022を起動します 私はこのケースをAEチームにエスカレーションしましたので、今彼らからのフィードバックを待っています。 Re:SPI NORフラッシュの他の場所からT1022を起動します AEチームと話し合う。

Linker script section alignment exceeds memory region size (RTD, AR: 4.7.0, SW: 2.0.0) Hello, I have installed the S32DS v3.5.12 together with the latest RTD (AR: 4.7.0, SW: 2.0.0) for an S32k148 MCU. I have generated the FreeRTOS example project for the S32K148 MCU as shown in the image below. I have studied the Linker file linker_flash_s32k148.ld and think I found an error in the generated file. First, examine the memory definition. According to the file 1024 bytes are reserved for the interrupt table inside the flash memory and then additional 16 bytes for the flash configuration flags/bits, etc. MEMORY { int_flash_interrupts : ORIGIN = 0x00000000, LENGTH = 0x00000400 /* 1K */ /* Do not change this section */ int_flash_config : ORIGIN = 0x00000400, LENGTH = 0x00000010 /* 16bytes */ /* Do not change this section */ int_flash : ORIGIN = 0x00000410, LENGTH = 0x0017FBF0 /* ~1.5MB */ int_sram_results : ORIGIN = 0x1FFE0000, LENGTH = 0x00000100 /* 256bytes */ int_sram : ORIGIN = 0x1FFE0100, LENGTH = 0x0003DF00 /* ~248K */ int_sram_stack_c0 : ORIGIN = 0x2001E000, LENGTH = 0x00001000 /* 4K */ ram_rsvd2 : ORIGIN = 0x2001F000, LENGTH = 0 /* End of SRAM */ }  If you continue analyzing the section definition at the beginning SECTIONS { .flash_interrupts : { . = ALIGN(2048); __interrupts_rom_start = .; KEEP(*(.intc_vector)) . = ALIGN(4); __interrupts_rom_end = .; } > int_flash_interrupts you see that the memory region int_flash_interrupts, which has an assigned size of 1024 bytes contains a 2048 byte alignment instruction, which exceeds the defined region size. Am I correct? If not, can you explain, what I am missing here. Best regards, M_SCH S32 SDK for S32K1 Re: Linker script section alignment exceeds memory region size (RTD, AR: 4.7.0, SW: 2.0.0) Hi @M_SCH  The ALIGN(n) instructs the compiler to align a variable on an n-byte boundary starting from the ORIGIN address. This just limits the location of a memory region to a certain n-byte size, this should not interfere with other memory regions as the memory region size does not exceed the n-byte boundary. B.R. VaneB

Boot T1022 from other locations in SPI NOR flash Hello All, I have a custom T1022 child board wherein the processor boots up from the uboot stored in SPI NOR Flash. I am planning to store multiple uboot(s) in the said NOR flash so that the processor boots up according to the parent board in which this child board is mounted. So my questions are: 1) Is it possible to do so? (Currently I have tried copying uboot between locations, but it is too slow) 2) As per the .cmm file, the uboot is always stored at location 0. Why is that? Can we change this location somewhere so that it asks the user for the uboot location? Any suggestions regarding this is welcome. Thanks and Regards, Souvik Re: Boot T1022 from other locations in SPI NOR flash You are welcome. Re: Boot T1022 from other locations in SPI NOR flash Ok. Thank you for your help. Re: Boot T1022 from other locations in SPI NOR flash Because you have to fetch different RCW from IFC NOR, you would have to manipulate the address lines going towards the IFC NOR. Example - IFC NOR is divided into virtual banks, and there is a logic with which we select a particular bank. you can go through the hardware design guide once for this. So you would need either a CPLD or an external controller that lets you switch the banks in the IFC NOR. So that different RCW present in different banks can be fetched by the PBL using that logic. So this needs a hardware design modification. Re: Boot T1022 from other locations in SPI NOR flash Investigating. Re: Boot T1022 from other locations in SPI NOR flash Ok . Thank you. I understood the way. Last question. How can we ensure that PBL fetches from a different location of the IFC NOR? I couldn't find any field wherein we set the fetching location. Re: Boot T1022 from other locations in SPI NOR flash you want to change the gpio and serdes configuration of child board right ? then you have to keep 3 different RCW on IFC NOR of child board. RCW is fetched by the PBL. Uboot comes later than the PBL stage so Uboot will not be able to handle this Re: Boot T1022 from other locations in SPI NOR flash Will back to you Re: Boot T1022 from other locations in SPI NOR flash In this case, we have to keep the IFC NOR FLASH on the parent boards instead of the child card. Am I correct? If we keep the NOR flash on the child card instead, how can we ensure that the RCW loads from different partitions? Can the partition locations be written on the uboot stored in SPI flash? Re: Boot T1022 from other locations in SPI NOR flash So here's what you would need :- RCW has the gpio and serdes configuration. So depending upon the 3 parent cards, you need 3 different RCW having the desired configuration. At power-on reset, PBL[Pre-bootloader] fetches this RCW from one of the desired non-volatile sources[IFC NOR, eSDHC,NAND flash] and loads this configuration. One of the possible solutions is to use IFC NOR as a source. IFC NOR would have 3 different RCWs present in 3 different memory partitions. The parent card has to be designed in such a way that when the child board is connected to Parent card A, the RCW gets fetched from partition A in the IFC NOR. when the child board is connected to Parent card B, the RCW gets fetched from partition B in the IFC NOR. similarly for the third Parent card. Re: Boot T1022 from other locations in SPI NOR flash Will discuss with the AE team. Re: Boot T1022 from other locations in SPI NOR flash When you say "you could load your image with that specific dtb.", do you mean that the parent cards keep their respective dtbs and when the processor boots up it loads the dtb stored in the parent card? If what I have understood is correct, this could be a possible solution alternative if the dtb is able to change the serdes configuration. In my case, consider a parent card A wherein we need the SRDS_PRTCL to be 0x86 and another parent card B wherein the SRDS_PRTCL is required to be 0x81 and we have a single processor child card. How can we ensure that the processor boots up as per the SRDS_PRTCLs for each board. In my opinion, dtb fetching starts after uboot has executed. But I need the uboot to be changed as per the parent card. Re: Boot T1022 from other locations in SPI NOR flash Can you not make 3 different device tree binaries that will have different gpio configurations depending upon the parent card? And when needed, you could load your image with that specific dtb. these 3 parent cards are built out of same application processor? Re: Boot T1022 from other locations in SPI NOR flash Got it. Re: Boot T1022 from other locations in SPI NOR flash Hello, I have designed a T processor child card. Currently, I have 3 different parent cards onto which this child card is to be mounted. Now, these 3 cards have different SRDS_PRTCL, different GPIO configurations, etc. I was thinking if we could by any change have a card-dependent boot-up instead of programming uboot multiple times whenever we change the parent board. Hence the requirement. Hope I am clear in my requirement. Thanks, Souvik Re: Boot T1022 from other locations in SPI NOR flash Please refer to the following update from the AE team. Regarding multiple Uboot(s) in the NOR flash. Can you please tell us a bit more about the requirement as to why you would need 2 Uboot in the NOR flash? "the processor boots up according to the parent board in which this child board is mounted" -- please elaborate on this. Re: Boot T1022 from other locations in SPI NOR flash I have escalated this case to the AE team, am waiting for the feedback from them now. Re: Boot T1022 from other locations in SPI NOR flash Hello, Any help with this?  Re: Boot T1022 from other locations in SPI NOR flash Discussing with the AE team.

カーネルドライバのIIO ADCサンプルコード S32G2 のカーネル ドライバーを使用して、いくつかの IIO ADC 入力チャネルを設定しようとしています。私が従うことができる例があるかもしれないと思っていましたか? 「include / linux / iio」ディレクトリの下の消費者機能を使用してADCのチャネルを要求および設定する必要があるかどうかわかりませんか?チャンネルが設定されると、 ポーリングまたは割り込みを通じて定期的に値をキャプチャし、その値をsysfsドライバーノードに書き込む必要があります。 なお、NXPコミュニティフォーラムやカーネルドキュメント(カーネルバージョン5.15)には、S32Gの例が見つかりませんでした。 どんな援助もありがとう。 Re:カーネルドライバのIIO ADCサンプルコード 提案に従って、NXPの「s32cc_adc.c」のADCコードの一部を実装することにしましたLinuxドライバーを新しいドライバーに。 Re:カーネルドライバのIIO ADCサンプルコード BSP 39.0 とカスタム ボードを使用しています。 また、いくつかのドキュメントを見ると、iio_channelを取得するには、確立されたiio_mapが必要ですか?iio_mapはすでにYoctoで生成されていますか、それともボードのdtsファイルで設定する必要があるものですか?

内核驱动程序的 IIO ADC 示例代码 我正在尝试通过 S32G2 上的内核驱动程序设置多个 IIO ADC 输入通道。我想知道是否有一个我可以效仿的例子？ 我不确定是否需要使用“include/linux/iio”目录下的消费者功能来请求和设置 ADC 的通道？一旦建立频道， 我希望通过轮询或中断定期捕获值，然后将这些值写入我的 sysfs 驱动程序节点。 请注意，我在任何 NXP 社区论坛或内核文档（内核版本 5.15）中都找不到 S32G 的任何示例。 感谢您的帮助。 回复：内核驱动程序的 IIO ADC 示例代码 根据建议，我决定从 NXP 的“s32cc_adc.c”中实现一些 ADC 代码Linux 驱动程序合并到我的新驱动程序中。 回复：内核驱动程序的 IIO ADC 示例代码 我正在使用带有定制板的 BSP 39.0。 另外，查看一些文档，为了获得 iio_channel，需要建立 iio_map？iio_map 是否已在 Yocto 中生成，或者这是否需要在 board dts 文件中设置？