S32K3 RTD5.0.0 lpi2c hello! Recently, I updated RTD4.0.0 to 5.0.0, then got problem. In Lpi2c configure page, "I2C Clock Source" don't contains any value.(in RTD4.0.0 it works ok) the RTD error is : Source clock is not enabled in Clock component is that a bug ? or something I didn't configure? 回复： S32K3 RTD5.0.0 lpi2c Hi@Vandarkholme Please add"Clock_Ip_ReferencePoints" and then try again. 回复： S32K3 RTD5.0.0 lpi2c oh, I add clockReference then it worked! In RTD5.0.0 clockReference is key component? RTD4.0.0 not need to configure that component

Difference between EIM and FCCU NCFF Hello, I'm currently learning on how to work with some safety concepts on the S32K344-Q257EVB, namely the FCCU, and i wanted to test it and see how it reacts to faults (in terms of changing states in the Finite State Machine (FSM) and checking the FCCU1/FCCU2 signals with an oscilloscope to see if they get asserted or not). My question is, how should i do that? On the reference manual i have read that the FCCU has some Non-Critical Fault Fake (NCFF) that could be used to achieve that, but there is also an Error Injection Module (EIM) and that is where my confusion begins. What is the difference between both? In which cases should i use one and/instead of the other? Thanks in advance! Best regards, JRodrigues Re: Difference between EIM and FCCU NCFF Hello Peter, Thanks for the clarification. Have a good rest of your day! Best Regards, JRodrigues Re: Difference between EIM and FCCU NCFF Hello, the NCFF referring to "All SRAM ECC uncorrectable error ERM_SRAM or ECC cache memory error.." can act as a fault that "happened in the memory and was then reported to the FCCU"? NCFF will inject the fault only to FCCU fail state machine (FSM). So you can verify the reaction of device in case such fault will come to FCCU. But NCFF will not inject the ECC error physically to ECC mechanism nor to the memory. For such purpose you will you EIM. So if you want to verify the reaction of ECC and reaction path on error in ECC mechanism to FCCU NCFSx, you will need to use EIM. Best regards, Peter Re: Difference between EIM and FCCU NCFF Hi Peter, So, in the S32K3xx_fault_map excel file that comes with the reference manual, the NCFF referring to "All SRAM ECC uncorrectable error ERM_SRAM or ECC cache memory error.." can act as a fault that "happened in the memory and was then reported to the FCCU"? Best Regards, JRodrigues Re: Difference between EIM and FCCU NCFF Hello, You can use for EOUT tests NCFF which can inject the faults to the FCCU. Usually you use it when you want to verify the FCCU reaction on incoming fault. It however cant physically inject fault to peripherals/ memories. In some cases there is inejction dirrectly on tested peripheral or FCCU can inject fault only to the status register like STCU_ERR and not in the test itself. However EIM: The Error Injection Module (EIM) is mainly used for diagnostic purposes. It provides a method for diagnostic coverage of internal memories (for example, system RAM, cache RAMs, and peripheral memories). EIM enables you to induce artificial errors on error-checking mechanisms of a system, such as ECC for RAM read data and parity bits. So EIM will create a physical fault on memory and memory then reports fault to FCCU. This way you can test for example if your ECC mechanism is working correctly, etc... Best regards, Peter

i.MX7 Solo LCD信号とピン配置 ご列席の皆様、 私はここのような同様の問題を抱えています: https://community.nxp.com/t5/i-MX-Processors/i-MX7-LCD-Pinout/m-p/1599101 しかし、私の質問は24ビット幅のLCDインターフェースです。 データシート ( IMX7SCEC Rev. 7, 09/2023 ) にもリファレンス マニュアル ( IMX7SRM Rev. 0.1, 08/2016 ) にも、どのピンが信号 R[0], R[1] に属しているかがわかりません。G[0]、G[1]、....B[0]、...[7]。 この情報は、HW回路を設計するために不可欠です。 ここでは、信号は次のようになります。 LCD_DATA[00-07] = B[0-7] LCD_DATA[08-15]=G[0-7] LCD_DATA[16-23]=R[0-7] ? つまり、LCD_DATA[00] = B0, LCD_DATA[01]= B1, ....そしてLCD_DATA[22]=R6、LCD_DATA23=R7、それぞれです。私は正しいですか? これらの信号とそのピン配置の具体的な宣言は、ドキュメントのどこで確認できますか。   日時:i.MX7ソロLCD信号とピン配置 こんにちは はい、その通りです。 LCD_DATA[00-07] = B[0-7] LCD_DATA[08-15]=G[0-7] LCD_DATA[16-23]=R[0-7]  これについては、i.MX7D Sabreの回路図を参照してください。 よろしくお願いします/サルドス、 アルド。

EB：如何在EB中设置优先级分组？ 当我在平台模块中使能Isr的时候，发现最大优先级只能到15，如果优先级设置的大于15的话，EB就会报优先级超出范围的错误。我怎样才能将优先级设置为大于 15？我想知道是否可以在EB中设置优先级组。 这里我使用s32k344和RTD 4.0.0.0

EB 生成コード: modules.h の Marco use_Gpt_moduleSTD_ONに変更することはできません EBにGPT、basenxp、platform、resource、その他のモジュールを追加し、コードを生成した後、Marcoがmodules.hをuse_Gpt_moduleしていることがわかりました。STD_ONに変更することはできません。このマルコをSTD_ONに変更する方法は? 回复: EB 生成コード: Marco use_Gpt_module of modules.hSTD_ONに変更することはできません ここではs32k344を使用しています。

IMXRT685-AUD-EVK debugging issue with JLink it is the first time i use IMXRT685-AUD-EVK, i meet two issues blocking in setup stage by following the Tutorial steps. First Issue: when debugging the example, error message popups as followng snapshot: Spoiler (Highlight to read) the logs from output is captured in attached text file: MCUxpresso_err.txt the logs from output is captured in attached text file: MCUxpresso_err.txt The environment and versions of IDE is as following list: MCUXpressoIDE: 24.9.25 JLink: V810 (installed with MCUXpressoIDE) Windows 10 Pro x64 22H2 Second Issue: failed when use xt-ocd to connect EVB through JLink, "Error: SWD Wait time-out expired!" printed. the template topology.xml is from here , and the modified version (with my serial number) is in attached whole log is as following: Ubuntu 22.04: edmond@ed-ubuntu:/opt/Tensilica/xocd-14.11$ ./xt-ocd -c ./topology.xml XOCD 14.11 2023-04-06 14:43:30 (c) 1999-2024 Cadence Design Systems Inc. All rights reserved. [Debug Log 2024-10-31 10:12:33] Loading module "gdbstub" v2.0.0.12 Loading module "jlink" v2.0.2.0 Using JLINK lib v.69600 Jlink USB Serial Number: 722949484 Connected to Jlink Device: Name:'J-Link LPCXpresso V2 compiled May 2 2023 17:39:56' S/N:722949484 Firmware: J-Link LPCXpresso V2 compiled May 2 2023 17:39:56 Requested/Set TCK: 1000kHz/65534kHz Jlink: Select pipelined SWD SWD-DP with ID 0x6BA02477 Loading module "jtag" v2.0.0.20 Loading module "xtensa" v2.0.0.48 Starting thread 'GDBStub' Listening for GDB connection on port 20000 Initialize XDM driver Error: SWD Wait time-out expired! SWD-DP with ID 0x6BA02477 SWD-DP with ID 0x6BA02477 SWD-DP with ID 0x6BA02477 SWD-DP with ID 0x6BA02477 Error: XDM initialization failed ERROR: Couldn't initialize, exit... other logs from Win11: PS C:\Program Files (x86)\Tensilica\Xtensa OCD Daemon 14.07> .\xt-ocd.exe -c .\topology.xml XOCD 14.07 2021-06-01 19:00:49 (c) 1999-2024 Cadence Design Systems Inc. All rights reserved. [Debug Log 2024-10-30 16:35:38] Loading module "gdbstub" v2.0.0.12 Loading module "jlink" v2.0.2.0 Using JLINK lib v.69600 Jlink USB Serial Number: 722949484 Connected to Jlink Device: Name:'J-Link LPCXpresso V2 compiled May 2 2023 17:39:56' S/N:722949484 Firmware: J-Link LPCXpresso V2 compiled May 2 2023 17:39:56 Requested/Set TCK: 1000kHz/65534kHz Jlink: Select SWD SWD-DP with ID 0x6BA02477 Loading module "jtag" v2.0.0.20 Loading module "xtensa" v2.0.0.48 Starting thread 'GDBStub' Opened GDB socket at port 20000 Initialize XDM driver Error: SWD Wait time-out expired! SWD-DP with ID 0x6BA02477 SWD-DP with ID 0x6BA02477 SWD-DP with ID 0x6BA02477 SWD-DP with ID 0x6BA02477 Error: XDM initialization failed ERROR: Couldn't initialize, exit... Have tried different combination with OS, xtensa ocd versions and JLink versions: Win10, Win11 and Ubuntu 22.04 xtensa ocd version: 14.07, 14.08, 14.11 JLink version: V810, V810C, V696(in another topic, this version fixed similar error, but not mine) Also checked the jumps as default: i.MXRT 600 Re: IMXRT685-AUD-EVK debugging issue with JLink Thanks! @mayliu1  It can work after i upload a hello world demo with DSP enabled through IDE (mimxrt685audevk_dsp_hello_world_usart_cm33) The xt-ocd can connect to DSP now. So I guess that because i bought a new board which was burned with the factory default image (without DSP enabled), but I want to debug DSP directly and ignore running IDE demo in toturial video, then it causes the communication failure. Just an advice to add a tip in guide document that to run hello world with DSP first then to try debugging DSP. Thank you again for your kindly support and your time! That's really helpful to me. Re: IMXRT685-AUD-EVK debugging issue with JLink Hi @e_matthews , Hi , I 'm glade that your project " hello world example" from SDK is well debugging through JLink. Question1: Does it mean JLink connecting to CPU is OK on IDE? Answer: Yes,  If you can debugging, It means CPU is OK on IDE. Question2: But JLink connection from xt-ocd still doen't work, it always show "Error: SWD Wait time-out expired!". Does it mean DSP still not work? Answer:  To reduce power consumption, The DSP core will do not power on  when the RT600 boots. If you want debug a DSP code, the RT600 Arm kernel need execute some code . For the detail description, you can refer to the guide sheet. Wish it helps you. If you still have question about it, please kindly let me know. If your question is solved, please tell me to close this case, thanks. Best Regards mayliu Re: IMXRT685-AUD-EVK debugging issue with JLink Dear @mayliu1  Thank you for advices. For 1, JLink firmware is updated with guide, log as: For 2, JLink commander connection is verified: For 3, hello world example from SDK is well debugging through JLink: Does it mean JLink connecting to CPU is OK on IDE? But JLink connection from xt-ocd still doen't work, it always show "Error: SWD Wait time-out expired!". Does it mean DSP still not work? Best Regards! Edmond Re: IMXRT685-AUD-EVK debugging issue with JLink Hi @e_matthews ， Hi, I have consulted with a RT600 series expert. He give some advices. 1: Please pay attention to the "Getting Started with Xplorer for EVK-MIMXRT685". The path of the "Getting Started with Xplorer for EVK-MIMXRT685" file is in XXX\SDK_2_16_000_EVK-MIMXRT685\docs. Especially, check  chapter 2.6 "2.6 Program LPC-Link2 with SEGGER J-Link", and update JLINK firmware. 2: Try to use J-link-commander to connect the board, whether It can connected. 3: Try to use MCUXpresso IDE create a simple project "mimxrt685audevk_hello_world" , using JLINK to debug, whether the project can run normally. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu Re: IMXRT685-AUD-EVK debugging issue with JLink Thanks! @mayliu For 1, the "./" means the current path, just inditate where's the topology exist. It should be the same if without it. For 2, i double checked the usbser ID which I used, it was correct and was retrieved from JLink log print as tortuial: 722949484 if I typed the wrong ID, the log was like the following instead of what i've got: Re: IMXRT685-AUD-EVK debugging issue with JLink Dear @e_matthews , I use MIMXRT685-EVK debug, It is similar to  MIMXRT685-AUD-EVK. 1: Please make sure that modify usbser ID in  topology.xml file according to your JLINK. 2: the command is xt-ocd.exe -c topology.xml,  but I see your command is xt-ocd.exe -c .\topology.xml.   Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu Re: IMXRT685-AUD-EVK debugging issue with JLink Dear @mayliu, Thank you for your kindly advice, I will follow your guide to check the toturial from the correct link. On the other hand, I double checked the wrong link that I jumped in: https://www.nxp.com.cn/document/guide/getting-started-with-imxrt685-aud-evk-development-platform:GS-MIMXRT685-AUD-EVK?section=plug-it-in  the only difference between two links: mine is "www.nxp.com.cn" and the video content in the first section are different: And then checking for the SDK version, what i used was for MIMXRT685-AUD-EVK as following: I also rebuild the SDK from the new link. The new downloaded SDK package are identical with my old one: Thank you again for replying! But there is still issue No.2 blocking, and it is not related with SDK. Only Jlink and xt-ocd are involved. Re: IMXRT685-AUD-EVK debugging issue with JLink Dear @e_matthews , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. Please tell me your SDK information, It must be consistent to your Board. From image you post I know your board is MIMXRT685-AUD EVK board , so you should import MIMXRT685-AUD-EVK SDK, not MIMXRT685-EVK SDK, It is very import. Also, I suggest you can refer to this link https://www.nxp.com/document/guide/getting-started-with-imxrt685-aud-evk-development-platform:GS-MIMXRT685-AUD-EVK Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu

HSE FW install for S32K310 i want to install HSE FW to S32K310, based on HSE install demo downloaded from the website, can i just modify the flash configuration in the link command file according to the S32K310? and also want to confirm, is S32K310 using the same HSE FW as S32K311? please provide some detailed guidance about how to modify the reference demo Re: HSE FW install for S32K310 Hi Lukas     you are right , some variables is defined in DTCM    we managed to move them to Sram no cacheable and it works now    Thanks!  Re: HSE FW install for S32K310 Hi Leo, one more thing - it may be caused by DTCM. If data objects used for communication with HSE are located in DTCM, make sure that this switch is turned on: It ensures that DTCM address is translated to DTCM Backdoor address by Crypto driver. That's because HSE cannot see normal DTCM address. Regards, Lukas Re: HSE FW install for S32K310 Hi Leo, 1. What is the frequency of HSE_CLK? If it is configured to 120MHz, try to decrease it to 60MHz. https://community.nxp.com/t5/S32K/HSE-provides-RSP-NOT-SUPPORTED-response/m-p/1712323/highlight/true#M26508 2. Try to disable data cache memory. All the data objects used for communication with HSE must be forced to non-cacheable memory. 3. The S32K3 reference manual says: "Before configuring HSE_CLK, you must wait for the SBAF to enter WFI by reading core status register of HSE CPU (PRTN0_CORE2_STAT)." So, it’s necessary to wait for WFI bit before running clock initialization. I found out that current RTD drivers do not check WFI bit. This was a few months time ago and I can see that this should be included in the drivers in RTD version 5.0.0 and higher. 4. What is the content of HSE GPR register at 0x4039_C028? What is the content of FSR and GSR registers in MU_0? Regards, Lukas Re: HSE FW install for S32K310 Hi Lukas      thank you very much for your reply!     indeed i can read the HSE FW version after i download the project     and the HSE_STATUS_INIT_OK flag is set every time when initialize the HW     however when try to use the Crypto driver    and HSE is not responding to the request, what could be the potential cause of it? Re: HSE FW install for S32K310 Hi @LeoYang-  I usually recommend to create new project directly for used derivative and then port the code. However, I believe that this project will work just with the changes you did. Used features are the same on both derivatives. Yes, the firmware support both S32K310 and S32K311: Regards, Lukas

カスタム RT1170 B で XIP ブート モードを FLEXSPI1 から FLEXSPI2 に変更した後のデバッグ モードの問題 NXPサポートチームの皆さん、こんにちは。 RT1170をベースにしたカスタムボードを使用しており、XIPブートモードをFLEXSPI1からFLEXSPI2に切り替えました。この変更を行った後、次のような必要なすべての変更が適用されたことを確認しました。 ピン配置の調整: FLEXSPI2に関連するすべてのピン構成を更新しました。 周波数設定: XIP の適切なクロック周波数で FLEXSPI2 を設定します。 追加の周辺機器構成:リファレンスマニュアルに記載されているすべての周辺機器とメモリの構成を確認。 問題点: リリース・モードではシステムは正常に動作しますが、 デバッグ・モードを使用できません。FLEXSPI2 からブートすると、デバッグが期待どおりに初期化されません。 FLEXSPI2 に切り替えた後にこのモードに影響を与える可能性のある、デバッグに固有の追加の構成または設定はありますか? この変更の影響を受ける可能性のあるメモリ マップ、クロック セットアップ、またはデバッグ インターフェイスの追加の設定、構成、または特定の領域についてアドバイスをいただけますか。デバッグ機能を適応させるために何が必要かについてのガイダンスをいただければ幸いです。 ご支援いただきありがとうございます i.MXRT 106倍

i.MX7 Solo LCD signals and pinout Ladies and Gentlemen, I have a similar problem like the one here: https://community.nxp.com/t5/i-MX-Processors/i-MX7-LCD-Pinout/m-p/1599101 But, my question is with 24 bit wide LCD interface. I cannot find neither in the datasheet ( IMX7SCEC Rev. 7, 09/2023 ), nor in the reference manual ( IMX7SRM Rev. 0.1, 08/2016 ), which pins belongs to signals R[0], R[1], .... G[0], G[1], .... B[0], ... B[7]. This information is essential to design a HW circuit. Shall I estimate, that the signals are as follows here: LCD_DATA[00-07] = B[0-7] LCD_DATA[08-15]=G[0-7] LCD_DATA[16-23]=R[0-7] ? I mean LCD_DATA[00] = B0, LCD_DATA[01]= B1, .... and LCD_DATA[22]=R6, LCD_DATA23=R7, correspondingly. Am I correct? Where can I find a concrete declaration of these signals and their pinout in the documentation?   Re: i.MX7 Solo LCD signals and pinout Hello, Yes, it is correct that way: LCD_DATA[00-07] = B[0-7] LCD_DATA[08-15]=G[0-7] LCD_DATA[16-23]=R[0-7]  You may refer to the i.MX7D Sabre schematic for this. Best regards/Saludos, Aldo.

i.MX7 Solo LCD 信号和引脚排列 女士们，先生们， 我有一个类似的问题，例如： https://community.nxp.com/t5/i-MX-Processors/i-MX7-LCD-Pinout/mp/1599101 但是，我的问题是关于 24 位宽的 LCD 接口。 我在数据表（ IMX7SCEC Rev. 7, 09/2023 ）和参考手册（ IMX7SRM Rev. 0.1, 08/2016 ）中都找不到哪些引脚属于信号 R[0]、R[1]、.... G[0]、G[1]、.... B[0]、... B[7]。 这些信息对于设计硬件电路至关重要。 我估计这里的信号如下： LCD_DATA[00-07] = B[0-7] LCD_DATA[08-15]=G[0-7] LCD_DATA[16-23]=R[0-7]？ 我的意思是 LCD_DATA[00] = B0，LCD_DATA[01]= B1，.... 并且 LCD_DATA[22]=R6，LCD_DATA23=R7，分别对应。我说得对吗？ 在文档中哪里可以找到这些信号及其引脚排列的具体声明？   回复：i.MX7 Solo LCD 信号和引脚排列 你好， 是的，这样是正确的： LCD_DATA[00-07] = B[0-7] LCD_DATA[08-15]=G[0-7] LCD_DATA[16-23]=R[0-7] 您可以参考 i.MX7D Sabre 示意图。 致以最诚挚的问候/问候， 阿尔多。

在定制 RT1170 B 上将 XIP 启动模式从 FLEXSPI1 更改为 FLEXSPI2 后，调试模式出现问题 您好，NXP 支持团队， 我正在使用基于 RT1170 的定制板，并进行了以下修改：我将 XIP 启动模式从 FLEXSPI1 切换到 FLEXSPI2。做出此更改后，我确保应用了所有必要的修改，包括： 引脚排列调整：更新了 FLEXSPI2 的所有相关引脚配置。 频率设置：使用适合 XIP 的时钟频率设置 FLEXSPI2。 附加外围设备配置：验证参考手册中概述的所有外围设备和内存配置。 问题： 虽然系统在发布模式下运行正常，但我无法使用调试模式。从 FLEXSPI2 启动时，调试未按预期初始化。 切换到 FLEXSPI2 后，是否有任何特定于调试的附加配置或设置可能会影响此模式？ 您能否就可能受此更改影响的内存映射、时钟设置或调试接口中的任何其他设置、配置或特定区域提供建议？我们将非常感激任何有关调整调试功能所需的指导。 感谢您的支持 i.MXRT 106x

NX3DV221 I/O Hello, Could you confirm if the NX3DV221 analog mux can handle both single-ended and differential signals? The datasheet doesn’t seem to specify this detail. Thank you! Re: NX3DV221 I/O Hello Antonino, Yes, the NX3DV221 may handle both single-ended and differential signals. BRs, Tomas

S32G2 LINUX-BSP and SJA1110 Hello,         I can‘t clearly understand the  SPI communication between S32G274A and SJA1110：         1、What is the DSA driver? If I enable it, then SJA1110 is an external module, it is the driver outof DTS tree for SJA1110?         2、where is the source code of DSA driver?  Is it here: https://github.com/nxp-archive/autoivnsw_sja1110_linux/tree/master , if it is not, what is this code in github for SJA1110?            then in this code, I find that it check if the sja1110's devtype is SJA1110_SWITCH, where to set this devtype, in the DTS file? /** * Write a given value to a given register of the switch * sja1110->devtype needs to be SJA1110_SWITCH */ static u32 sja1110_write_reg(struct sja1110_priv *sja1110, u32 reg_addr, u32 val) {        3、There is only sja1110.ko in Linux bsp as default, I want to visit the interface "sja1110_write_reg" provided by  https://github.com/nxp-archive/autoivnsw_sja1110_linux/tree/master/sja1110_init.c  to config sja1110 ,   what should I do? GoldVIP Re: S32G2 LINUX-BSP and SJA1110 Hello,         Thank you for your reply, I don't have question now. Re: S32G2 LINUX-BSP and SJA1110 Hello @yangjinzhuang Perfect, let me know if you have any other question from the S32G side. Best regards, Alejandro Re: S32G2 LINUX-BSP and SJA1110 Hello,        Thank you for your reply, I will go to the  Other-NXP-Products forum, I had the NDA. Re: S32G2 LINUX-BSP and SJA1110 Hello @yangjinzhuang, All your questions are specific to the SJA1110 chip, this is outside of my scope and the S32G forum scope. Please post your questions in the Other-NXP-Products forum. On it, one of my collogues should be able to help you with everything related to the SJA1110. Please be aware that the documentation related to the SJA1110 and its SDK requires signing a NDA, for this you can contact your FAE/NXP representative. Let me know if you have more questions related to the S32G products. Best regards, Alejandro Re: S32G2 LINUX-BSP and SJA1110 Hello,        1、can you give me the command to config SJA1110's port mode after DSA driver is loaded?       2、I see that SJA1110 has SPI_HOST and SPI_AP host access point,  I also see there are SWITCH_CONTROL_INTERNAL and SWITCH_CONTROL_SPI mode in SDK. In my understand that now, the DSA driver has no relationship with SJA1110's SPI mode and access point, is it right?       3、what is the relationship with SPI_HOST/SPI_AP and SWITCH_CONTROL_INTERNAL/SWITCH_CONTROL_SPI? Does it set SPI_HOST with  SWITCH_CONTROL_INTERNAL  at the same time?Does it set SPI_AP with  SWITCH_CONTROL_SPI at the same time?       4、If I set SPI_AP, the external host controller must be other SJA1110? Can the external controller be S32G274A? The design is S32G274A----SPI----SJA1110 in GLDBOX hardware. I am not sure if S32G274A can access SJA1110 through SPI on SPI_AP interface as an external host controller. Re: S32G2 LINUX-BSP and SJA1110 Hello,         Thanks for your reply, I still want to know how to config SJA1110 and SPI commands here: https://community.nxp.com/t5/Other-NXP-Products/bd-p/other  Re: S32G2 LINUX-BSP and SJA1110 Hello @yangjinzhuang, Here are my answers to your questions: 1 - Yes, that is the aim of the DSA driver. 2 - Yes, you can check the compatibility in https://docs.kernel.org/networking/dsa/sja1105.html  3 - Sorry, I made a mistake. The .c, .o and .ko you mention, refer the out of tree driver mentioned before, this is loaded at boot time. This is the driver that handles the configuration loading while the DSA driver handles the switch functionality. The information for BSP35 is the following [page 60, Linux BSP 35.0 User Manual for S32G2 platforms, 19-Jan-2023]: Please also check section 7.7 Setting up SJA1110 switch. If you have specific questions about the SJA1110 configuration and SPI commands, please post it here: https://community.nxp.com/t5/Other-NXP-Products/bd-p/other  Let me know if this information answers your questions. Re: S32G2 LINUX-BSP and SJA1110 Hello,         The sja1110_init.c and build result in Linux-BSP project path is as follows: AUTO_YOCTO_BSP/build_s32g274ardb2/tmp/work/s32g274ardb2-linux/sha1110/1.0-r0/git/sja1110_init.c  AUTO_YOCTO_BSP/build_s32g274ardb2/tmp/work/s32g274ardb2-linux/sha1110/1.0-r0/git/sja1110.o AUTO_YOCTO_BSP/build_s32g274ardb2/tmp/work/s32g274ardb2-linux/sha1110/1.0-r0/git/sja1110.ko   Re: S32G2 LINUX-BSP and SJA1110 Hello,          Thanks for your reply, my Linux-bsp version is 35.0 and switch chip is SJA1110.          1、Does DSA driver support config switch's port mode(ingress/egress)?          2、Does SJA1110's DSA driver provide same functions with SJA1105 in Linux-bsp UM?          3、I build Linux-bsp 35.0 on Ubuntu，I can find the source code as follows in the 35.0 project https://github.com/nxp-archive/autoivnsw_sja1110_linux/tree/master/sja1110_init.c, then I can also see the build result of sja1110.o and sj1110.ko in the same path, they are built from sja1110_init.c, which is as same as  https://github.com/nxp-archive/autoivnsw_sja1110_linux/tree/master/sja1110_init.c, I can't understand this with your answer before. Re: S32G2 LINUX-BSP and SJA1110 Hello @yangjinzhuang  here are my answers to your questions: 1 - There might be a small confusion on the term "out-of-tree Linux kernel module", it does not refer to the device tree, instead it means the following [article]: the behavior is the following  [page 62, Linux BSP 41.0 User Manual for S32G2 platforms]: the description above is related to a simple configuration loader, not the DSA driver. The DSA (Distributed Switch Architecture) driver behaves as described below [page 62]: 2 - You can find the code in: https://github.com/nxp-auto-linux/linux/tree/release/bsp41.0-5.15.153-rt/drivers/net/dsa/sja1105 3 - the code you shared, as you can see in the name of the repo, is archived, it is no longer supported as you can see in the compatible linux versions: Furthermore I was not able to find any reference to S32G chip family in the repo. I used the BSP41 as an example, if you need details about another version let me know and also let me know if you have more questions about this topic. Re: S32G2 LINUX-BSP and SJA1110 Hello @yangjinzhuang, I will start to analyze your questions and come back to you when I have a relevant update. I appreciate your patience.  Best regards, Alejandro

EB生成的代码：Marco use_Gpt_module modules.h无法更改为 STD_ON 我在EB中添加了GPT、basenxp、platform、resource等模块，然后生成代码后发现modules.h中的Marco use_Gpt_module无法更改为 STD_ON。如何将此宏更改为 STD_ON？ 回复：EB生成的代码：Marco use_Gpt_module modules.h无法更改为 STD_ON 这里我用的是s32k344。

Issue with Debugging Mode After Changing XIP Boot Mode from FLEXSPI1 to FLEXSPI2 on Custom RT1170 B Hello NXP Support Team, I am working with a custom board based on the RT1170 and have made the following modification: I switched the XIP boot mode from FLEXSPI1 to FLEXSPI2. After making this change, I ensured that all necessary modifications were applied, including: Pinout Adjustments: Updated all relevant pin configurations for FLEXSPI2. Frequency Settings: Set up FLEXSPI2 with the appropriate clock frequency for XIP. Additional Peripheral Configurations: Verified all peripheral and memory configurations as outlined in the reference manual. Issue: While the system operates correctly in release mode, I am unable to use debugging mode. Debugging does not initialize as expected when booting from FLEXSPI2. Is there any additional configuration or setting specific to debugging that could be impacting this mode after switching to FLEXSPI2? Could you advise on any additional settings, configurations, or specific areas in the memory map, clock setup, or debugging interface that might be impacted by this change? Any guidance on what might be necessary to adapt the debugging functionality would be greatly appreciated. Thank you for your support i.MXRT 106x Re: Issue with Debugging Mode After Changing XIP Boot Mode from FLEXSPI1 to FLEXSPI2 on Custom RT117 Dear @yosri_c , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM  This link is MIMXRT1170 reference manual. Please pay attention to chapter 10 System Boot 1: Please check the Flash location in your project configuration. FlexSPI2: 0x60000000 FlexSPI1:  0x30000000 , this is for the NXP MIMXRT1170-EVKB board. 2: Please check BOOT config  and BOOT mode pin setting in your board.    Those PINs setting should be consistent to your project design. 3: I suggest you can import SDK demo "evkbmimxrt1170_fsl_romapi_cm7" , set Link application to RAM, modify relative configuration from FlexSPI1 to FlexSPI2, debug and check whether FLEXSPI2 NOR flash work OK.  I think this link is very useful for FLEXSPI Booting, you can refer to. https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/i-MX-RT-FLEXSPI-booting-guide/ta-p/1669262 Also,  maybe you can refer to this case, this case is also about FLEXSPI2. https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Problems-with-FlexSPI2-on-i-MX-RT1172-and-QSPI-flash/m-p/1716545 Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! mayliu

EB generated code: Marco use_Gpt_module of modules.h can not change to STD_ON I added GPT, basenxp, platform, resource and other modules in EB, then after I generated code I found that Marco use_Gpt_module of modules.h can not change to STD_ON. How to change this marco to STD_ON? Re: EB generated code: Marco use_Gpt_module of modules.h can not change to STD_ON Hi Sorry, this is a known bug and will be fixed in a future release. If you want an immediate solution you will have to create a static version of the modules.h header file(remove all the generation code and just set directly to STD_ON or STD_OFF each of the USE_EXAMPLE_MODULE you are interested in). Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- 回复： EB generated code: Marco use_Gpt_module of modules.h can not change to STD_ON Here I use s32k344.

EB: EB で優先度のグループ化を設定する方法は? プラットフォームモジュールで Isr を有効にすると、最大優先度が 15 までしか見つかりませんでしたが、優先度が 15 より大きいに設定されている場合、EB は優先度が範囲外であるというエラーを報告します。優先度を 15 より大きく設定するにはどうすればよいですか?そして、EBで優先グループを設定できるかどうか知りたいです。 ここでは、s32k344とRTD 4.0.0.0を使用しています

EB: how to setting priority grouping in EB? When I enable Isr in platform module, then I found the maximum priority only up to 15, if the priority is set to greater than 15, then EB will report a error that the priority out of range. how can I set the priority greater than 15? And I want to know whether I can set the priority group in EB. Here I use s32k344 and RTD 4.0.0.0 Re: EB: how to setting priority grouping in EB? Hi @vivid_  In the S32K3xx Reference Manual, it is stated that there are 16 priority levels configurable in 4 bits in IRQn fields in NVIC IPRn registers. According to NVIC_SetPriority(), the 4 less significant bits in IRQn fields in NVIC IPRn registers are not implemented. Whith the above information, the Table 4-18 (Priority grouping) of the ARM Cortex-M7 Devices Generic User Guide, can be understood in this way: In addition, about priority grouping, a function is also provided, see the following image. BR, VaneB

IMXRT1170-EVK how-to configure multicore project use of BOARD_SDRAM I am finding most of the single core cm7 projects are loading code into BOARD_SDRAM (which is large) in multicore projects no BOARD_SDRAM is initialized and code is loaded into SRAM_DTC_cm7, though the required shared memory is initialized: What would be the best way to combine these two memory layouts so that I might utilize the much larger BOARD_SDRAM for my code while still retaining shared memory layout between the CM7/CM4? What files need to be updated/configurations in MCUXpresso IDE, as I'm seeing most of the link/map files are auto-generated? Re: IMXRT1170-EVK how-to configure multicore project use of BOARD_SDRAM Thanks for the response Omar.  That's not exactly what I was asking.  I tried a few different memory layouts and was able to find one that was acceptable and worked after setting the XIP_BOOT_HEADER_DCD_ENABLE=1.  Without that the system would hardfault and I would have to recover using the MCU Boot Utility.  I found some explanation of the flag in this application note: https://www.nxp.com/docs/en/nxp/application-notes/AN12183.pdf Re: IMXRT1170-EVK how-to configure multicore project use of BOARD_SDRAM Hello I hope you are well. You can use SDRAM to load code so CM4 fetch from there: How to move CM4 core project to SDRAM in RT1176 - NXP Community Most of the examples use TCM as it has the best performance as it is nearer to the core. Best regards, Omar

iMX RT1021 TCM and OCRAM allocation and issue Scenario: We have design, where firmware utilizes only IRAM. Our usage was within 128Kb utilizing 2 TCM banks (64K each). We have expanded the design and RAM usage increased above 128Kb. We had enabled OCRAM (128Kb)  in scatter loader file. .map file looks normal and memory is allotted. We are using standard MPU configuration given in example. ( is cached has play here? ) Issue: Application starts misbehaving when large memory buffer is allocated with new scatter loader file. Some of the functionalities partially fail, like File system, network etc. I have attached  map file generated with and without large buffer allocated in the program. Like to have suggestion on, what I am missing here and root cause for the issue. Thanks. i.MXRT 102x Re: iMX RT1021 TCM and OCRAM allocation and issue I bellevue we have found solution.  Let us close this case. Currently system is stable andmemory allocation is fine with fix i had made.  Further memory allocations are carefully monitored. Re: iMX RT1021 TCM and OCRAM allocation and issue Hi @harikrishnan_ch  My apologies for the delayed response and thank you for providing additional information.  By looking at your scatter file it seems that you are using LWIp stack, but what I do not know how is the large buffer related to the stack or how interacts with your application, so I could not reproduce your issue. Could you replicate this on a much simpler environment?  Let me know if you found something else that we could consider during this time.  Best regards,  Diego Re: iMX RT1021 TCM and OCRAM allocation and issue Hello Deigo,  Do you have any update on recreation of issue?  thanks  haric Re: iMX RT1021 TCM and OCRAM allocation and issue Hello Deigo,  But , after reading a bit of data sheet  and memory related application note.  I disabled only Data Cache in code.  /* Enable I cache and D cache */ //SCB_EnableDCache(); SCB_EnableICache(); Now the system functions properly. I do not see and un usual behaviour of program. Still, I like to knwo the root cause and why controller memory access behaves in such manner. thanks and regards haric Re: iMX RT1021 TCM and OCRAM allocation and issue Hello Diego, I use Keil and SDK version in reference with Keil is MIMXRT1021_DFP 12.1.0.  SDK is older version  I had attached .map file, there you could find typical use case where memory usage can be seen.  based on that you could create a test scenario. thanks and regards haric Re: iMX RT1021 TCM and OCRAM allocation and issue Hi @harikrishnan_ch  I understood, that you where first using the ITCM and DTMC ( 64 KB each) for your application. But then you also required the OCRAM ( 128 KB), so you started to use this memory. I have the i.MX RT1020 to work and SDK examples. Are you able to point me how I could replicate your issue with using an  SDK example as an starting point?  Are you using KEIL or IAR? What is your current SDK version? Cache could sometimes have an implication on system, application performance.  Best regards,  Diego