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RDDRONE-FMUK66ボードがデバイスマネージャーに表示されない - PuTTY接続に必要なヘルプ こんにちは!私はmicroUSB経由でラップトップに接続された RDDRONE-FMUK66 ボードで作業していますが、それに接続されているJLink Mini EDUが ユニバーサルシリアルバスコントローラーで認識されていても、デバイスマネージャーに表示されません。すべての物理接続を確認し、さまざまなケーブルとUSBポートを試し、ボードに関連するドライバーをインストールし、SEGGER J-Linkソフトウェアを使用してテストしましたが、成功しませんでした。私の目標はPuTTYを介してボードに接続することですが、COMポートとしてリストされていません。どなたか同様の問題に遭遇した方や、ボードをシリアルポートとして表示させる方法についてのご提案をお持ちの方がいらっしゃいましたら、アドバイスをいただければ幸いです。感謝! 日時:RDDRONE-FMUK66ボードがデバイスマネージャーに表示されない - PuTTY接続に必要なヘルプ そう言っていただけると嬉しいです。新しい問題がある場合は、新しいスレッドを作成することを歓迎します。 日時:RDDRONE-FMUK66ボードがデバイスマネージャーに表示されない - PuTTY接続に必要なヘルプ ご回答いただき、誠にありがとうございました!しかし、ケーブルにも問題がありましたが、最終的にはそれを理解しました。
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RDDRONE-FMUK66 Board Not Showing in Device Manager - Help Needed for PuTTY Connection Hi! I’m working with an RDDRONE-FMUK66 board connected to my laptop via microUSB, but it doesn’t show up in Device Manager, even though the JLink Mini EDU connected to it is recognized under Universal Serial Bus Controllers. I’ve checked all physical connections, tried different cables and USB ports, installed any relevant drivers for the board, and tested it using SEGGER J-Link software, but with no success. My goal is to connect to the board through PuTTY, but it isn’t listed as a COM port. If anyone has experienced a similar issue or has suggestions on how to get the board to appear as a serial port, any advice would be greatly appreciated. Thanks! Re: RDDRONE-FMUK66 Board Not Showing in Device Manager - Help Needed for PuTTY Connection I'm glad to hear that. Any new issues, welcome to create the new thread. Re: RDDRONE-FMUK66 Board Not Showing in Device Manager - Help Needed for PuTTY Connection Thank you very much for the response! However, I also had an issue with a cable, but I eventually figured it out. Re: RDDRONE-FMUK66 Board Not Showing in Device Manager - Help Needed for PuTTY Connection Hello @Minodora27 , Thanks for posting this question in community.  The RDDRONE-FMUK66 board uses the Kinetis K66 chip, but is not a general-purpose MCU product. Its usage is different from that of other series of Kinetis products. I don't have this board right now. However, I've found some materials that I think can help you solve your problem. Product page: PX4 Robotic Drone VMU/FMU | NXP Semiconductors Under the Documentation section of the product page, there are many reference documents available. You can refer to Getting started using the RDDRONE-FMUK66 and Programming FMUK66 for first use  first. In addition, I have also sought more information from other colleagues. The source code and bootloader of RDDRONE-FMUK66 can be found as follows: https://nxp.gitbook.io/hovergames/downloads https://nxp.gitbook.io/hovergames/developerguide/building-firmware Hope the above information is helpful to you. Best Regards, Celeste
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S32K312 - Is there way to partition swap without running app ? Hello. I use S32K312 with AB SWAP HSE F/W, it is working well. I need to SWAP A ↔ B patrition without running application. Is it possible? For example, other MCU give me script for TRACE32 like below.     Best Regards, Sean Sung Re: S32K312 - Is there way to partition swap without running app ? Hello @lukaszadrapa  Thank you for reply. I'll try that. Best Regards, Sean Sung Re: S32K312 - Is there way to partition swap without running app ? Hi @ssean  Take a look at this post: https://community.nxp.com/t5/S32K/s32k3-flash-swap-requirements/m-p/1920123/highlight/true#M38475 I described there how to write minimalist code for AB swap. You can write very simple T32 script for this. Regards, Lukas
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Linux上のCodeWarrior studioのライセンスアクティベーションとインストール 皆さん、こんにちは LinuxベースのPCを使用しています。 CodeWarrior Studioライセンスをアクティブにしようとしています。ライセンスを持っていて、license.datとしてエクスポートしました。これをCW_ARMv8のインストールフォルダに配置しました。それは認識しているようです。ファイルを削除すると、「ライセンスが見つかりません」と表示されるためです。「ifconfig」で見つけたMACアドレスを入力しました。エラーは「LM_NOT_THIS_HOST」です。何が間違っているのですか? ありがとうございます! 日時:Linux上のCodeWarriorスタジオのライセンスアクティベーションとインストール ライセンスは nxp.com サイトから生成して、新しいMACアドレスで再度暗号化する必要があります。以下のビデオをご覧ください。 https://www.nxp.com/company/about-nxp/smarter-world-videos/HOW-TO-MOVE-YOUR-LICENSE
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PFE Master/Slave - Set up M7 Master Network Dear NXP fellows, This question is a sequel to my previous topic: Questions regarding multi-core networking in S32G399A  Right now, I have enabled PFE Master/Slave on our custom board based on S32G399A-RDB3 by appending pfe-slave to the Yocto distro-features: DISTRO_FEATURES:append = " pfe pfe-slave" This enables the PFE Slave to run on the A53 cores (Linux BSP). On the slave side, it seems to be working as expected, I can assign IP addresses to the three PFE interfaces and the ping is working from both sides. For your reference, the command libfci_cli phyif-print returns: DISCLAIMER: This is a DEMO application. It is not part of the production code deliverables. 0: emac0 ingress: 57 egress: 45 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: 00:04:9f:be:ef:00 33:33:00:00:00:01 01:00:5e:00:00:01 33:33:ff:be:ef:00 01:80:c2:00:00:00 01:80:c2:00:00:03 01:80:c2:00:00:0e 33:33:00:01:00:03 01:00:5e:00:00:fc mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 0: emac0 accepted: 57 rejected: 0 discarded: 0 processed: 57 egress: hif0 match-rules: --- 1: emac1 ingress: 75 egress: 53 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: 00:04:9f:be:ef:01 33:33:00:00:00:01 01:00:5e:00:00:01 33:33:ff:be:ef:01 mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 1: emac1 accepted: 75 rejected: 0 discarded: 0 processed: 75 egress: hif1 match-rules: --- 2: emac2 ingress: 13 egress: 37 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: 00:04:9f:be:ef:02 33:33:00:00:00:01 01:00:5e:00:00:01 33:33:ff:be:ef:02 01:80:c2:00:00:00 01:80:c2:00:00:03 01:80:c2:00:00:0e 01:00:5e:00:00:fc 33:33:00:01:00:03 mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 2: emac2 accepted: 13 rejected: 0 discarded: 0 processed: 13 egress: hif2 match-rules: --- 5: util ingress: 0 egress: 0 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: --- mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: --- 6: hif0 ingress: 105 egress: 57 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: --- mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 3: hif0 accepted: 29 rejected: 0 discarded: 0 processed: 29 egress: --- match-rules: --- 7: hif1 ingress: 53 egress: 75 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: --- mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 4: hif1 accepted: 0 rejected: 0 discarded: 0 processed: 0 egress: --- match-rules: --- 8: hif2 ingress: 37 egress: 13 discarded: 0 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: --- mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 5: hif2 accepted: 0 rejected: 0 discarded: 0 processed: 0 egress: --- match-rules: --- 9: hif3 ingress: 0 egress: 0 discarded: 31 malformed: 0 flexible-filter: --- ptp-mgmt-if: --- MAC: --- mirrors: rxmirr0: --- rxmirr1: --- txmirr0: --- txmirr1: --- logical interfaces: 6: hif3 accepted: 0 rejected: 0 discarded: 0 processed: 0 egress: --- match-rules: --- Command successfully executed.  and the command libfci_cli logif-print returns: DISCLAIMER: This is a DEMO application. It is not part of the production code deliverables. 0: emac0 accepted: 57 rejected: 0 discarded: 0 processed: 57 parent: emac0 egress: hif0 match-rules: --- 1: emac1 accepted: 75 rejected: 0 discarded: 0 processed: 75 parent: emac1 egress: hif1 match-rules: --- 2: emac2 accepted: 13 rejected: 0 discarded: 0 processed: 13 parent: emac2 egress: hif2 match-rules: --- 3: hif0 accepted: 29 rejected: 0 discarded: 0 processed: 29 parent: hif0 egress: --- match-rules: --- 4: hif1 accepted: 0 rejected: 0 discarded: 0 processed: 0 parent: hif1 egress: --- match-rules: --- 5: hif2 accepted: 0 rejected: 0 discarded: 0 processed: 0 parent: hif2 egress: --- match-rules: --- 6: hif3 accepted: 0 rejected: 0 discarded: 0 processed: 0 parent: hif3 egress: --- match-rules: --- Command successfully executed. However, I would like to configure the M7 core PFE-master now. My questions are: Can I assign an IP address to the PFE Master from the PFE Slave (BSP)? Do I need to use the EB Tresos PFE-DRV_S32G_M7_MCAL sample application for configuring the M7 core networking? Does it require to connect the S32G Debug Probe to the board in order to access the M7 core? Thank you for your support! Best regards, Guilherme Re: PFE Master/Slave - Set up M7 Master Network Hello @Joey_z , Ok, thank you very much. Best regards, Guilherme Re: PFE Master/Slave - Set up M7 Master Network hi,GuilhermeS32G Thank you for your reply. PFE MCAL driver does not have this function, thank you for your suggestion, I will report this problem. BR Joey Re: PFE Master/Slave - Set up M7 Master Network Hello @Joey_z , Thank you for your explanation. I can see that the latest releases of the S32G Real-Time Driver AUTOSAR 4.4 for Cortex-M7 can be configured, built, and debugged using the S32 Design Studio. However, the S32G PFE MCAL 4.4 driver still requires EB Tresos Studio. Is there any work in progress to make the future releases of the S32G PFE MCAL driver compatible with the S32 Design Studio? Thanks again. Best regards, Guilherme Re: PFE Master/Slave - Set up M7 Master Network hi,GuilhermeS32G It is recommended that you debug using Lauterbach Trace32 according to readme.txt requirements. The S32 Debug Probe can be debuggable by loading .elf files, but this is  unstable and does not ensure that you can debug successfully, you can see the following way. If the following problems occur, try loading the main.c file. BR Joey Re: PFE Master/Slave - Set up M7 Master Network Hello @Joey_z , Thank you for your reply. I see, so that means I require the Lauterbach Trace32 debugger and the EB Tresos Studio IDE for successfully running this example. Do you know if there is any movement inside NXP to migrate the PFE-DRV_S32G_M7_MCAL software to the S32 Design Studio IDE and supporting the S32 Debug Probe instead? Best regards, Guilherme Re: PFE Master/Slave - Set up M7 Master Network hi,GuilhermeS32G To configure PFE-master for M7 core, you can refer to the PFE-DRV_S32G_M7_MCAL package MasterProject_RDB3 project. In the meantime, you can refer to the readme for more details to complete the setup. You can set IP_ADDRESS_CTRL_0 to set the IP address . RTD drivers must be installed, copy the installed RTD driver plugins and PFE driver plugin to Tresos plugins directory. Also, Run and debug the application with Lauterbach TRACE32. BR Joey
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Linux 上 CodeWarrior Studio 的许可证激活和安装 大家好, 我正在使用基于 Linux 的个人电脑。 我正在尝试激活我的 CodeWarrior 工作室许可证。我有许可证并将其导出为 license.dat。我已将其放在 CW_ARMv8 的安装文件夹中。它似乎认识到了这一点。因为当我删除文件时它显示“未找到许可证”。我输入了通过“ifconfig”找到的mac地址。我收到的错误是“LM_NOT_THIS_HOST”。我做错了什么? 谢谢! 回复:Linux 上 CodeWarrior Studio 的许可证激活和安装 需要从 nxp.com 网站生成许可证,以便使用新的 MAC 地址再次加密,请观看以下视频: https://www.nxp.com/company/about-nxp/smarter-world-videos/HOW-TO-MOVE-YOUR-LICENSE
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License activation and installation for CodeWarrior studio on Linux Hi all, I am using a Linux based pc. I am trying to active my CodeWarrior studio license. I have a license and exported it as license.dat. I have placed this in the installation folder of CW_ARMv8. Which it seems to recognize. Because when I remove the file it says "license not found". I have entered my mac address which I find through "ifconfig". The error I get is "LM_NOT_THIS_HOST". What am I doing wrong? Thanks! Re: License activation and installation for CodeWarrior studio on Linux the license needs to be generated from nxp.com site so that it gets encrypted once more with the new MAC address please see the video below: https://www.nxp.com/company/about-nxp/smarter-world-videos/HOW-TO-MOVE-YOUR-LICENSE
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LS1046A DMA function Does the DMA controller on the LS1046 support a DMA chaining mode, where each link in the chain corresponds to a DMA descriptor, and after the chain is initialized and started, the DMA controller automatically completes all DMA operations in sequence? Re: LS1046A DMA function Yes, it supports this function. Re: LS1046A DMA function So if we follow the steps, LS1046 should support this function? Re: LS1046A DMA function So if we follow the steps, LS1046 should support this function? Re: LS1046A DMA function Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion. Please refer to "18.6.6 Channel Linking" in LS1046ARM.pdf for details.
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LS1046A DMA功能 LS1046 上的 DMA 控制器是否支持 DMA 链接模式,其中链中的每个链接对应一个 DMA 描述符,并且在链初始化和启动后,DMA 控制器会自动按顺序完成所有 DMA 操作? 回复:LS1046A DMA功能 是的,它支持这个功能。 回复:LS1046A DMA功能 那么如果我们按照这些步骤,LS1046应该支持这个功能吗? 回复:LS1046A DMA功能 那么如果我们按照这些步骤,LS1046应该支持这个功能吗? 回复:LS1046A DMA功能 通道链接(或链接)是一种机制,其中一个通道设置 另一个通道(或其自身)的 TCDn_CSR[START] 位,从而启动服务 请求该频道。当正确启用时,EDMA 引擎会自动 在主循环或次循环完成时执行此操作。 详情请参考LS1046ARM.pdf中的“18.6.6通道链接”。
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Encoding and Decoding simultaneously on i.MX8M Quad Hello, According to Datasheet, i.MX8M Quad supports 4K/60fps decoding, but There is no mention about encoding. Our function is video encoding and decoding simultaneously. Please let us know if i.MX8M Quad support it. Thank you. Best regards, Andy i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Encoding and Decoding simultaneously on i.MX8M Quad Hello,  Thanks for your prompt reply. Best regards, Andy Re: Encoding and Decoding simultaneously on i.MX8M Quad Hello, Yes the MX8MQ support encoding / decoding, but for encoding 4K 30fps. Regards
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S32K322割り込み PB17でEIRQ[31]を使用する必要がありますが、このPB17を外部割り込みとして設定する必要がある場合は、IMCR[559]を設定する必要がありますが、S32K322ではIMCR[409]までしかIMCRがありません。S32K322でIMCR[559]を設定するにはどうすればよいですか。 Re:S32K322割り込み こんにちは @danielmartynek、 ご支援のほどよろしくお願いいたします。
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Sending 4K Video via MIPI-DSI on IMX8M Quad Hello, I'd like to know if it is possible to send 4K video through DSI as the followings. "The datasheet indicates that using DSI achieves FHD 60fps, while HDMI achieves 4K 60fps. Is it possible to compress and transmit 4K video via the DSI interface using formats like DSC 1.2 or DSC 1.1?" Thank you. Best regards, Andy Re: Sending 4K Video via MIPI-DSI on IMX8M Quad Hello, Thanks for your confirmation. Best regards, Andy Re: Sending 4K Video via MIPI-DSI on IMX8M Quad Hello, Yes, is possible but you must get at 4k 30fps maximum for tx Regards
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CAN TX reset issue Hi NXP,     I need to operate CAN operation with Blocking mode to send data in faster rate. I have tried non blocking mode , there I have not faced any issue. Once I start using Blocking mode , COntroller will reset whenever I configure non zero value. FLEXCAN_DRV_SendBlocking(INST_FLEXCAN_CONFIG_1, E_MB_MSG_TX, &arrayMessageBufferInfo[E_MB_MSG_TX].rx_info, psCanFrameToSend->u32Identifier, psCanFrameToSend->au8Data, (uint32_t)10UL/* Found Timeout error and operate at 0 */); Here it works only with 0, For other Timeout configs it's resetting the board. Could you please help me out? It's failing in semaphore wait might. Which are all the configs I need to consider when I want to use blocking mode operation Re: CAN TX reset issue Hi@AbhiMR In the attachment, I have made sample codes for both non-blocking and blocking sending methods. You can test these two sample projects. If you have any questions or problems, you can point them out and I will help you reproduce and analyze it This is my test, you can send frame ID = 2 from PC to S32K116, S32K116 will send back the received frame counter and transmited frame counter. Re: CAN TX reset issue Hi NXP, Please find more details. Could you please share 8byte CAN TX operation example with attached setting. Need example in Blocking mode. Note: CAN TX not working in Blocking mode, it's not hitting any ISR. If not how to get SUCCESS notification? I have attached all CAN related configuration.  Re: CAN TX reset issue Hi NXP, I am sharing all my CAN config. Better if you can provide working example with 8byte TX payload.  Please refer the details that we elaborated more  In our application we have the following configuration, which are of initialization and run time operation to transmit the can frame. /*-------------------------------------------------INIT PART ---------------------------------------------------------------------------------------------------*/ flexcan_user_config_t flexcanInitConfig_500k = {   .flexcanMode = FLEXCAN_NORMAL_MODE,   .fd_enable = false,   .payload = FLEXCAN_PAYLOAD_SIZE_8,   .max_num_mb = 16UL,   .num_id_filters = FLEXCAN_RX_FIFO_ID_FILTERS_8,   .is_rx_fifo_needed = false,   .transfer_type = FLEXCAN_RXFIFO_USING_INTERRUPTS,   .rxFifoDMAChannel = 0U,   .pe_clock = FLEXCAN_CLK_SOURCE_OSC,   .bitrate = {     .propSeg = 7UL,     .phaseSeg1 = 4UL,     .phaseSeg2 = 1UL,     .preDivider = 1UL,     .rJumpwidth = 1UL   } }; FLEXCAN_DRV_Init(INST_FLEXCAN_CONFIG_1, &flexcanState0, &flexcanInitConfig_500k); /* Install callback function */ FLEXCAN_DRV_InstallEventCallback(INST_FLEXCAN_CONFIG_1, flexcanCallBack, NULL); FLEXCAN_DRV_InstallErrorCallback(INST_FLEXCAN_CONFIG_1, flexcanErrorCallBack, NULL); /*--------------------------------------------------INIT Completed --------------------------------------------------------------------------------------------*/ Non-Blocking Mode We have developed our application to transmit CAN frame at every 100ms. In non-blocking mode able to use FLEXCAN_DRV_Send method to transfer CAN Buffer , where we can get FLEXCAN_EVENT_TX_COMPLETE response in the above configured callback "flexcanCallBack". It behaves as expected. /*------------------------------ Runtime operation ----------------------------------------------*/   FLEXCAN_DRV_Send(INST_FLEXCAN_CONFIG_1, E_MB_MSG_TX, &arrayMessageBufferInfo[E_MB_MSG_TX].rx_info, psCanFrameToSend->u32Identifier, psCanFrameToSend->au8Data); /*------------------------------ Runtime operation ----------------------------------------------*/ In the above implementation we have drawback in transmission of frame at higher speed in non-blocking mode. Transmission is getting delayed whenever we have CAN request on the same time. Blocking mode Thought of trying blocking mode and facing the following issues With Timeout 0UL able to send the CAN frame with expected speed in our application without notifying success message. It will always return STATUS_TIMEOUT from blocking call.  We suspect not safer in implementation. /*-----------------------------------Runtime Operation -------------------------------------------------------------------*/ Returnvalue=FLEXCAN_DRV_SendBlocking(INST_FLEXCAN_CONFIG_1, E_MB_MSG_TX, &arrayMessageBufferInfo[E_MB_MSG_TX].rx_info, psCanFrameToSend->u32Identifier, psCanFrameToSend->au8Data, (uint32_t)0UL); /*-----------------------------------Runtime Operation -------------------------------------------------------------------*/ I tried sending data with timeout(Any Value from 1UL ) to get STATUS_SUCCESS   . In this case controller will go for hang state. /*-----------------------------------Runtime Operation -------------------------------------------------------------------*/ Returnvalue=FLEXCAN_DRV_SendBlocking(INST_FLEXCAN_CONFIG_1, E_MB_MSG_TX, &arrayMessageBufferInfo[E_MB_MSG_TX].rx_info, psCanFrameToSend->u32Identifier, psCanFrameToSend->au8Data, (uint32_t)10UL); /*-----------------------------------Runtime Operation -------------------------------------------------------------------*/             Observation is that controller is stuck at OSIF_SemaWait function, because stopped producing osif_Tick. The following line of controller got hang, observed delta is 0 to hang the controller.               if ((timeoutTicks != OSIF_WAIT_FOREVER) && (delta > max))     /* Line number 349 in osif_baremetal.c  */             Not received any TX completion interrupt to post semaphore from ISR. Since Post semaphore we have at FLEXCAN_CompleteTransfer function. NOTE: It's not hitting any ISR in CAN Blocking mode  Since we don’t have to process anything in non-blocking mode for TX operation. We want to try blocking mode with STATUS_SUCCESS   message. Could you please review the above details and provide us the detail to fix the same and let us know the list of methods to improve CAN TX frame transmission from the application. Share suitable examples to explore all the methods. Additional note: Controller: S32k116 SDK Version : S32SDK_S32K1XX_RTM_4.0.2 Referred link : file:///C:/NXP/S32DS.3.4/S32DS/software/S32SDK_S32K1XX_RTM_4.0.2/doc/html_S32K116/group__flexcan__driver.html Re: CAN TX reset issue Hi@AbhiMR Sorry for the long waiting, cause we overloaded recently. Could you please provided your project and then i will help you to check it. Re: CAN TX reset issue Further to my debugging info. The semaphore has not been posted to continue the operation. It has to happen from  FLEXCAN_CompleteTransfer(instance, mb_idx); .  It will happen only when I receive a TX_Complete interrupt even in blocking mode, It's not happening. The config I am using is of for CAN init  flexcan_user_config_t flexcanInitConfig_500k_listen = { .flexcanMode = FLEXCAN_LISTEN_ONLY_MODE, .fd_enable = false, .payload = FLEXCAN_PAYLOAD_SIZE_8, .max_num_mb = 16UL, .num_id_filters = FLEXCAN_RX_FIFO_ID_FILTERS_8, .is_rx_fifo_needed = false, .transfer_type = FLEXCAN_RXFIFO_USING_INTERRUPTS, .rxFifoDMAChannel = 0U, .pe_clock = FLEXCAN_CLK_SOURCE_OSC, .bitrate = { .propSeg = 7UL, .phaseSeg1 = 4UL, .phaseSeg2 = 1UL, .preDivider = 1UL, .rJumpwidth = 1UL } };flexcan_user_config_t flexcanInitConfig_500k_listen = { .flexcanMode = FLEXCAN_LISTEN_ONLY_MODE, .fd_enable = false, .payload = FLEXCAN_PAYLOAD_SIZE_8, .max_num_mb = 16UL, .num_id_filters = FLEXCAN_RX_FIFO_ID_FILTERS_8, .is_rx_fifo_needed = false, .transfer_type = FLEXCAN_RXFIFO_USING_INTERRUPTS, .rxFifoDMAChannel = 0U, .pe_clock = FLEXCAN_CLK_SOURCE_OSC, .bitrate = { .propSeg = 7UL, .phaseSeg1 = 4UL, .phaseSeg2 = 1UL, .preDivider = 1UL, .rJumpwidth = 1UL } }; FLEXCAN_DRV_Init(INST_FLEXCAN_CONFIG_1, &flexcanState0, &flexcanInitConfig_500k_listen);
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Camera tuning on i.MX8M Quad Hello, I'd like to know if i.MX8M Quad supports camera tuning inside If i.MX8M Quad does not support camera tuning, Customer always have to apply the pre-tuned Camera Module with i.MX8M Quad? Thank you. Best regards, Andy i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Camera tuning on i.MX8M Quad Hello, Thank you for your quick reply. Best regards, Andy Re: Camera tuning on i.MX8M Quad Hello, The Mx8Mplus support camera tunning trough ISP module that is not present on MX8MQ. Regards
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[MKW36A512VFP4] Antenna Diversity Dear NXP support team, Please let me know if KMW36 supports antenna diversity. If it support antenna diversity, please share the related reference circuit and guide for me how to use about software and hardware. Thanks, Deega Jung Product: KW 34|35|36 Re: [MKW36A512VFP4] Antenna Diversity Hello, Thank you for contacting NXP support. The antenna diversity is implemented with two antenna’s which are separated and have offset orientation which allows the transceiver to statistically improve the chance to receive the RF signal outside the dynamic range of the system. The KW36 has support only for one antenna so the antenna diversity is not supported on this chip, on the KW36-FRDM has a PCB F-antenna which can be bypassed to test via SMA connection. We provide an schematic and design file that can be located on the FRDMKW36. This provide the information on how this is configured in the board. Please let me know if there is anything else where I can help you.
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DRM support on iMX8M Quad Hello, Could you tell me if iMX8M Quad supports DRM, Widevine? If so, do we need a license agreement witn NXP for DRM support? Thank you. Best regards, Andy Re: DRM support on iMX8M Quad Hello, The i.MX8M can support Widevine Level 1 in Android. There has been some work being done on this regard, although it’s handled through NXP Professional Services, so we do not have any public information on pricing we can share. (The i.MX8M should also be able to support it on Linux) I would need to ask you to please contact NXP Professional Services for more details. https://www.nxp.com/support/support/nxp-professional-services:PROFESSIONAL-SERVICE Regards
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S32K322中断 我需要在 PB17 上使用 EIRQ[31],如果我需要将此 PB17 配置为外部中断,则意味着我需要配置 IMCR[559],但在 S32K322 中,我的 IMCR 最高只能到 IMCR[409]。如何在 S32K322 中配置 IMCR[559]。 回复:S32K322中断 你好@danielmartynek , 它正在工作,感谢您的支持。
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Writing data from UART with DMA in a new Array Hi all, I receive the data, but the problem is, that the CITER value from the ELINKNO register doesn't match with the value I got, when I write the registervalue in a variable. Additionally the data in the recv_buf is not written from zero or the same field than in Msg. I attached the DMA init and the code for the UART IRQ handler. Please help me. Sandra Re: Writing data from UART with DMA in a new Array Hi @12914A, Have you read the register's value by debugging? You can also test the example included with the example projects, which is based on the code in AN5413: S32K1xx Series Cookbook. Best regards, Julián
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Echo cacellation for video calling on IMX8M Quad Hello, I'd like to if iMX8M Quad support echo cancellation function for video calling. If it is possible, some audio parts are needed to connect to i.MX8M Quad? Thank you. Best regards, Andy i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Echo cacellation for video calling on IMX8M Quad Hi, Jorge Thanks for your prompt reply. It helps me a lot. Best regards, Andy Re: Echo cacellation for video calling on IMX8M Quad Hello,   We have VoiceSeeker that is a multi-microphone voice control audio front-end signal processing solution. VoiceSeeker provides high performance beamforming and multi-channel acoustic echo cancellation (AEC).   This solution is supported on i.MX8MM, i.MX8MP and i.MX RT600.   I suggest you take a look on this fact sheet.   Best regards.
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S32K322 interrupts I need to use EIRQ[31] on PB17, If I need to configure this PB17 as external interrupt means I need to configure IMCR[559] but in S32K322 I have IMCR only up to IMCR[409]. How can I configure IMCR[559] in S32K322. Re: S32K322 interrupts Hi @danielmartynek, It is working thanks for the support. Re: S32K322 interrupts Hi @vignesh3, IMCR_512 (in the excel) is IMCR[0] in RM. 559 - 512 = 47. Use IMCR[47]. I would recommned using the RTD drivers for that. Regards, Daniel Re: S32K322 interrupts Hi  danielmartynek, How many IMCR register is there in S32K322. that did not mentioned in RM, I need to config EIRQ[31] that means IMCR[559] I need to write but this register is not there in S32K322. Re: S32K322 interrupts Hi @vignesh3, This is specified in the RM: BR, Daniel
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