DCDx 工具已禁用 DCD配置似乎已被禁用。如何才能实现这一点？ 是工具兼容性问题吗？ 使用 MCUXpresso IDE v25.6.136。 打开从 SDK_26_03_00_FRDM-MCXA266 中提取的示例项目 usb_cdc Re: DCDx Tool is disabled Hello 能否请您确认一下，您是否对示例进行了修改，还是直接从 SDK 导入的示例未经任何修改？ 可能是您的配置工具版本过旧，其中不包含 MCXA266，您需要更新。 我检查了我的版本，没有出现错误信息。我已经更新了版本。 在 MCUXpresso IDE 中，配置工具更新默认处于禁用状态。要更新 MCUXpresso IDE 中集成的配置工具，请按照本文中的说明启用配置工具更新。 窗口>首选项>安装/更新>可用软件站点>启用MCUXpresso配置工具 更新MCUXpresso IDE中的配置工具 之后可能会出现一些更新提示窗口，选择更新并点击“下一步”，然后接受许可协议条款。 点击“接受”>“完成”>“全选”>“信任所选”>“重启 MCUXpresso IDE”。 然后请重试并再次查看 MCUXpresso IDE 功能窗口以确认版本。 如果这样可以解决问题，请告诉我；如果不行，能否请您手动安装最新版本的 Config Tools (26.03) MCUXpresso Config Tools v26.03，并告知我您的发现。 此致敬礼，路易斯 Re: DCDx Tool is disabled 我已将配置工具更新到最新版本，但仍然看到所选处理器不支持该工具：TEE，设备配置。使用 26.03 版本。 Re: DCDx Tool is disabled 你好， 你想达到什么目的？您似乎将 DCD 工具（代表设备配置数据，仅适用于部分 I.MXRT10xx）与 USB CDC 类混淆了，后者没有任何特殊工具，只是外设工具对某些 MCU 提供支持。 DCD 工具永远不会支持 MCXA 系列，因为据我所知，它不具备 DCD 工具所需的功能。 此致 彼得·赫拉德斯基 配置工具团队 Re: DCDx Tool is disabled 目前我正在手动添加DCD文件。为什么 MCXA 系列工具不支持它？ Re: DCDx Tool is disabled 你的DCD文件里有什么内容？DCD 工具生成在设备启动期间要加载的二进制数据，目前适用于 i.MXRT10xx，该功能由启动 ROM 提供。

后向兼容性 TJA1051 您好， 我的产品中使用的是TJA1050，但由于数据手册中的这一行，我将其替换为TJA1051： 今天我在做另一个项目的时候又遇到了TJA1051，然后看到了这个： 当 Vio = VCC 时，这意味着 VIH = 0.7 * 5 = 3.5V 数据手册 TJA1050 内容如下： 换句话说：TJA1050 和 TJA1051 在控制器方面不兼容。 不知何故我错过了那部分，现在我们的产品使用的是直接连接到 Kinetis MK22 的 TJA1051（不是 /3 版本），而 Kinetis MK22 有 3.3V 输出。 而且它运行良好。 所以我的问题是：我运气好吗？它居然奏效了？ 或者这是由于 MK22 引脚具有 5 伏耐压能力，以及 TXD 上的 TJA1051 内部上拉电阻共同作用的结果？ 我现在不知道该往哪个方向走了…… 接受现状，还是重新设计我们所有的产品？ 提前感谢！ 您好 约恩 Re: Backward compatibility TJA1051 1：您可以在 TJA1051 工作期间测试 TX 引脚值。 2：换成 TJA1051/3，应该就没有风险了。

如何使用 S32k344 多链接效果器 我正在使用 FRDM-A-S32K344 型号，并且我正在尝试通过 Multilink FX 下载 LED 闪烁功能，但它不起作用。我想知道为什么。我一直遇到错误，即使尝试通过 Gemini 修复也无济于事。请帮忙。 我还确认了 Multilink FX 型号的橙色指示灯（TGPWR）亮起。 Gemini 指示移除 JP11 OPENSDA 电压，但我不知道该怎么做。 Re: how to use S32k344 multilink fx 我解决了。移除 JP11 后就生效了。

在 MCUXpresso 中将 MCU 从 LPC54S018J4M 更换为 LPC54S018J2M 大家好， 我使用 MCUXpresso 和上述 MCU 的评估板开发了一个项目。 评估板采用的是 LPC54S018J4M，而我的定制板采用的是 LPC54S018J2M，两者基本相同，只是闪存容量不同（2 / 4 MB）。 我比较了两个处理器的 SDK 中的启动文件，它们完全相同，也就是说，两者都包含指向 4MB 闪存的 SPI 描述符。 /* SPI 描述符 - Winbond W25Q32JV */ 直接将内存详细信息第一行中的内存大小从 0x400000 更改为 0x200000 是否安全？ 顺祝商祺！ 雷纳 Re: Changing MCU from LPC54S018J4M to LPC54S018J2M in MCUXpresso 嗨@hfuhruhurr 谢谢你的帖子！ 建议始终选择您在项目中使用的特定设备/软件包。 请创建一个新项目，选择正确的设备包，然后将您现有的源文件、项目设置和配置复制到新项目中。 这将有助于确保为所选套餐正确生成所有设备特定设置，并可能解决任何与配置相关的问题。 此外，您还可以更改所选的MCU：如何使用MCUXpresso更改MCU 希望这些信息对您有所帮助！ Re: Changing MCU from LPC54S018J4M to LPC54S018J2M in MCUXpresso 亲爱的卡洛斯： 谢谢你的回复。我知道推荐的方法，但我想避免这种方法，所以才询问这个特定的模型，因为……嗯，我在原帖中已经阐述了我的理由。 我刚刚按照我的计划做了（将地图内存从 4MB 改为 2MB），它运行完美。 顺祝商祺！ 雷纳

u-boot migration from Zeus 2019.04 +fslc to Wrynose 2026.01 for LS1046/26 CPU Hi  We are using u-boot code version from  "git://source.codeaurora.org/external/qoriq/" for our LS1046/26 Cpu based cards. The version of this u-boot is  2019.04 +fslc. We also supports secure boot. We are now thinking of upgrading our u-boot to Wrynose 2026.01. Our existing U-Boot source code was originally obtained from the now-deprecated repository: git://source.codeaurora.org/external/qoriq/. Could you please advise on the appropriate Git repository to use for the latest code? Additionally, it would be helpful if you could share any key considerations or best practices to ensure a smooth transition during the upgrade. Re: u-boot migration from Zeus 2019.04 +fslc to Wrynose 2026.01 for LS1046/26 CPU Hello, For LS1046/LS1026A-family Layerscape U-Boot, the replacement for the deprecated CodeAurora QorIQ tree is: git clone https://github.com/nxp-qoriq/u-boot.git NXP guidance is to replace old URLs such as: source.codeaurora.org/external/qoriq/qoriq-components/u-boot.git with: github.com/nxp-qoriq/u-boot.git or, more generally, replace source.codeaurora.org/external/qoriq/qoriq-components with github.com/nxp-qoriq in build scripts, manifests, and Yocto recipes . For a Wrynose-based BSP , I would start from the QorIQ Yocto SDK manifest , not by cloning U-Boot alone: repo init -u https://github.com/nxp-qoriq/yocto-sdk -b wrynose repo sync --force-sync The public nxp-qoriq/yocto-sdk repo shows an active wrynose branch . The same repo documents the general repo-init flow and lists the Yocto branch/release mapping mechanism. For U-Boot specifically, the public nxp-qoriq/u-boot repo is the QorIQ U-Boot tree; its default branch shown in the retrieved repo page is lf_v2024.04 , and the active branch list also shows lf_v2026.04 . Tags shown include recent lf-* release tags such as lf-6.12.49-2.2.0 , lf-6.18.2-1.0.0 , and lf-6.18.20-2.0.0 . So the practical rule is: use the U-Boot revision selected by the Wrynose Yocto manifest/recipe , rather than manually taking an arbitrary “latest” U-Boot branch. Key transition considerations: Migrate all CodeAurora references Search your build tree for old URLs: grep -rn 'source.codeaurora.org/external/qoriq' . Replace source.codeaurora.org/external/qoriq/qoriq-components with github.com/nxp-qoriq in manifests, build configs, and recipes. Use the release manifest as the source of truth For a BSP upgrade, keep U-Boot, ATF, RCW, CST, kernel, device trees, and recipes aligned to the same NXP release stream. NXP’s current Layerscape flow commonly uses ATF + U-Boot , not standalone U-Boot only. Port your custom board from the LS1046ARDB reference again For LS1046 custom boards, NXP points to the LS1046ARDB U-Boot reference files: configs/ls1046ardb_tfa_defconfig , arch/arm/dts/fsl-ls1046a-rdb.dts , and board/freescale/ls1046ardb/ . For older-style customizations, also review include/configs/ls1046ardb.h and the board folder. Reconcile your existing board changes against the new device-model/Kconfig/DTS structure rather than copying old 2019.04 code wholesale. Secure boot: rebuild and re-validate the full chain In Yocto, secure boot images are built by adding: DISTRO_FEATURES:append = " secure" then running: bitbake secure-boot-qoriq CST, SRKH, OTPMK, RCW SB_EN , ATF, and signed U-Boot image handling should all be revalidated on a development/non-fused unit before touching production fuse settings. Expect boot-flow differences from 2019.04 Since LSDK 18.12, NXP introduced the TF-A boot flow for Layerscape RDBs: Boot ROM → BL2 → BL31 → U-Boot/UEFI → Linux , compared with the older PPA-style flow. If your current product still carries assumptions from the old PPA/direct U-Boot path, review them carefully. Keep a controlled migration baseline First bring up an unmodified NXP reference configuration close to your hardware. Then apply your board deltas in small groups: RCW/SerDes, DDR, console, boot media, QSPI/eMMC/SD, Ethernet/FMan, environment layout, secure boot. Validate both non-secure and secure boot paths before declaring parity with the old 2019.04 + fslc tree. Regards

32ビット並列受信（立ち上がりエッジピン）（FRDM-MCXN947） 現在、32ビットパラレルシフターを構成して、外部デバイスからデータを受信するようにしようとしています。その際、ピンの1つ（FLEX_D4/DATA_VALID）をデータシフトのための信号として使用します。 これまでの進歩により、DATA_VALIDがトリガーされたときに32ビットデータを読み込み、そのデータをeDMA Ping-Pongバッファに移動させることが可能になりました。現在、Printf文を使用してバッファデータをコンソールに読み出すテストを行っています。Shifterにエラーが発生した場合（データシートによると通常はオーバーランを示す）、それもコンソールに出力されます。 私の主な問題はTimerConfigにあると考えています。DATA_VALIDの立ち上がりエッジでShifterが何度も読み取りをトリガーしてしまうのですが、正しいデータを実際に移動させながら一度だけ読み取りを行うような設定が見つかりません。 コンソール出力: 読み取りバッファA: 0x3fffefff シフトエラーコード: 0x8 シフターの状態: 0x0 SHIFTSDEN: 0x8 DMA CSR: 0x0 DMAエラー: 0x0 TCD BITER: 0x2 CSR: 0x12 CH_MUX: 0x40 バッファBの読み取り: 0x3ffffefff シフトエラーコード: 0x8 シフターの状態: 0x0 SHIFTSDEN: 0x8 DMA CSR: 0x0 DMAエラー: 0x0 TCD BITER: 0x2 CSR: 0x12 私のFLEX_IOの設定ファイルを添付します。ありがとう。 クロック|タイマー 通信・制御(I3C |I2C |SPI |FlexCAN |イーサネット |FlexIO) 開発ボード MCX N Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) 更新: 「 kFLEXIO_TimerDisableOnTriggerFallingEdge 」がCPUをコールバック内に留めていたことが分かりました。 タイマー比較後に無効にしたいのですが、このオプションでは SHIFTBUF は 0x0 の値のみを報告し、SHIFTERR フラグは報告しません。 Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) こんにちは、 @carlos_oさん、返信ありがとうございます！ 思ったようにタイマーをエッジで表示DATA_VALIDきましたが、Threadは更新しませんでした。現在使用しているコードを添付します。 私が現在直面している問題は、FlexIOを他のデバイスと同等の速度で動作させることです。今のセットアップでは基本的にサンプリングDATA_VALIDで、高速になるとシフターがオーバーランになることがあります。私の考えでは、私のデザインにはMCXとホストデバイス間で共有クロックが必要であり、ホストデバイスが32ビットデータを送る予定だと思います。32ビットデータバス内のピンをこの信号に使えるので、FlexIOのピンを分割する必要がありません。このアイデアについて何かご意見があればぜひお聞かせください! 以前のご質問にお答えします。 1.レジスタは、低速でも意図どおりにデータが格納されています。DATA_VALIDの降下エッジごとに、SHIFTBUFは32ピンからデータを保存し、EDMAは散布・採集方法でピンポンバッファに転送します。 2. アナログ Discovery 2で入力をシミュレートしています。アナログ Discovery 2はデータピンが16本しかないため、32ビットの上限値を書き込み、DATA_VALIDピンでクロックをシミュレートし、未使用のピンを固定しています。低速走行時におけるテストデータは正しく一致している。 3. 私はFRDM-MCXN947を使用しています Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) こんにちは、 @Flexin_On_The_IO さん。 投稿ありがとうございます！ あなたのレジスターで現在の行動について教えていただけますか? どのようなテストデータを受信しようとしていますか？また、現在どのようなデータが受信されていますか？ どのMCXNを使っているのか教えていただけますか? これはカスタムボードですか？そうでない場合は、使用しているボードを指定してください。 Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) こんにちは、 @Flexin_On_The_IO さん。 返信が遅くなり申し訳ありません。 目指している速度を具体的に教えていただけますか? AN14284 『FlexIO Emulated インターフェース のタイミングパラメータチューニング』をレビューすると良いでしょう。このアプリのノートにはあなたの目標に役立つ情報が載っているかもしれません。    Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) こんにちは、 @carlos_o さん。 私が最低限達成したい速度は18.5MHzです。シフターは約6.25MHzで追いつくことは確認できますが、ハードウェアの制限で高速で問題が:Pました。 下は私のAnalog Discovery 2の波形で、MCLK信号とデータ用のバイナリカウンタ(AD2のピン数が少ないため12ビットのみ)、そしてDATA_VALID信号を手動で制御しています。 高周波数(20 MHz)になると、AD2は実際にはまともな方形波を出せず、信号の整合性が悪いためにFRDMが望ましくないシフトをトリガーしているのではないかと気づきました。 送っていただいたファイルを拝見しましたが、私が解決したいと考えている問題の解決策になるかもしれないと思いました。DATA_VALIDがMCLKと同時に立ち上がり/立ち下がりする場合、クロックが完全にデクリメントできないため、データのシフトが欠落すると考えられます。 私の主な質問は、シフターは通常、他のデバイスからのトリガー信号がローになった後でも、完全なシフトサイクルを完了するために遅延クロック/タイマーを必要とするのかということです。現在のシステム構成では、データを取りこぼさないように、MCLKのエッジ間でDATA_VALIDがハイレベルを維持する必要があります。

how to use S32k344 multilink fx I am using the FRDM-A-S32K344 model and I am trying to download the LED blinky feature via Multilink FX, but it isn't working. I would like to know why. I keep getting errors, and even trying to fix it through Gemini doesn't help. Please help. I also confirmed that the orange light (TGPWR) was on for the Multilink FX model. Gemini says to remove the JP11 OPENSDA voltage, but I don't know how to do that. Re: how to use S32k344 multilink fx I solved it. It worked after removing JP11.

DCDx Tool is disabled DCD configuration appeared disabled. What can be done to enable it? Is it problem with compatibility of the tool?  Working with MCUXpresso  IDE v25.6.136. Opening extracted example project usb_cdc from SDK_26_03_00_FRDM-MCXA266 Re: DCDx Tool is disabled Hello Could you help us confirm if you have made modifications on the example or it’s the example without modifications from importing from the SDK? Probably you had an older version of Config tools that do not contain MCXA266 and you need to update. I review my versions and doesn’t appear the error message. I have updated versions. In the MCUXpresso IDE, the config tools updates are disabled by default. To update Config Tools integrated in the MCUXpresso IDE, kindly follow the instructions in this post to enable the Config tools updates. Window>Preferences>Install/Update>Available Software Sites>Enable MCUXpresso Config Tools Updating Config Tools in the MCUXpresso IDE, After this, probably some windows appear for available updates, select them and next, then accept terms of license agreement, Click on Accept>Finish>Select All>Trust Selected>Restart MCUXpresso IDE Then please retry and view for the MCUXpresso IDE Features window again to confirm the versions. Let me know if that work for you, and if not, could you help us install the latest version of Config Tools (26.03) manually MCUXpresso Config Tools v26.03 and let me know your findings. Best Regards, Luis Re: DCDx Tool is disabled I updated Config Tools to the latest version, but still see that Tools are not supported for the selected processor: TEE, Device Configuration. Using 26.03 version. Re: DCDx Tool is disabled Currently I'm adding DCD file manually. Why it shouldn't be supported by the tool for MCXA family? Re: DCDx Tool is disabled Hi,  What are you trying to achieve ? It seems you are confusing DCD tool (which stands for Device Configuration Data and is available only for some of the I.MXRT10xx) and the USB CDC class which does not have any special tool, except the support in the Peripherals tool for some MCUs. The DCD tool will never be supported for MCXA family, as it as far as I know doesn;t have the feature needed for DCD tool.  Regards Petr Hradsky Config Tools Team Re: DCDx Tool is disabled What is inside your DCD file? The DCD tool generates binary data to be loaded during device boot and is currently provided for i.MXRT10xx where this feature is provided by the boot rom.  

Changing MCU from LPC54S018J4M to LPC54S018J2M in MCUXpresso Hi everybody, I developed a project with MCUXpresso using the evaluation board for above mentioned MCUs. The eval board carries a LPC54S018J4M and my custom board carries the LPC54S018J2M which is essentially the same except the different size of the flash memory (2 / 4 MB) I compared the startup files in SDKs for both processors and they're exactly the same, i.e. both have the SPI descriptor for 4MB flash inside /* SPI Descriptor - Winbond W25Q32JV */ Is it safe to just change the memory size in the Memory Details, first line, from 0x400000 to 0x200000? Best regards, Rainer Re: Changing MCU from LPC54S018J4M to LPC54S018J2M in MCUXpresso Hi @hfuhruhurr  Thank you for the post! The recommendation always will be to select the specific device/package you are using in your project.  Please create a new project, select the correct device package, and then copy your existing source files, project settings, and configurations into the new project. This will help ensure that all device-specific settings are generated correctly for the selected package and may resolve any configuration-related issues. Also, you could change the MCU selected: How to Change MCU with MCUXpresso Hope this information helps! Re: Changing MCU from LPC54S018J4M to LPC54S018J2M in MCUXpresso Dear Carlos, thanks for your response. I am aware of the recommended way but wanted to avoid this and therefore asked for this specific model since ... well I outlayed my reasoning in the original post. I just did what I had in mind (changing the memory in the map from 4MB to 2MB) and it works flawlessly. Best regards, Rainer

32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) I am currently trying to configure a 32-bit parallel Shifter to receive data from an external device with one of the pins (FLEX_D4/DATA_VALID) being used as a signal to Shift in the data.  The progress I have made has allowed me to read in the 32-bit data when DATA_VALID has triggered and move the data into an eDMA Ping-Pong buffer. I am currently testing through Printf statements of reading the buffer data to a console and if the Shifter has any errors (usually indicating Overrun according to the datasheet) they will print to the console as well.  I believe my main issue is with the TimerConfig as it is triggering the Shifter to read too many times on one rising edge of DATA_VALID but I have not found a configuration that allows me to read only once while actually moving the correct data.  Console Output:  Reading Buffer A: 0x3fffefff Shifter Error Code: 0x8 Shifter Status: 0x0 SHIFTSDEN: 0x8 DMA CSR: 0x0 DMA Error: 0x0 TCD BITER: 0x2 CSR: 0x12 CH_MUX: 0x40 Reading Buffer B: 0x3fffefff Shifter Error Code: 0x8 Shifter Status: 0x0 SHIFTSDEN: 0x8 DMA CSR: 0x0 DMA Error: 0x0 TCD BITER: 0x2 CSR: 0x12 My FLEX_IO setup is attached. Thank you. Clock|Timers Communication & Control(I3C | I2C | SPI | FlexCAN | Ethernet | FlexIO) Development Board MCXN Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) Update: I was able to deduce that "kFLEXIO_TimerDisableOnTriggerFallingEdge" was keeping my CPU in the callback. I believe I want to disable after a Timer Compare but with this option SHIFTBUF only reports a value of 0x0 but with no SHIFTERR flag.  Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) Hi  @Flexin_On_The_IO  Thank you for your post! Could you please share the current behavior you see in your register?  Which test data are you trying to receive and what you currently get?  Could you please share which MCXN are you using?  Is it a custom board? if not, please specify the board you are using Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) Hi @carlos_o thank you for the reply! I was able to get the Timer reading on DATA_VALID edge like I wanted but did not update the thread. My current code is attached. The problem I am facing now is getting the FlexIO to keep up with other devices. In my current setup I am basically sampling DATA_VALID and at higher speeds, the Shifter can get Overrun. My thinking is that my design requires a shared clock between the MCX & host device that would be sending the 32-bit data. I can use a pin within the 32-bit data bus to be this signal so I do not need to breakup the FlexIO pins. Any input on this idea would be welcome! To answer your previous questions: 1. The registers are populating as intended at lower speeds. On every DATA_VALID falling edge, the SHIFTBUF stores data from the 32 Pins and the EDMA transfers to my Ping-Pong buffer via a Scatter-Gather method. 2. I am simulating input through an Analog Discovery 2, since that only has 16 data pins I am just writing the upper values of the 32-bits, simulating a clock on the DATA_VALID pin, and tying the unused pins down. Test data is matching correctly at low speeds. 3. I am using the FRDM-MCXN947 Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) Hi @Flexin_On_The_IO  Apologize the late reply,  Could you please specify the speeds you are trying to achieve?  You could review AN14284: Timing Parameter Tuning for FlexIO Emulated Interface, this app note could have some helpful information to your goal.    Re: 32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947) Hello again, @carlos_o  The bare minimum speed I am trying to reach is 18.5MHz. I can confirm the Shifter does keep up at around 6.25MHz but I was having issues at higher speeds due to my hardware limitations :P.  Below is my Analog Discovery 2 waveform where I am just providing the MCLK signal, a binary counter for the data (12-bit only due to low pin count on AD2), and manually controlling the DATA_VALID signal.  When I get to higher frequencies (20 MHz) I realize the AD2 cannot actually provide a decent square wave and may be causing my FRDM to trigger undesired Shifts due bad signal integrity.  I was looking at the file you sent me and I think it may be a solution to an issue I want to take care of. If DATA_VALID rises/falls at the same time as MCLK I believe it misses the a Shift of data since the clock was not able to fully decrement. My main question is do the Shifters usually require a delayed clock/Timer in order to complete their full shift cycle even after the Trigger from the other device has gone low? My current setup requires the DATA_VALID to remain high between MCLK edges to not miss the data.

How to force 32-bit instructions (avoiding 16-bit Thumb) on i.MXRT1170 EVKB using Arm FuSa Compiler Hi Everyone, I am currently working on a Proof of Concept (PoC) project using the NXP MIMXRT1176DVMAA processor on an i.MXRT1170 EVKB board. My development environment consists of MCUXpresso IDE with the safety-certified Arm Compiler for Embedded FuSa.During compilation, I want to avoid the generation of 16-bit instructions and force the toolchain to emit only 32-bit instructions.I understand that the Thumb-2 (T32) instruction set natively mixes 16-bit and 32-bit instructions by default to balance performance and code size. However, for our project requirements, we need every single generated instruction to be exactly 32 bits wide. Could anyone kindly guide me on how to configure the compiler or toolchain options in MCUXpresso IDE to enforce 32-bit wide instruction generation? Thank you, Karthi Re: How to force 32-bit instructions (avoiding 16-bit Thumb) on i.MXRT1170 EVKB using Arm FuSa Compi Hi @KD7 , Thanks for your interest in NXP MIMXRT series! On RT1170 / Cortex-M7, this is not supported as a global compiler setting. The core executes ARMv7-M Thumb/T32 code, and T32 is inherently mixed 16-bit/32-bit. The A32 -marm option would be the fixed 32-bit instruction set option, but it is not valid for M-profile targets. For hand-written assembly only, .W can force selected T32 instructions to 32-bit encodings where valid, but it cannot force all compiler-generated C/C++ instructions to be 32-bit. ARM may provide more information on this topic. Thanks and best regards, Gavin

如何使用 Arm FuSa 编译器在 i.MXRT1170 EVKB 上强制执行 32 位指令（避免使用 16 位 Thumb 指令集） 大家好， 我目前正在使用 NXP MIMXRT1176DVMAA 处理器在 i.MXRT1170 EVKB 板上进行概念验证 (PoC) 项目。 我的开发环境由 MCUXpresso IDE 和经过功能安全认证的 Arm 嵌入式 FuSa 编译器组成。在编译过程中，我希望避免生成 16 位指令，并强制工具链只生成 32 位指令。我知道 Thumb-2 (T32) 指令集默认情况下会混合使用 16 位和 32 位指令，以平衡性能和代码大小。但是，根据我们的项目要求，我们需要生成的每一条指令都正好是 32 位宽。 请问哪位好心人可以指导我如何在 MCUXpresso IDE 中配置编译器或工具链选项，以强制生成 32 位宽的指令？ 谢谢你， 卡尔蒂 Re: How to force 32-bit instructions (avoiding 16-bit Thumb) on i.MXRT1170 EVKB using Arm FuSa Compi 嗨@KD7 ， 感谢您对 NXP MIMXRT 系列产品的关注！ 在 RT1170 / Cortex-M7 上，不支持将此作为全局编译器设置。该内核执行 ARMv7-M Thumb/T32 代码，而 T32 本质上是 16 位/32 位混合的。A32 -marm 选项是固定的 32 位指令集选项，但对 M我的目标无效。 仅对于手写汇编，.W 可以强制选定的 T32 指令在有效的情况下使用 32 位编码，但它不能强制所有编译器生成的 C/C++ 指令都是 32 位的。 ARM可能会提供更多相关信息。 谢谢，并致以最诚挚的问候！ 加文

MCUXpresso Secure Provisioning Tool (SEC) version 26.06 now available What's new in SEC v26.06? Support new processors: - MCX A series extended with MCX A557 variant - MCX N series extended with MCX N246 variant - New MCX NxxxT processors: MCX N246T/N247T/N527T/N536T/N537T/N546T/N547T/N556T/N557T/N946T/N947T - New MCX C processors: MCXC151, MCXC161, MCXC162 - i.MX952 A0 processor with Cortex-M debug support (unsigned only, serial downloader) MCX A28x/45x/5xx: Added FlexSPI NOR support; added signed & encrypted boot support for ECC and PQC ML-DSA MCX E31x: Added key catalog configuration, SMR region configuration and reset core configuration.  Added debug access protection (ADKP) for OEM_PROD and IN_FIELD life cycles MCX L25x: Added Secure Installer support for signed boot and more ! Known issues and limitations Troubleshooting Downloads  To download the installer, please login to our download site via: https://nxp.com/mcuxpresso/secure Useful links: Release Notes: MCUXpresso Secure Provisioning Tool (SEC) release notes Fact Sheet: MCUXpresso Secure Provisioning Tool Fact Sheet announcement

Create Key & Certificate for HTTPS Server using IP on Windows Introduction HTTP is a protocol used to enable communication between web browsers and servers. A secure variation of this protocol is HTTPS, which adds encryption to protect data exchanged between the client and the server. This ensures that even if someone intercepts the communication, they cannot understand the transmitted information. In embedded systems and MCU-based applications, libraries such as mbedTLS are commonly used to implement secure communication. These libraries rely on cryptographic keys and digital certificates. For production environments, certificates are typically signed by a Certificate Authority (CA), which guarantees their authenticity and allows web browsers to trust the connection. However, when a certificate is generated manually (self-signed), web browsers do not inherently trust it. Despite this, self-signed certificates are a practical option for internal or development use cases, since the communication remains encrypted. Additionally, it is possible to configure client devices to trust these certificates when required.   Download OpenSSL First, verify whether OpenSSL is installed on your system. If not, it must be downloaded and installed. To check if OpenSSL is already installed, run next line in command prompt: openssl --version If the command is not recognized, OpenSSL is not installed. If OpenSSL is not already installed on your system, you can easily find installation instructions by searching the web for your specific operating system. There are many reliable step‑by‑step guides available for Windows, Linux, and macOS that explain how to download, install, and verify OpenSSL properly. Following an up‑to‑date guide for your OS will help ensure the installation is completed correctly and securely.   Preparation Select a folder where all keys and certificates will be stored. Open a command prompt in this folder and proceed with the following steps.   Create Keys NOTE: Please replace %%Name%% according to your preference. Create a private key for the Server Certificate openssl genrsa -out %%KeyName%%.key 2048 Create a private key to simulate Certificate Authority (CA) openssl genrsa -out %%CAKeyName%%.key 2048 Create Certificate Authority Generate a self-signed CA certificate: openssl req -x509 -new -nodes -key %%CAKeyName%%.key -sha256 -days 3650 -out %%CAName%%.crt Create Server Certificate Config file to request certificate Create a configuration file named %%ConfigFileName%%.cnf using the following template, this can be created with Notepad. [req] default_bits = 2048 prompt = no distinguished_name = dn req_extensions = v3_req [dn] C=%%Country%% ST=%%State%% L=%%City%% O=%%Owner%% OU=%%Division%% CN=%%CommonName%% [v3_req] subjectAltName = @alt_names [alt_names] IP.1 = %%ServerIP%% Generate Certificate Signing Request (CSR) openssl req -new -key %%KeyName%%.key -out %%CertificateRequestName%%.csr -config %%ConfigFileName%%.cnf Sign Certificate with simulated CA openssl x509 -req -in %%CertificateRequestName%%.csr -CA %%CAName%%.crt -CAkey %%CAKeyName%%.key -CAcreateserial -out %%CertificateName%%.crt -days 365 -extensions v3_req -extfile %%ConfigFileName%%.cnf Prepare to use with mbedTLS Convert private Key to DER (Distinguished Encoding Rules) openssl rsa -in %%KeyName%%.key -outform DER -out %%KeyName%%_key.der Convert Certificate to DER (Distinguished Encoding Rules) openssl x509 -in %%CertificateName%%.crt -outform DER -out %%CertificateName%%.der Convert Key DER to array in a source file xxd -i %%KeyName%%_key.der > %%KeyName%%_key.c Convert Certificate DER to array in a source file xxd -i %%CertificateName%%.der > %%CertificateName%%_cert.c Install CA Certificate (Optional – Avoid Browser Warnings) To prevent browser warnings, install the CA certificate on the client device (PC, phone, etc.). Double-click the CA certificate file (.crt). Click Install Certificate. Select Local Machine. Choose Place all certificates in the following store. Click Browse and select Trusted Root Certification Authorities. Click Next → Finish. After this step, the system will trust certificates signed by this CA.

MCUXpresso Config Tools 26.06 Now Available We are pleased to announce that MCUXpresso Config Tools 26.06 are now available. Downloads Also via installer in MCUXpresso for VS Code https://marketplace.visualstudio.com/items?itemName=NXPSemiconductors.mcuxpresso In order to use it with other toolchains, download the installer for all platforms, please login to our download site via:  https://www.nxp.com/mcuxpresso/config Please refer to https://docs.mcuxpresso.nxp.com/config/latest/ for installation and quick start guides. For online version, login into MCUXpresso site: MCUXpresso WEB Release Notes Full details at https://docs.mcuxpresso.nxp.com/config/latest/ Version 26.06 Update for the latest NPI support

Config Tools for i.MX 26.06 Now Available We are pleased to announce that Config Tools for i.MX 26.06 are now available. Downloads & links To download the installer for all platforms, please login to our download site via:  https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX Please refer to  Documentation  for installation and quick start guides. For further information about DDR config and validation, please go to this  blog post. Release Notes Full details on the release (features, known issues...) Version 26.06 DDR tool – NXP-validated memory configurations for multiple vendors is available System Manager – extended CLI support for a headless setting

S32K388 GMAC0 lwIP FreeRTOS S32DS36 RTD600 Debug Error Dear 1. The original project was developed based on S32DS3.5 + RTD5.0.0, Build OK & Run OK 2. Development requires basic RTD 6.0.0. Development environment: S32DS 3.6.2 + RTD 6.0.0 + TCPIP_STACK_3.0.0 + FreeRTOS_11.1.0_6.0.0 3. RTD5.0.0 and RTD6.0.0 have significant differences, so projects based on the original RTD5.0.0 cannot be used. Instead, refer to the example code provided in the forum ( Example: S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600 ). 4. Modify the corresponding PIN according to your hardware platform as follows:          5. Debugging the example code revealed that some initialization steps failed, as follows:    6. If the corresponding code is masked, the program can run, but the PHY address cannot be found. The attached file contains a debug example. I'm not sure if the reference example provided on the forum has been modified, or if I only modified the PIN definition, or if there's some other configuration error. Re: S32K388 GMAC0 lwIP FreeRTOS S32DS36 RTD600 Debug Error Hi, Petrs Hello, you are absolutely right. I am indeed using my own hardware platform. During RTD 5.0.0 debugging, I was able to ping successfully using the example code provided on the official website. When using RTD 6.0.0 in person, I followed the same approach, mainly changing the PIN and discovering the code.The program failed to run. The attached file is based on my own hardware RTD 5.0.0 (S32DS3.5 + RTD 5.0.0 + TCPIP_STACK_2.0.0) and can ping. The example code is OK, but I'm not sure if the clock configuration is incorrect. Could you please provide some assistance? Re: S32K388 GMAC0 lwIP FreeRTOS S32DS36 RTD600 Debug Error Hi, It seems you only changed the MDIO/MDC pins compared to the community example you referred to. Does this mean you are using your own custom-designed board? I tested your project on the S32K388EVB-Q289, and the MCU initialization completed successfully. The PHY address was not detected because the MDIO/MDC signals are connected to different pins on the EVB. After changing the MDIO/MDC pins to PTD16/PTD17, the PHY address was correctly obtained. BR, Petr

What kind of port does the T Embed have? I have the standard model T Embed, but i have no Idea what kind of port it has (the other port, not usb c), because the official site says its a grove port, the lilygo Wiki site says its a qwiic port. Can anyone help me please? Boot ROM|Booting | Flash Re: What kind of port does the T Embed have? Hello @papaku , The T‑Embed is not an NXP product, so this may be outside the scope of our support. Thank you for your understanding. BR Celeste

调用 SDK 闪存 API，但 S32K144 的 D_Flash 中缺少一些数据 大家好： 我在我的项目（S32K144）中调用 SDK flash init API，然后调用 Flash erase 和 Flash write。然后我发现 Flash 中的一些数据变成了 0xFF。然后我尝试在 Flash 初始化和 Flash 擦除/写入之间添加延迟，然后数据就正常了。然后我尝试检查 while (!(FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK)); 而不是使用延迟函数。但它还是失败了。所以，我想知道是否需要延迟一段时间，等待闪存模块在硬件层完成初始化。 BR 洛基 Re: Call SDK flash API and some data in D_Flash missing of S32K144 嗨@Loky ， 你使用的是哪个驱动程序版本？ 不建议使用旧版 SDK 驱动程序；应改用 RTD 驱动程序。 Flash_Init 函数不会修改闪存内容。 擦除和写入功能已经在内部轮询 CCIF 标志，因此无需在应用程序代码中轮询它。 您观察到的现象可能与缓存或闪存预取缓冲区有关。请尝试禁用它们（PCCCR、OCMDR0），并检查问题是否仍然存在。 此致， 丹尼尔 Re: Call SDK flash API and some data in D_Flash missing of S32K144 嗨，丹尼尔： 这是我们目前使用的SDK Flash驱动程序版本。我的同事告诉我，S32K144 只有 SDK Flash 驱动程序，没有 RTD 驱动程序。能否简要解释一下SDK驱动程序出了什么问题？如果您有S32K144 RTD驱动程序，能否分享给我？ 我尝试了您提到的方法（禁用缓存），但没有成功。 当上电复位或低压检测RESET时，我会将一些信息记录到闪存中，并且同一扇区中还有一些其他数据。我将读取所有行业数据，更新信息并重写该行业相关内容。但我有一些新的发现。我发现读取闪存之前数据就已经是 0xFF 了。如果在执行擦除或写入指令时闪存意外断电，再次上电后，该扇区中的数据是否会变为 0xFF？我会继续调查这个问题，也许是我的软件出现了漏洞。 BR 洛基 Re: Call SDK flash API and some data in D_Flash missing of S32K144 嗨@Loky ， 该SDK是过时的软件。NXP 现在提供 RTD 驱动程序，其中也包括 Flash 驱动程序，包括 MCAL 层和与传统 SDK 等效的底层 IP 层。 您可以点击此处下载RTD软件包： https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K1-RTD44-D 请确保您使用的是 RTD 发行说明中指定的兼容版本的 S32 Design Studio。 你是否也禁用了预取缓冲区？ OCMDR0 – 程序闪存预取缓冲区 OCMDR1 – 数据闪存预取缓冲区 如果在擦除或编程操作进行期间闪存意外断电，NXP 无法保证数据完整性。受影响的闪存内容将变为未定义状态，并且可能包含 ECC 错误。 考虑使用模拟 EEPROM 功能。 它是为此目的而优化的。 请参阅 AN11983 – 使用 S32K1xx EEPROM 功能 https://www.nxp.com/docs/en/application-note/AN11983.pdf 第五章 S32K1xx 电压骤降检测 第六章 S32K1xx 新快速写入模式 此致， 丹尼尔 Re: Call SDK flash API and some data in D_Flash missing of S32K144 嗨，丹尼尔： 谢谢你寄来的RTD包裹，我明天会查看。 我还没试过禁用预取缓冲区。你是说在擦除并写入闪存之前，我应该同时禁用缓存和预取吗？我也会试试。 是的，我今天确实遇到了一个无法纠正的 ECC 错误，它触发了硬故障。除了在设备通电后再次擦除该扇区之外，还有其他方法可以解决这个 ECC 问题吗？我认为这种方法不适用于我目前的软件设计。 谢谢你的建议。我将与同事们讨论模拟EEPROM。 BR 洛基 Re: Call SDK flash API and some data in D_Flash missing of S32K144 嗨，丹尼尔： 我很高兴地告诉大家，我们已经找到了根本原因，因为在断电期间 VCC-5v 不稳定，MCU 在低电压下反复 RESET，导致软件在初始化期间擦除闪存，但无法写入闪存。 BR 洛基

LLCE + PFE CAN2ETHを使用した時の時間デターミニスティック(TAS)トラフィックのベストプラクティス NXPチームの皆様、こんにちは。 私たちは、HPCにコネクテッドされたゾーンコントローラとしてS32G399Aを用いる ゾーンアーキテクチャ に取り組んでいます 現在のアーキテクチャ： 現在、GMACは完全なTime-Aware Shaper(TAS / 802.1Qbv)サポートと完全なTSN機能を備えています。 DDSはこのGMACパス上で動作し、サービス指向トラフィックに関して良好な時間決定性を確保しています。 新たな探査： AN13423で説明された公式のNXP LLCE + PFEサンプルアプリケーション(CAN2ETH / ETH2CAN)を成功裏に立ち上げてテストしました。 目的は、選択された高周波・低遅延CAN信号をLLCE→PFE(IEEE1722 AVTP over UDP)を通じてECUから直接オフロードし、ゾーンコントローラのCPU負荷とレイテンシを削減することです。 コミュニティの議論から、PFEは802.1AS-Rev(時間同期)のみをサポートしており、GMACとは異なりTime-Aware Shaper(802.1Qbv / TAS)やフレームプリエンプションをサポートしていないことが分かっています。 質問／ガイダンス依頼： LLCEはPFEと密接に統合されているため（PFE_HIF3を使用）、このシナリオにおけるNXPの推奨するベストプラクティスは何ですか？ NXPが提供するPFEのソースコードを使ったりカスタマイズしたりすることで、PFEでTASサポートを有効にすることは可能でしょうか?(NXPがPFEのソースコードを提供しているのを見ましたが、これでTAS機能の追加や有効化に役立つでしょうか?) PFEでTASを有効化できない場合、LLCE + PFEトラフィックの強固な時間決定性を実現するためのNXPの推奨ベストプラクティスCAN2ETH何でしょうか? 重要な時間敏感なCAN信号は引き続きGMAC + TAS経路を使い、非クリティカルまたは大量の信号のみがLLCE + PFEを使うべきでしょうか? 推奨される方法は、PFEポートの下流にある外部TSNスイッチ(例えばSJA1110)に依存して、トンネルされたトラフィックの完全なTASスケジューリングを提供することでしょうか? 将来的にPFEでTASサポートを追加する計画やファームウェアアップデートはありますか? GMACとPFEの適切な分岐を決めつつ、セーフティに関わる決定性やハードリアルタイム信号の決定性を損なわないことを望んでいます。 公式なガイダンスやリファレンス・デザイン、構成のおすすめがあれば大変助かります。 お手数ですが、よろしくお願いいたします。 よろしくお願いいたします。 アルサル・イマーム SDVアーキテクト @ GK Automobiltechnologie (Disrupt) ゴールドVIP Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH こんにちは、アルサリマム ご連絡と詳細な情報提供をありがとうございました。 ご質問を拝受いたしました。確認のお手伝いをさせていただきます。 BR ジョーイ Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH こんにちは、arsalimam AUTOSAR_MCAL_ETH_43_PFE_UM.pdf を参照してください。PFE MCALドライバはTime Awareシェイパーをサポートしており、シェーパーは電子データ内で設定可能です。 この情報があなたの助けになれば幸いです。 BR ジョーイ Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH こんにちは、Joey_zさん。 迅速なご対応と、AUTOSAR_MCAL_ETH_43_PFE_UM.pdf をご紹介いただき、ありがとうございました。ご説明ありがとうございます。PFE MCALドライバのドキュメントを確認し、時間認識シェイパー(TAS / 802.1Qbv)の設定をEB(Elektrobit)ツールで検討します。 簡単な追加質問ですが、PFE MCALドライバーはフレームプリエンプション(IEEE 802.1Qbu / 802.3br)もサポートしていますか?もしそうなら、ユーザーマニュアルの該当セクションやTASと併用するための設定ガイダンスを共有していただければ幸いです。 GMACとLLCE+PFEのトラフィック分割を最終決定する前に、PFEパスで利用可能なTSN機能セットを完全に理解しようとしています。改めてサポートありがとうございます。 よろしくお願いいたします。 Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH こんにちは、アルサリマム 簡単な追加質問ですが、PFE MCALドライバーはフレームプリエンプション(IEEE 802.1Qbu / 802.3br)もサポートしていますか? >>>PFEはサポートしていません。 BR ジョーイ