i.MX 95 NNStreamer C++ 演示 NPU 问题 环境 | 元器件 | 细节 | |-----------|--------| | 主板 | i.MX 95 | | 电路板支持包。 | lf-6.12.49-2.2.0 | | 内核 | Linux ... 6.12.49-lts-next-gbf3cf0324593 #1 SMP PREEMPT 2026年6月16日星期二 03:46:26 UTC aarch64 | | NNStreamer | 2.4.2 | | TensorFlow Lite | 2.19.0 | | Neutron 委托 | libneutron_delegate.so 报告版本为 v1.0.0-f24d08e5，非零cp，构建于 2025 年 11 月 12 日 | | nnstreamer-examples | v1.6 (SRCREV 062ebd1) 和 v1.9 (SRCREV 37d3d86) — 行为相同 | |相机 | OV5640 MIPI 通过 libcamera (imx8-isi)，相机 ID：/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c | 从 meta-nxp-demo-experience/配方示例/imx-nnstreamer-examples/imx-nnstreamer-examples.bb 获取二进制文件，安装在 /opt/gopoint-apps/scripts/machine_learning/nnstreamer/。 模型 所有模型均来自 Yocto gopoint-base-apps 配方（downloads.json，lf-6.12.49_2.2.0 分支），托管于： https://github.com/nxp-imx-support/nxp-demo-experience-assets/raw/lf-6.12.49_2.2.0/models/ 目标模型位于 /opt/gopoint-apps/scripts/machine_learning/nnstreamer/downloads/models/： | 任务 | CPU 型号 | NPU 型号 | |------|-----------|-----------| | 人脸检测 | face-detection/ultraface_slim_uint8_float32.tflite | face-detection/ultraface_slim_uint8_float32_neutron.tflite | | 目标检测 | object-detection/ssdlite_mobilenet_v2_coco_quant_uint8_float32_no_postprocess.tflite | object-detection/ssdlite_mobilenet_v2_coco_quant_uint8_float32_no_postprocess_neutron.tflite | | 分类 | classification/mobilenet_v1_1.0_224_quant_uint8_float32.tflite | classification/mobilenet_v1_1.0_224_quant_uint8_float32_neutron.tflite | 来自同一来源的元数据：labels_mobilenet_quant_v1_224.txtcoco_labels_list.txt，box_priors.txt。 必需的环境变量 i.MX 95 上的 OV5640 需要 libcamera ISI： export CAMERA_BACKEND=libcamera export LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c'--- 问题 1：人脸检测 神经网络处理单元模式 CAMERA_BACKEND=libcamera \ LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c' \ /opt/gopoint-apps/scripts/machine_learning/nnstreamer/face_detection/example_face_detection_tflite \ --后端 NPU \ --model_path downloads/models/face-detection/ultraface_slim_uint8_float32_neutron.tflite \ --display_perf 时间 管道日志： 信息：启动应用程序... 调试：libcamerasrc name=cam_src camera-name=/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c \ ！video/x-raw,width=640,height=480,framerate=30/1,format=YUY2 !队列 ！tee name=t \ t.！队列名称=thread-nn 最大缓冲区大小=2 泄漏=2 \ ！imxvideoconvert_g2d name=scale_csc_g2d_0 ！video/x-raw,width=320,height=240,format=RGB \ ！张量转换器！tensor_filter latency=1 framework=tensorflow-lite \ model=downloads/models/face-detection/ultraface_slim_uint8_float32_neutron.tflite \ custom=Delegate:External,ExtDelegateLib:libneutron_delegate.so name=face_filter \ ！张量接收器名称=tsink_fd \ t.！队列名称=thread-img 最大缓冲区大小=2 泄漏=2 ！cairooverlay 名称=cairooverlay \ ！fpsdisplaysink name=img_tensor text-overlay=false video-sink=waylandsink 信息：NeutronDelegate 委托：49 个节点中有 2 个节点被委托，共 2 个分区。 信息：Neutron 委托版本：v1.0.0-f24d08e5，非零cp。 [libcamera v0.0.0+6194-lf-6.12.49-2.2.0] [ov5640 管道：ov5640 -> csidev-4ad30000.csi -> formatter@20 -> crossbar] 相机 camera.cpp:1215配置流：（0）640x480-YUYV/未设置 调试：管道状态从 NULL 变为 READY。 调试：管道状态从就绪变为暂停。 调试：管道状态从暂停变为播放。 结果：边界框错乱。 CPU 模式——相同的流水线，不同的模型和委托 CAMERA_BACKEND=libcamera \ LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c' \ /opt/gopoint-apps/scripts/machine_learning/nnstreamer/face_detection/example_face_detection_tflite \ --后端 CPU \ --model_path downloads/models/face-detection/ultraface_slim_uint8_float32.tflite \ --display_perf 时间 日志： 信息：启动应用程序... 信息：已为 CPU 创建 TensorFlow Lite XNNPACK 委托。 调试信息：[相同的相机流程，相同的 imxvideoconvert_g2d] ... tensor_converter！tensor_filter latency=1 framework=tensorflow-lite \ model=downloads/models/face-detection/ultraface_slim_uint8_float32.tflite \ custom=Delegate:XNNPACK,NumThreads:6 ... 调试：管道状态已更改……正在播放。 结果： ✅ 边界框准确。 相同的流程，相同的摄像机，相同的 imxvideoconvert_g2d YUY2→RGB 转换。唯一区别：量化的 .tflite+ XNNPACK 与 _neutron.tflite + neutron 委托。 --- 问题 2：目标检测（SSD MobileNetV2） 神经网络处理单元模式 CAMERA_BACKEND=libcamera \ LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c' \ /opt/gopoint-apps/scripts/machine_learning/nnstreamer/object_detection/example_detection_mobilenet_ssd_v2_tflite \ --后端 NPU \ --model_path downloads/models/object-detection/ssdlite_mobilenet_v2_coco_quant_uint8_float32_no_postprocess_neutron.tflite \ --labels_path downloads/models/object-detection/coco_labels_list.txt \ --boxes_path downloads/models/object-detection/box_priors.txt \ --display_perf 时间 管道日志： 信息：启动应用程序... 调试：libcamerasrc name=cam_src camera-name=/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c \ ！video/x-raw,width=640,height=480,framerate=30/1,format=YUY2 !队列 ！tee name=t \ t.！队列名称=thread-nn 最大缓冲区大小=2 泄漏=2 \ ！imxvideoconvert_g2d name=scale_csc_g2d_0 ！video/x-raw,width=300,height=300,format=RGB \ ！张量转换器！tensor_filter latency=1 framework=tensorflow-lite \ model=downloads/models/object-detection/ssdlite_mobilenet_v2_coco_quant_uint8_float32_no_postprocess_neutron.tflite \ custom=Delegate:External,ExtDelegateLib:libneutron_delegate.so name=detection_filter \ ！tensor_decoder name=tensor_decode_bounding_boxes_1 mode=bounding_boxes option1=mobilenet-ssd \ option2=downloads/models/object-detection/coco_labels_list.txt \ option3=downloads/models/object-detection/box_priors.txt \ 选项4=640:480 选项5=300:300 ！imxvideoconvert_g2d！mix.sink_0 \ t.！队列名称=thread-img 最大缓冲区大小=2 泄漏=2 ！mix.sink_1 \ imxcompositor_g2d name=mix sink_0::zorder=2 sink_1::zorder=1 latency=20000000 min-upstream-latency=20000000 \ ！cairooverlay 名称=perf！fpsdisplaysink name=img_tensor text-overlay=false video-sink=waylandsink 信息：NeutronDelegate 委托：26 个节点中有 1 个节点被委托，共 1 个分区。 信息：Neutron 委托版本：v1.0.0-f24d08e5，非零cp。 相机 camera.cpp:1215配置流：（0）640x480-YUYV/未设置 调试：管道状态已更改……正在播放。 结果：摄像头画面区域完全黑屏。边界框不准确。 CPU 模式——相同的流水线，不同的模型和委托 CAMERA_BACKEND=libcamera \ LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c' \ /opt/gopoint-apps/scripts/machine_learning/nnstreamer/object_detection/example_detection_mobilenet_ssd_v2_tflite \ --后端 CPU \ --model_path downloads/models/object-detection/ssdlite_mobilenet_v2_coco_quant_uint8_float32_no_postprocess.tflite \ --labels_path downloads/models/object-detection/coco_labels_list.txt \ --boxes_path downloads/models/object-detection/box_priors.txt \ --display_perf 时间 日志： 信息：启动应用程序... 信息：已为 CPU 创建 TensorFlow Lite XNNPACK 委托。 调试：[相同的管道，相同的 imxvideoconvert_g2d，相同的 imxcompositor_g2d，XNNPACK 代理] 调试：管道状态已更改……正在播放。 结果：摄像头画面区域仍然完全是黑色的（与 NPU 相同）。边界框正确。 CPU和NPU均出现黑屏。人脸检测和分类（不使用 imxcompositor_g2d）显示正常的摄像头画面。 --- 问题 3：分类（MobileNetV1） 神经网络处理单元模式 CAMERA_BACKEND=libcamera \ LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c' \ /opt/gopoint-apps/scripts/machine_learning/nnstreamer/classification/example_classification_mobilenet_v1_tflite \ --后端 NPU \ --model_path downloads/models/classification/mobilenet_v1_1.0_224_quant_uint8_float32_neutron.tflite \ --labels_path downloads/models/classification/labels_mobilenet_quant_v1_224.txt \ --display_perf 时间 管道日志： 信息：启动应用程序... 调试：libcamerasrc name=cam_src camera-name=/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c \ ！video/x-raw,width=640,height=480,framerate=30/1,format=YUY2 !队列 ！tee name=t \ t.！队列名称=thread-nn 最大缓冲区大小=2 泄漏=2 \ ！imxvideoconvert_g2d name=scale_csc_g2d_0 ！video/x-raw,width=224,height=224,format=RGB \ ！张量转换器！tensor_filter latency=1 framework=tensorflow-lite \ model=downloads/models/classification/mobilenet_v1_1.0_224_quant_uint8_float32_neutron.tflite \ custom=Delegate:External,ExtDelegateLib:libneutron_delegate.so name=classification_filter \ ！张量解码器名称=tensor_decode_labeling_1 模式=图像标注 \ option1=downloads/models/classification/labels_mobilenet_quant_v1_224.txt ！overlay.text_sink\ t.！队列名称=thread-img 最大缓冲区大小=2 泄漏=2 \ ！textoverlay name=overlay font-desc="Sans, 24" valignment=baseline halignment=center \ ！imxvideoconvert_g2d！cairooverlay name=perf \ ！fpsdisplaysink name=img_tensor text-overlay=false video-sink=waylandsink 信息：NeutronDelegate 委托：4 个节点中有 1 个节点被委托，共 1 个分区。 信息：Neutron 委托版本：v1.0.0-f24d08e5，非零cp。 相机 camera.cpp:1215配置流：（0）640x480-YUYV/未设置 调试：管道状态已更改……正在播放。 结果：摄像头画面正常。标签始终错误。 CPU 模式——相同的流水线，不同的模型和委托 CAMERA_BACKEND=libcamera \ LIBCAMERA_CAM_DEVICE='/base/soc/bus@42000000/i2c@42530000/ov5640_mipi@3c' \ /opt/gopoint-apps/scripts/machine_learning/nnstreamer/classification/example_classification_mobilenet_v1_tflite \ --后端 CPU \ --model_path downloads/models/classification/mobilenet_v1_1.0_224_quant_uint8_float32.tflite \ --labels_path downloads/models/classification/labels_mobilenet_quant_v1_224.txt \ --display_perf 时间 日志： 信息：启动应用程序... 信息：已为 CPU 创建 TensorFlow Lite XNNPACK 委托。 调试信息：[相同的管道，相同的 imxvideoconvert_g2d，XNNPACK 代理] 调试：管道状态已更改……正在播放。 结果： ✅ 摄像头画面正常。标签正确且能根据摄像机画面做出响应。 --- 摘要 在这三个演示中，CPU 和 NPU 都使用相同的相机管线、相同的 imxvideoconvert_g2d YUY2→RGB 转换以及相同的 GStreamer 管线结构。唯一的区别在于： | 变量 | CPU 测试 | NPU 测试 | |----------|----------|----------| | 模型 | *.tflite（量子化） | *_neutron.tflite | | 委托 | XNNPACK (委托:XNNPACK) | neutron (委托:External,ExtDelegateLib:libneutron_delegate.so)| 结果： | 演示 | CPU（量化 .tflite）+ XNNPACK) | NPU (_neutron.tflite + neutron) | |------|:---:|:---:| 人脸检测——边界框 | ✅ 正确 | ❌ 乱码 | | 目标检测 — 边界框 | ✅ 正确 | ❌ 不准确 | | 分类 — 标签 | ✅ 正确 | ❌ 错误 | 目标检测结果显示，CPU 和 NPU 中的摄像头画面均为黑色。此演示使用 imxcompositor_g2d 进行显示；人脸检测和分类使用 cairooverlay/textoverlay 并正常显示。 Re: i.MX 95 NNStreamer C++ Demo NPU Issues 嗨@Chavira ： 板级支持包（BSP）版本为6.12.49 。我通过 Yocto 单独构建了nxp-nnstreamer-examples (SRCREV: 062ebd1 )，然后将编译好的 deb 部署到目标板上。我没有通过 GoPoint 应用程序启动演示程序，而是根据随附的downloads.json文件手动下载了模型文件。并使用前面提到的命令运行程序。 Re: i.MX 95 NNStreamer C++ Demo NPU Issues 嗨@BIG_FLY ， 感谢您提供的有关 GoPoint 演示的信息。 请问您能否详细说明一下您是如何运行演示的？ 您是直接使用 GoPoint 应用程序运行这些程序，还是自己交叉编译的？ 您能否一步一步地描述一下您那边是如何进行演示的？ 您使用的是 电路板支持包。 版本 6.12.49 吗？ 你用的是哪款板？ 这些信息将有助于我们更好地了解您的设备配置并发现任何潜在问题。 此致， 查维拉

[S32K358] HSM、RTD対応バージョン（S32K358） 親愛なるNXP s32k358におけるHSM、RTDのバージョンは何ですか？ ありがとう、 ブライアン Re: [S32K358] Version for HSM, RTD on s32k358 こんにちは、 @bryan_hong さん。 RTDおよびHSEファームウェアは最新バージョンを使用することをお勧めします。つまり、次のようになるということです。 - S32K358用HSEファームウェア バージョン0.2.55.0 - RTD 7.xx リリースノートにもあるように、RTD 7.x.xのCryptoドライバはHSEファームウェア0.2.55.0でテストされています。 よろしくお願いいたします。 ルーカス Re: [S32K358] Version for HSM, RTD on s32k358 こんにちは、ルーカス。 コメントありがとうございます。とても参考になりました。 ありがとう、 ブライアン    

RT1064 400kHzでのI2C通信異常 RT1064デバイスのI2C2インターフェースはモジュールAに接続されます。通信異常は400kHzで発生しますが、100kHzでは正常に動作します 1. 同じシリーズ内の異なるモデルのモジュールBを400kHzで接続することは問題ありません 2. 波形の観点からは、ホストクロックが伸縮され、モジュールAに接続された後に復元される異常に相当します 追伸:デバイスのI2Cドライバーポートを別の1064デバイスに実装し、モジュールAをテストしましたが、400kで問題ありません その理由は何でしょうか? 1. 図1 モジュールA ロジックアナライザの400kHzにおける異常波形 2. 図2：モジュールAの100kHzにおけるロジックアナライザの波形 3. 図3：モジュールBの400kHzにおける波形 i.MXRT 106x Re: RT1064 I2C communication abnormality at 400kHz こんにちは、 @foreverwlh2025 さん。 追加のご説明ありがとうございます。これは非常に重要な指摘です。   あなたの観察からすると、問題はモジュールA自体の異常というよりも、2段ADUM1251アイソレーションリンクによる400 kHz I2Cのタイミングマージン不足に関連している可能性が高いようです。 ライズ時間が規格内であっても、RT1064ではLPI2Cマスター側の400kHz構成、特にMCFGR2[FILTSCL/FILTSDA]およびMCCR0/MCCR1の確認を推奨します。なぜなら、RT1064のマスター同期レイテンシはライズ時間だけでなく、デジタルフィルターやタイミングパラメータ設定にも影響を受けるからです。 プロジェクトで実際に使用されている構成を読み、RT1064リファレンスマニュアル第47章の表47-5「LPI2C例タイミング構成」と比較することをお勧めします。 特に、選択したクロック条件における以下の設定が、サンプル値と一致しているかどうかを確認してください。 I2Cモジュールクロックソース 目標ボーレート：400Kbps PRESCALE FILTSCL / FILTSDA セソルド クロックロ CLKHI データビデオ お役に立てれば幸いです。 よろしくお願いいたします。 5月 Re: RT1064 I2C communication abnormality at 400kHz 追加情報として、昨日ポジショニングにいくつかの進展がありました: ハードウェア拡張は以下の通りです: マザーボード:RT1064--- ADUM1251 3.3V～5V サブボード：ADUM1251 - モジュールA 5V～3.3V 検証の結果、ハードウェアリンクの2層にADUM1251を追加した後、モジュールAで通信異常が発生したことが判明した。しかし、ADUM1251を取り外すと、400kで通信が正常に戻った。その理由は何でしょうか? 追伸:ハードウェアエンジニアは、ADUM1251は通信レイテンシを増加させるだけで、それ以外には影響がないと考えています Re: RT1064 I2C communication abnormality at 400kHz こんにちは、@mayliu1 当社の製品はまもなくリリースされ、数日間この問題を調査してきました。できるだけ早くご返信いただければ、大変ありがたいです! Re: RT1064 I2C communication abnormality at 400kHz ハイ 補足情報 1.2人のハードウェアエンジニアはオシロスコープで問題の波形を確認し、上昇時間は100+ns以内の要件を満たしました 2. I2Cの初期化および読み書き機能ドライバを別のタイプのRT1064デバイスに移植し、モジュールAを問題なくテストしました 以下の図は、別のデバイスモジュールAの波形を示しています。テスト用ロジックアナライザー 疑い： 1.ストレッチ後に時計が異常に回復するなら、他にどんな理由が考えられますか 2. 前回の返信で言及されたMCFGR2のような設定設定専用機能はありますか?I2C初期化プロセスで設定するインターフェースは見当たりませんでした ----上昇時間が満たされた場合、これらのレジスタ設定を考慮する必要はないのでしょうか? Re: RT1064 I2C communication abnormality at 400kHz こんにちは、 @foreverwlh2025 さん、 私たちの製品にご関心を寄せ、コミュニティをご利用いただき、本当にありがとうございます。 これはモジュールAの問題ではなく、その特定のRT1064 LPI2C2バスの400 kHzのタイミングマージンの問題だと思います。 RT1064では、LPI2Cのタイミングはバスの上昇時間、バス負荷、プルアップ抵抗、グリッチフィルタ レイテンシの影響を受けます。 リファレンス・マニュアルRT1064RMでは、上昇時間が長いと同期レイテンシが増加すると説明されています。（第47.3.1.4章を参照）タイミングパラメータ） マスターグリッチフィルターMCFGR2[FILTSCL/FILTSDA]は、**レイテンシ**がSCLの最低ロー/ハイ期間を下回るように設定されなければならず、RT1064はMCCR0/MCCR1の400 kbpsタイミング設定の例を提供しています。表47-5をご確認ください。LPI2Cのタイミング構成例 したがって、モジュールAがバスエッジをわずかに遅くしたり、実効負荷を変えたりすると、バスは400kHzで故障しても100kHzでは動作し続けることがあります。 お役に立てれば幸いです。 よろしくお願いいたします。 5月 Re: RT1064 I2C communication abnormality at 400kHz 10 MHzのLPI2C機能クロックは、RT1064リファレンスマニュアルの400 kbpsのタイミング設定例には記載されていません。 このクロックを使用すれば400kbpsのボーレートを生成することは可能ですが、自動生成されるタイミングパラメータは、特にtLOW、tHIGH、セットアップ/ホールドタイミング、およびデータ有効タイミングに関して、I2C仕様と照らし合わせて慎重に検証する必要があります。 デザインリスクを減らすために、リファレンス・マニュアルに示されている48 MHzなどの検証済みクロックソースを使用することが推奨されています。 Re: RT1064 I2C communication abnormality at 400kHz 以下は印刷設定です。どのパラメータを調整する必要があるでしょうか？ 追伸:どうやら自動インターフェース割り当てによるようです Re: RT1064 I2C communication abnormality at 400kHz 60MHzと8MHzの両方を変更してみましたが、それでもうまくいきませんでした。下図の赤い枠で囲まれた部分は、修正後に印刷された値を示しており、マニュアルに記載されている値とは異なっています。 Re: RT1064 I2C communication abnormality at 400kHz こんにちは、 @foreverwlh2025 さん。 I2Cクロックを設定する方法はいくつかあります。 提案として、8 MHzと60 MHzを試してみるのも良いでしょう。この2つのクロック設定は比較的簡単に達成できます。 SDKのデモを使っています: 「evkmimxrt1064_lpi2c_edma_b2b_transfer_master」 方法1：LPI2Cクロックソースを60MHzに設定する 時計の分周器を0に設定するだけです。 方法2：LPI2Cクロックソースを8MHzに設定する MCUXpresso IDEsクロックツールを使い、以下の通りに設定してください。クロックソースとしてOSC_CLKを選択し、分周器を3に設定すると、LPI2C（I2C）モジュール用の8MHzクロックが生成されます。 お役に立てれば幸いです。 よろしくお願いいたします。 5月 Re: RT1064 I2C communication abnormality at 400kHz 現在のI2Cクロックは、SDK2_13_0-EVK-MIMXRT1064 \ ボード \ evkmimxrt1064 \ river_deamples \ lpi2cディレクトリ内のサンプル構成に基づいて構成されています。 #define LPI2C_CLOCK_SELECT(0U) #define LPI2C_CLOCK_DIVIDER(5U) CLOCK_SetMux(kCLOCK_Lpi2cMux、LPI2C_CLOCK_SELECT); CLOCK_SetDiv(kCLOCK_Lpi2cDiv、LPI2C_CLOCK_DIVIDER); ---正確な8MHzか48MHzをどうやって修正すればいいですか?（時計の木が見えないようですね） Re: RT1064 I2C communication abnormality at 400kHz こんにちは、 @foreverwlh2025 さん。 レジスタを直接設定してみるのも良いでしょう。 例えば、60 MHzのI2Cクロックを使用する場合、以下の構成を適用できます。 お役に立てれば幸いです。 よろしくお願いいたします。 5月 Re: RT1064 I2C communication abnormality at 400kHz 図に示すように、パラメータに対応するようにレジスタ設定を変更しようとしましたが、60MHzでは改善がありませんでした。良いモジュールでも8MHzでは正常に動作しません

S32K144チップにはクロック構成の問題があり、クロックを変更するとタイミング周期が変わってしまう。 S32K144の開発中に、以下の問題に遭遇しました。 初期化タイマーの割り込みオーバーフロー期間は1秒に設定する必要があります。 前提として、私のクロック設定は8MHzです。 しかし、時計を20Mの時計に変えた後… タイマーのオーバーフロー期間が1秒ではなく、400ミリ秒になっていることに気づきました。 しかし、タイマーのクロック設定は依然として8MHzの内部クロックに設定されたままです。 PCC->PCCn[PCC_FTM1_INDEX] |= PCC_PCCn_PCS(0x01) /* クロックソース=1、8 MHz SIRCDIV1_CLK */ | PCC_PCCn_CGC_MASK; /* FTMレジスタのクロックを有効にする */ この問題の原因となっている設定上の問題が何なのか、私には分かりません。 Re: S32K144芯片的时钟配置问题，更改时钟后定时周期出现变化 ハイ 次の S32K1 RM の表 27-9 を参照してください。peripheral module clocking (continued),FTM具体選択哪个时钟源需要查看FTMn_SC[CLKS]和29.6.17 PCC FTM1 Register (PCC_FTM1)的PCS位。 プロセッサ エキスパートがコンフィギュレーションを生成し、ベアメタル モードでレジスタを直接操作しました。SDK サイトを使用した API が原因でベアメタル プログラムがクラッシュしたかどうかはわかりません。 さらに、ProcessorExpert 搭載 SDK の API を使用する場合は、ベアメタルの直接操作レジスタの構築リファレンス S32K144_Project_FTM サンプル ftm_periodic_interrupt_s32k144 を参照してください。 よろしくお願いいたします ロビン

如何通过 I2C 从 NTP5332 读取 UID 我有一个问题，如何通过 I2C 接口从 NTP5332 读取 UID？我在数据手册中没有找到 UID 的块地址。 Re: How to read UID from NTP5332 through I2C Hello @zhjyang  UID 是芯片内部唯一标识，不在任何 memory block 中，只能通过 NFC接口RF 命令读取,比如 INVENTORY （ISO15693）

EMIOS Pwm tooling error Emios 0 ch 255 in MCL I am trying to run trapezoidal motor control using S32K312 mini development board.  After porting the initialisation, I get the following error :  Issue: [Generation error] Please configure the counter bus EMIOS_0_CH_255 in MCL Level: Error Type: Tool problem Tool: Peripherals Origin: Peripherals Resource: Sources Information: [Generation error] Please configure the counter bus EMIOS_0_CH_255 in MCL My setup has : EMIOS mcl  initialises 0 and 1  for  EMIOS0 - Channel 0 -> PWM time base EMIOS1 - Channel 23 -> Time base for Hall pulse counter EMIOS pwm for  EMIOS0 Channel 1 as OPWMB for PWM 20KHz EMIOS Channel 3 as OPWMB for PWM pulse  Both the channels are based out od EMIOS Channel 0 in BCD mode.  Re: EMIOS Pwm tooling error Emios 0 ch 255 in MCL Here is a mex file. Re: EMIOS Pwm tooling error Emios 0 ch 255 in MCL Hi @ArunnK  I have tried applying the configuration you mentioned for Emios_Mcl and Emios_Pwm in the FreeRTOS_Toggle_Example_S32K312 (RTD 7.0.0 with FreeRTOS 7.0.0), and I have not been able to reproduce the errors on my side. Would you mind sharing your .mex file? It would also be really helpful if you could outline the steps you followed, so I can try to replicate the same behavior here. BR, VaneB Re: EMIOS Pwm tooling error Emios 0 ch 255 in MCL Hi @ArunnK  Thank you for sharing your .mex file. I imported it into the FreeRTOS_Toggle_Example_S32K312 (RTD 7.0.0 with FreeRTOS 7.0.0) project I previously used, and the error did not appear. To make sure we are following the same steps, could you please try the following: Delete the current example project and recreate. Update the code as needed to ensure everything is correct. Once the configurations are successfully generated, go to File → Import → S32 Configuration Tools → Import Configuration (*.mex). Select the .mex file you shared and merge it into the current configuration. After that, does the error still appear? And just to be sure, please double-check that all the software versions you are using are compatible.

imx93 sai - simple-audio-card devicetree settings Hi, I am searching for the device tree settings of the simple-audio-card for: -imx93 is the Master -Audio Codec is Slave TDM 16 Slots / 32 Bit and the following timing should be fullfilled: Any hints are appreciated Linux Re: imx93 sai - simple-audio-card devicetree settings Hello, Unfortunately, we do not have device tree examples to configure SAI port as slave in TDM for i.MX93. You could use this post as reference: https://community.nxp.com/t5/i-MX-Processors/How-should-I-write-a-dts-file-to-use-16ch-TDM-with-quot-simple/m-p/1625768#M203519 Best regards.

How to read UID from NTP5332 through I2C I have a question, how to read UID from NTP5332 through I2C interface? I don't see the block address for UID in the datasheet Re: How to read UID from NTP5332 through I2C Hello @zhjyang The UID is a unique identifier within the chip; it is not stored in any memory block and can only be read via NFC interface RF commands, for example... INVENTORY (ISO15693)

RT1064 I2C 通信异常，频率为 400kHz RT1064 设备的 I2C2 接口连接到模块 A。在 400kHz 频率下出现通信异常，但在 100kHz 频率下工作正常。 1. 将同一系列中不同型号的模块 B 以 400kHz 的频率连接没有问题。 2. 从波形上看，这相当于主机时钟在连接到模块 A 后被拉伸然后恢复时发生的异常情况。 PS：将该设备的 I2C 驱动程序移植到另一台 1064 设备上，测试模块 A，在 400k 功耗下未发现问题。 原因可能是什么？ 图 1 模块 A 逻辑分析仪在 400kHz 下的异常波形 图 2：模块 A 在 100kHz 下的逻辑分析仪波形 图3：模块B在400kHz时的波形 i.MX RT106x Re: RT1064 I2C communication abnormality at 400kHz 你好@foreverwlh2025 ， 感谢您的进一步说明——这是一个非常重要的发现。   根据您的观察，该问题似乎更有可能是由于两级 ADUM1251 隔离链路导致的 400 kHz I2C 时序裕量不足，而不是模块 A 本身的异常。 即使上升时间在规格范围内，在 RT1064 上，我们仍然建议检查 LPI2C 主侧 400 kHz 配置，特别是 MCFGR2[FILTSCL/FILTSDA] 和 MCCR0/MCCR1，因为 RT1064 上的主同步延迟不仅受上升时间的影响，还受数字滤波器和定时参数设置的影响。 我们建议您阅读项目中实际使用的配置，并将其与 RT1064 参考手册第 47 章中的表 47-5“LPI2C 示例时序配置”进行比较。 请特别检查以下设置是否与您所选时钟条件的示例值相符： I2C模块时钟源 目标波特率：400Kbps 预分频 FILTSCL/FILTSDA SETHOLD CLKLO CLKHI DATAVD 希望对你有帮助 顺祝商祺！ 5月 Re: RT1064 I2C communication abnormality at 400kHz 补充信息：昨天在定位方面取得了一些进展： 我们的硬件扩容计划如下： 主板：RT1064--- ADUM1251 3.3V 至 5 V 子板：ADUM1251-模块A 5V转3.3V 经验证，在硬件链路的两层中添加 ADUM1251 后，模块 A 的通信出现异常。但移除 ADUM1251 后，通信在 400k 处恢复正常。造成这种情况的原因可能是什么？ PS：我们的硬件工程师认为 ADUM1251 只会增加通信延迟，不会产生其他影响。 Re: RT1064 I2C communication abnormality at 400kHz 你好，@mayliu1 我们的产品即将发布，我们已经调查这个问题好几天了。如果您能尽快回复，我们将不胜感激！ Re: RT1064 I2C communication abnormality at 400kHz HI 补充信息 1.我们的两位硬件工程师使用示波器检查了故障波形，上升时间符合要求，在 100ns 以上。 2. 我将 I2C 初始化和读写功能驱动程序移植到另一种 RT1064 设备，并测试了模块 A，没有发现任何问题。 下图显示了另一个设备模块 A 的测试逻辑分析仪的波形。 怀疑： 1.如果时钟在拉伸后恢复异常，还有哪些其他原因可能导致这种情况？ 2. 是否有专门的功能来设置上次回复中提到的 MCFGR2 等设置？我没有看到在 I2C 初始化过程中需要设置任何接口。 ----如果上升时间满足要求，我们是否就不需要考虑这些寄存器设置了？ Re: RT1064 I2C communication abnormality at 400kHz 嗨@foreverwlh2025 ， 非常感谢您对我们产品的关注以及对我们社区的使用。 我认为这很可能不是 A 模块的问题，而是该特定 RT1064 LPI2C2 总线上的 400 kHz 时序裕量问题。 在 RT1064 上，LPI2C 时序受总线上升时间、总线负载、上拉电阻和毛刺滤波器延迟的影响。 RT1064RM 参考手册指出，上升时间越大，同步延迟就越高。（参见第 47.3.1.4 章）时序参数） 主故障滤波器 MCFGR2[FILTSCL/FILTSDA] 必须设置，使其延迟保持在最小 SCL 低/高周期以下，RT1064 在 MCCR0/MCCR1 中提供了 400 kbps 定时设置的示例。请查看表 47-5。LPI2C 示例时序配置 因此，如果模块 A 使总线边沿稍微变慢或改变有效负载，则总线可能在 400 kHz 时发生故障，但在 100 kHz 时仍然可以工作。 希望对你有帮助 顺祝商祺！ 5月 Re: RT1064 I2C communication abnormality at 400kHz RT1064 参考手册中没有列出 400 kbps 的 10 MHz LPI2C 功能时钟。 虽然可以使用此时钟生成 400 kbps 波特率，但应根据 I2C 规范仔细验证自动生成的定时参数，特别是 tLOW、tHIGH、建立/保持定时和数据有效定时。 为降低设计风险，建议使用经过验证的时钟源，例如 48 MHz，如参考手册所示。 Re: RT1064 I2C communication abnormality at 400kHz 以下是打印配置。可能需要调整哪个参数？ PS：显然是由于自动接口分配造成的 Re: RT1064 I2C communication abnormality at 400kHz 你好@foreverwlh2025 ， 您可以尝试直接设置寄存器。 例如，当使用 60 MHz I2C 时钟时，可以采用以下配置。 希望对你有帮助 顺祝商祺！ 5月 Re: RT1064 I2C communication abnormality at 400kHz 当前的 I2C 时钟是基于 SDK2_13_0-EVK-MIMXRT1064 板 \ boards \ evkmimxrt1064 \ river_deamples \ lpi2c 目录中的示例配置进行配置的。 #define LPI2C_CLOCK_SELECT (0U) #define LPI2C_CLOCK_DIVIDER (5U) CLOCK_SetMux(kCLOCK_Lpi2cMux, LPI2C_CLOCK_SELECT); CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_DIVIDER); 我该如何修改才能获得精确的 8MHz 或 48MHz 频率？（时钟树似乎看不见） Re: RT1064 I2C communication abnormality at 400kHz 我尝试将频率修改为 60MHz 和 8MHz，但仍然无效。下图中的红色方框显示的是修改后打印的值，这些值与手册中的值不同。 Re: RT1064 I2C communication abnormality at 400kHz 你好@foreverwlh2025 ， 配置 I2C 时钟有多种方法。 建议您尝试 8 MHz 和 60 MHz，因为这两个时钟设置相对容易实现。 我正在使用 SDK 演示版： "evkmimxrt1064_lpi2c_edma_b2b_transfer_master" 方法一：将 LPI2C 时钟源配置为 60 MHz 只需将时钟分频器设置为 0 即可。 方法二：将 LPI2C 时钟源配置为 8 MHz 使用 MCUXpresso IDE 时钟工具并按如下所示进行配置。选择 OSC_CLK 作为时钟源，并将分频器设置为 3，这将为 LPI2C (I2C) 模块生成 8 MHz 时钟。 希望对你有帮助 顺祝商祺！ 5月 Re: RT1064 I2C communication abnormality at 400kHz 如图所示，我尝试修改寄存器设置以匹配参数，但在 60MHz 下性能没有提升；即使是性能良好的模块在 8MHz 下也无法正常工作。

UJA1169ATK/F/3 I'm using UJA1169ATK/F/3 connected to a S32K146 CPU on FlexCAN1. The UJA1169ATK/F/3 is used in Partial Networking with WakeUp Frame (no FD!) to wakeup the whole system from a deep sleep mode. Actually every thing works correctly if a valid Frame is sent within the CAN BUS (for valid Frame a mean a frame which is compatible with the filtering masks selected). The problem arise when an unwanted Frame (i.e. a frame, non FD, which is syntactically correct but do not pass the WUP filtering in use) is sent. What happen is that, quit often, if one such frame is sent, than any successive valid Frame does not wakeup the transceiver any more. It seems that, when an unwanted Frame, often, locks the capability of the UJA1169ATK/F/3 to correctly recognize valid Frames and hence to wakeup. At first i suppose the problem could be something on the bus which generate a bus error which in turns switch the UJA1169ATK/F/3 in reset mode without moving RX signal and thus without advise CPU. But this is not the case, since i used a CAN monitor and no bus error are recorded (note that i use a Windows application to generate messages on CAN BUS and another application to monitor the bus; both application use separate USB/CAN converter). Do you have any idea of which could be the problem ? Re: UJA1169ATK/F/3 Hello Michele, The behavior you describe is most likely related to the internal PN error handling of the UJA1169A. The device maintains an internal frame detection error counter. If a sequence of frames is received that do not match the configured PN filters (or are interpreted as invalid in PN evaluation), this counter can overflow and trigger a PN frame detection error (PNFDE). Once this condition occurs, the SBC may temporarily stop correctly recognizing valid wake-up frames, which could explain why subsequent valid frames no longer wake the device. I recommend checking the PNFDE status bit and verifying the PN configuration (ID/mask, DLC, data mask and data rate settings). As a debug step, you can try disabling data field evaluation (PNDM = 0) to determine whether the issue is related to data filtering. Please let me know the observed PNFDE state and PN configuration so I can further support your analysis. BRs, Tomas

MCUXpressoで「転送送信」が有効になっている場合に、無効なeDMAコードが生成される（MCXN547） こんにちは、 MCUXpresso Config Tools v26.xをMCXN547プロジェクトで使用し、eDMAペリフェラルコンポーネントを使ってADC -> eDMA転送を設定しています。 構成： eDMAチャネルAPIモード:トランザクション(転送設定) eDMAリクエスト: ADC1 FIFO Aリクエスト 送金送信：有効 自動停止リクエスト:有効 周辺要求:有効 peripherals.cで生成されたコード には以下が含まれます: status = EDMA_SubmitTransfer(&DMA0_CH0_Handle, DMA0_CH0_Transfers_config, 1U); assert(status == kStatus_Success); しかし、ステータスの宣言は生成されません。その結果、プロジェクトはコンパイルに失敗します。 error: 'status' undeclared (first use in this function) 生成されるコードは以下のいずれかになります。 status_t status; status = EDMA_SubmitTransfer(...); または： assert(kStatus_Success == EDMA_SubmitTransfer(...)); この問題に遭遇したことがある方はいらっしゃいますか？ これはConfig Toolsにおける既知のコード生成バグでしょうか、それとも「転送を送信」を使用する際に必要な追加の設定オプションがあるのでしょうか？ 必要に応じて生成されたペリフェラル.cと.mexの設定も提供できます。 ありがとうございます。 ボード設計 MCX N Re: MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) ハイ 迅速なご対応ありがとうございます。 はい、ツールのバージョン26.03を持っています。 プロセッサー: MCXN547(2020年3月26日) - MCX MCXN MCUXpresso SDK バージョン 25.13.00 パッケージ:mcuxsdk-core バージョン:2.0.0 DMA0転送構成の「すべての転送をループ」に、このコードをDMA0_init()に追加します。 /* DMA0 ループ転送送信 */ status = EDMA_SubmitLoopTransfer(&DMA0_CH0_Handle, DMA0_CH0_Transfers_config, 1U); assert(status == kStatus_Success); 「ステータス」がどこにも宣言されていない場合。 Re: MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) こんにちは、 @tjo_dkさん。 投稿ありがとうございます！ どのMCXN547パッケージを使っているのか教えていただけますか? 使用しているConfig Toolsのバージョンは何ですか？26.03でしょうか？ どのSDKバージョンをインストールしていますか? 私の環境で同様の設定を行うために、この情報を共有してください。 Re: MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) こんにちは、 @tjo_dk さん。 あなたと同じ構成で、同様の問題を再現しようと試みました。しかし、私の環境では、コードプレビューにはすでにDMA0_init関数内でステータス変数の宣言が含まれています。

The S32K144 chip has a clock configuration issue; the timing period changes after the clock is modified. I encountered the following problem during the development of S32K144: The initialization timer's interrupt overflow period should be 1 second. The premise is that my clock configuration is 8MHz. However, after I changed the clock to a 20M clock... I discovered that my timer overflow period is no longer 1 second, but has become 400 milliseconds. However, my timer clock selection is still set to the 8MHz internal clock. PCC->PCCn[PCC_FTM1_INDEX] |= PCC_PCCn_PCS(0x01) /* Clock src=1, 8 MHz SIRCDIV1_CLK */ | PCC_PCCn_CGC_MASK; /* Enable clock for FTM regs */ I'm not sure what configuration issue is causing this problem. Re: S32K144芯片的时钟配置问题，更改时钟后定时周期出现变化 Hi 建议看一下S32K1 RM的Table 27-9. Peripheral module clocking (continued)，FTM具体选择哪个时钟源需要查看FTMn_SC[CLKS]和29.6.17 PCC FTM1 Register (PCC_FTM1)的PCS位。 你用Processor Expert生成配置，又用baremetal方式直接操作寄存器。我不确定是否是因为调用了SDK里的API导致和你的baremetal程序冲突了。 建议debug情况下直接检查上述两个寄存器。 顺便提一句，baremetal直接操作寄存器的话建议参考S32K144_Project_FTM例程，如果想用ProcessorExpert 搭配SDK的API则建议参考ftm_periodic_interrupt_s32k144例程。 Best Regards, Robin

IMX93 SAI - シンプルオーディオカードデバイスツリー設定 こんにちは、simple-audio-cardのデバイスツリー設定を探しています: -imx93 はマスターです -オーディオコーデックはスレーブTDM 16スロット/32ビット そして、以下のタイミングが守られる必要があります。 どんなヒントでもありがたいです Linux Re: imx93 sai - simple-audio-card devicetree settings こんにちは、 残念ながら、i.MX93のTDMでSAIポートをスレーブとして構成するためのデバイスツリーの例は提供しておりません。 参考文献としては以下の投稿を参考にしてください: https://community.nxp.com/t5/i-MX-Processors/How-should-I-write-a-dts-file-to-use-16ch-TDM-with-quot-simple/mp/1625768#M203519 よろしくお願いいたします。

S32K144芯片的时钟配置问题，更改时钟后定时周期出现变化 我在开发S32K144过程中遇到了如下问题： 这个定时器的初始化  计数中断溢出周期应该是1s   前提是我的  时钟配置是8M的时钟 但是当我更改时钟为  20M的时钟之后 我发现我的定时溢出周期  不是1s了  而变成了400ms    但是我的  定时器  时钟选择还是  8M的内部时钟   PCC->PCCn[PCC_FTM1_INDEX] |= PCC_PCCn_PCS(0x01) /* Clock src=1, 8 MHz SIRCDIV1_CLK */ | PCC_PCCn_CGC_MASK; /* Enable clock for FTM regs */ 我不清楚是哪里没有配置导致这个问题出现 Re: S32K144芯片的时钟配置问题，更改时钟后定时周期出现变化 HI 建议看一下S32K1 RM的表27-9。外设模块时钟（续），FTM具体选择哪个时钟源需要查看FTMn_SC[CLKS]和29.6.17 PCC FTM1寄存器（PCC_FTM1）的PCS位。 您用Processor Expert生成配置，又用裸机方式直接操作注册。我是否不确定是因为调用了SDK里的API导致和您的裸机程序冲突了。建议调试情况下直接检查上述两个注册。 顺便提一下，baremetal直接操作注册的话建议参考S32K144_Project_FTM例程，如果想用ProcessorExpert搭配SDK的API则建议参考ftm_periodic_interrupt_s32k144例程。 此致敬礼， Robin

UJA1169ATK/F/3 我正在使用连接到 FlexCAN1 上的 S32K146 CPU 的 UJA1169ATK/F/3。UJA1169ATK/F/3 用于部分联网，通过唤醒帧（无 FD！）将整个系统从深度睡眠模式唤醒。 实际上，只要在 CAN 总线上发送有效的帧（有效帧是指与所选过滤掩码兼容的帧），一切都能正常工作。 当发送不需要的帧（即语法正确但未通过 WUP 过滤的非 FD 帧）时，就会出现问题。通常情况下，如果发送了一个这样的帧，那么任何后续的有效帧都不会再唤醒收发器。似乎当出现不需要的帧时，UJA1169ATK/F/3 经常会锁定其正确识别有效帧的能力，从而无法唤醒。 首先我猜测问题可能是总线上的某些东西产生了总线错误，进而导致 UJA1169ATK/F/3 进入 RESET 模式，而没有移动 RX 信号，因此没有通知 CPU。但事实并非如此，因为我使用了 CAN 总线监测器，没有记录到总线错误（请注意，我使用 Windows 应用程序在 CAN 总线上生成消息，并使用另一个应用程序监测总线；这两个应用程序都使用单独的 USB/CAN 变流器）。 您知道问题可能出在哪里吗？ Re: UJA1169ATK/F/3 你好，米歇尔， 您描述的行为很可能与 UJA1169A 的内部 PN 错误处理有关。 该设备维护一个内部帧检测错误计数器。如果接收到的帧序列与配置的 PN 滤波器不匹配（或在 PN 评估中被解释为无效），则此计数器可能会溢出并触发 PN 帧检测错误 (PNFDE)。 一旦出现这种情况，SBC 可能会暂时停止正确识别有效的唤醒帧，这可以解释为什么后续的有效帧不再唤醒设备。 我建议检查 PNFDE 状态位并验证 PN 配置（ID/掩码、DLC、数据掩码和数据速率设置）。作为调试步骤，您可以尝试禁用数据字段评估 (PNDM = 0) 以确定问题是否与数据筛选有关。 请告知我观察到的 PNFDE 状态和 PN 配置，以便我能进一步支持您的分析。 BRs，托马斯

I2C経由でNTP5332からUIDを読み取る方法 質問があります。I2Cインターフェースを通じてNTP5332のUIDをどのように読み取るのでしょうか?データシートにUIDのブロックアドレスが見当たりません Re: How to read UID from NTP5332 through I2C こんにちは、 @zhjyang UIDはチップ内の固有識別子であり、メモリブロックには保存されず、NFCインターフェースのRFコマンドを介してのみ読み取ることができます。 INVENTORY (ISO15693)

RT1064 I2C communication abnormality at 400kHz The I2C2 interface of the RT1064 device connects to Module A. Communication anomalies occur at 400kHz, but it functions properly at 100kHz 1. Connecting module B of a different model within the same series at 400kHz is no problem 2. In terms of waveform, it is equivalent to an anomaly occurring when the host clock is stretched and then restored after connecting to Module A PS: Implement the I2C driver port of the device to another 1064 device, test module A, no issues at 400k What might be the reason？ 1. Figure 1 Module A Abnormal Waveform of Logic Analyzer at 400kHz 2. Figure 2: Waveform of Logic Analyzer for Module A at 100kHz 3. Figure 3: Waveform of Module B at 400kHz i.MXRT 106x Re: RT1064 I2C communication abnormality at 400kHz Hi @foreverwlh2025 , Thanks for the additional clarification — this is a very important observation.   From your observations, the issue appears more likely to be related to insufficient 400 kHz I2C timing margin caused by the two-stage ADUM1251 isolation link, rather than an abnormality of Module A itself. Even if the rise time is within spec, on RT1064, we still recommend checking the LPI2C master-side 400 kHz configuration, especially MCFGR2[FILTSCL/FILTSDA] and MCCR0/MCCR1 , because the master synchronization latency on RT1064 is affected not only by rise time, but also by the digital filter and timing parameter settings. We suggest reading out the actual configuration used in your project and comparing it with Table 47-5, “LPI2C Example Timing Configurations,” in Chapter 47 of the RT1064 Reference Manual . In particular, please check whether the following settings match to the example values for your selected clock condition: I2C module clock source Target baud rate: 400Kbps PRESCALE FILTSCL / FILTSDA SETHOLD CLKLO CLKHI DATAVD Wish it helps you Best Regards May Re: RT1064 I2C communication abnormality at 400kHz Additional information, there was some progress in positioning yesterday: Our hardware expansion is: Motherboard: RT1064--- ADUM1251    3.3 V to 5 V Subboard: ADUM1251- Module A          5v to 3.3v After verification, it was found that after adding ADUM1251 to the two layers of the hardware link, module A had abnormal communication. However, after removing it, communication returned to normal at 400k. What could be the reason for this？ PS: Our hardware engineers believe that ADUM1251 only increases communication latency and has no other impact Re: RT1064 I2C communication abnormality at 400kHz Hi,@mayliu1 Our product is about to be released, and we have been investigating this issue for several days. If we could receive your response as soon as possible, we would greatly appreciate it！ Re: RT1064 I2C communication abnormality at 400kHz Hi  Supplementary information 1. Our two hardware engineers checked the waveform of the problem through an oscilloscope, and the rise time met the requirements, within 100+ns 2. I ported I2C initialization and read-write function drivers to another type of RT1064 device,  and tested module A without any issues The following figure shows the waveform of another device module A testing logic analyzer doubt: 1. If the clock recovers abnormally after stretching, what other reasons could be causing it 2. Is there a dedicated function to set settings such as MCFGR2 mentioned in the last reply? I didn't see any interface to be set in the I2C initialization process ----If the rise time is met, do we not need to consider these register settings？ Re: RT1064 I2C communication abnormality at 400kHz Hi @foreverwlh2025 ， Thank you so much for your interest in our products and for using our community. I think that this is most likely not a Module A issue, but a 400 kHz timing-margin issue on that specific RT1064 LPI2C2 bus. On RT1064, LPI2C timing is affected by bus rise time, bus loading, pull-up resistors, and glitch-filter latency.  RT1064RM  reference manual describe  that larger rise time increases synchronization latency.  (refer to chapter 47.3.1.4 Timing Parameters) The master glitch filters MCFGR2[FILTSCL/FILTSDA] must be set so their latency stays below the minimum SCL low/high period, and RT1064 provides example 400 kbps timing settings in MCCR0/MCCR1 .  Please check the Table 47-5. LPI2C Example Timing Configurations So if Module A makes the bus edges slightly slower or changes the effective loading, the bus may fail at 400 kHz but still work at 100 kHz .  Wish it helps you Best Regards May Re: RT1064 I2C communication abnormality at 400kHz Below is the configuration for printing. Which parameter may need to be adjusted? PS:apparently due to automatic interface allocation Re: RT1064 I2C communication abnormality at 400kHz A 10 MHz LPI2C functional clock is not listed in the RT1064 Reference Manual example timing configurations for 400 kbps. Although it is possible to generate a 400 kbps baud rate with this clock, the automatically generated timing parameters should be carefully verified against the I2C specification, particularly with respect to tLOW, tHIGH, setup/hold timing, and data valid timing. To reduce design risk, it is recommended to use a validated clock source, such as 48 MHz, as shown in the Reference Manual. Re: RT1064 I2C communication abnormality at 400kHz I tried modifying 60MHz and 8MHz, but it still didn't work. The red box in the figure below shows the values printed after modification, which are different from the manual Re: RT1064 I2C communication abnormality at 400kHz Hi @foreverwlh2025 , There are several ways to configure the I2C clock. As a suggestion, you can try 8 MHz and 60 MHz, as these two clock settings are relatively easy to achieve. I am using the SDK demo: "evkmimxrt1064_lpi2c_edma_b2b_transfer_master" Way 1: Configure LPI2C clock source to 60 MHz Simply set the clock divider to 0. Way 2: Configure LPI2C clock source to 8 MHz Use the MCUXpresso IDE Clock Tool and configure it as shown below. Select OSC_CLK as the clock source and set the divider to 3, which will generate an 8 MHz clock for the LPI2C (I2C) module. Wish it helps you Best Regards May Re: RT1064 I2C communication abnormality at 400kHz Hi @foreverwlh2025 , You may try setting the registers directly. For example, when using a 60 MHz I2C clock, the following configuration can be applied. Wish it helps you Best Regards May Re: RT1064 I2C communication abnormality at 400kHz The current I2C clock is configured based on the sample configuration in the SDK2_13_0-EVK-MIMXRT1064 \ boards \ evkmimxrt1064 \ river_deamples \ lpi2c directory, #define LPI2C_CLOCK_SELECT (0U) #define LPI2C_CLOCK_DIVIDER (5U) CLOCK_SetMux(kCLOCK_Lpi2cMux, LPI2C_CLOCK_SELECT); CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_DIVIDER); ---How can I modify it to obtain the precise 8MHz or 48MHz? (The clock tree doesn't seem to be visible) Re: RT1064 I2C communication abnormality at 400kHz As shown in the diagram, I tried to modify the register settings to correspond to the parameters, but there was no improvement at 60MHz; Even good modules cannot function properly at 8MHz

S32G399A-RDB3 QNX PFE Driver Problems Greetings, we try to get PFE running on a S32G399A-RDB3 board with QNX. As far as I can tell, this is a valid combination: BSP 37.0 PFE-FW_S32G_1.7.0 PFE-DRV-S32G_A53_QNX_1.4.0 It ends with a no carrier error on all network interfaces. Plugging the cable into different ethernet ports changes nothing.  It used to work with gmac0. Any ideas? io pkt call: io-pkt-v6-hc -p tcpip -d pfe-2 pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw,no_reset,mode0=sgmii,phy0=0,mode1=sgmii,phy1=1 Uboot parameters: Uboot is the same as from the Linux sdcard image with modified parmeters for qnx boot.  setenv hwconfig "pcie0:mode=rc,clock=ext;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=2G5" setenv pfeng_mode 'enable,sgmii,sgmii,rgmii' setenv s32cc_gmac_mode disable setenv pfeng enable; s32ccgmac disable; s32ccgmac enable; setenv boot_qnx_atf 'mmc dev 0; fatload mmc 0:1 0x83e00000 s32g399a-rdb3.dtb; pfeng enable; s32ccgmac disable; s32ccgmac enable; fatload mmc 0:1 0x80080000 ifs-s32g399a-rdb.ui; bootm 0x80080000 - 0x83E00000' setenv bootcmd 'run boot_qnx_atf' saveenv Log: U-Boot 2020.04+g156b168010 (Jun 09 2023 - 10:14:25 +0000)   CPU:   NXP S32G399A rev. 1.1 Model: NXP S32G399A-RDB3 DRAM:  3.5 GiB MMC:   FSL_SDHC: 0 Loading Environment from MMC... OK Configuring PCIe0 as RootComplex PCIe0: Failed to get link up PCI: Failed autoconfig bar 1c In:    serial@401c8000 Out:   serial@401c8000 Err:   serial@401c8000 Board revision: RDB3 Revision F Net:   EQOS phy: rgmii @ 1   Warning: eth_eqos (eth0) using random MAC address - 26:e4:e6:43:15:ad eth0: eth_eqosFailed to get speed of XPCS for emac1_xpcs PFE: emac0: sgmii emac1: sgmii emac2: rgmii , eth1: eth_pfeng Hit any key to stop autoboot:  3  2  1  0  switch to partitions #0, OK mmc0 is current device 50640 bytes read in 17 ms (2.8 MiB/s) 11948752 bytes read in 540 ms (21.1 MiB/s) ## Booting kernel from Legacy Image at 80080000 ...    Image Name:       Image Type:   AArch64 Linux Kernel Image (uncompressed)    Data Size:    11948688 Bytes = 11.4 MiB    Load Address: 80080000    Entry Point:  80080000    Verifying Checksum ... OK ## Flattened Device Tree blob at 83e00000    Booting using the fdt blob at 0x83e00000    Loading Kernel Image    Using Device Tree in place at 0000000083e00000, end 0000000083e0f5cf    fixup: pfe0 set to 00:01:be:be:ef:11    fixup: pfe1 set to 00:01:be:be:ef:22    fixup: pfe1: update phy addr to 0x8    fixup: pfe2 set to 00:01:be:be:ef:33   Starting kernel ...   Reserving RAM region for PFE driver on EVB/RDB Done. ClockCycles samples:  0 43600679  1 43600679  2 43600678  3 43600679  4 43600678  5 43600678  6 43600678  7 43600679 All ClockCycles offsets within tolerance Welcome to QNX Neutrino 7.1.0 on the NXP S32G399A RDB Board!! Starting watchdog... Starting serial driver ... Starting Networking driver (/dev/socket)...   Process 4107 (ifconfig) exited status=0.   Process 10 (sh) exited status=0.   Process 9 (dhclient) exited status=0. cp: Can't open source file.  (/proc/boot/libfci_cli)   Process 20489 (cp) exited status=1. Starting SPI driver (/dev/spi0,1,2,3,4,5)... Starting I2C 0/1/2/3/4 driver (/dev/i2c0,1,2,3,4)... Starting USDHC0 memory card driver... [00]     SIM="SDMMC" HBA="imx" [00,0,0] type=00 ver=05 resp=00                       SDMMC:   Process 24596 (chkqnx6fs) exited status=0.   Process 28692 (mount) exited status=0. Starting QSPI Flash driver... Starting USB host driver (/dev/usb/*) Detected QSPI Flash: Macronix MX25UW512, JEDEC 0xC2 - 0x813A, Size: 0x4000000 Launching devb-umass for /dev/usb/* ... #  Process 36891 (sleep) exited status=0. sh: /var/cetitec2/startup.sh: No such file or directory   Process 45081 (sh) terminated signo=0 code=0 by process 0 value=0. slog2info   Jan 01 00:00:00.023                       random.4                  low*     0  qcrypto: loading configuration file '/etc/qcrypto.conf' [qcrypto_common.c(190)] Jan 01 00:00:00.024                    random.4..0                 slog*   700  Random is using the Fortuna PRNG Jan 01 00:00:00.031                       random.4                  low      0  qcrypto: 'openssl' plugin loaded [qcrypto_plugins.c(354)] Jan 01 00:00:00.031                    random.4..0                 slog    700  Selecting timer as an entropy source Jan 01 00:00:00.032                    random.4..0                 slog    700  Registered path names Jan 01 00:00:00.032                    random.4..0                 slog    700  random: starting resmgr Jan 01 00:00:00.032                    random.4..0                 slog    700  random: Daemonizing the process Jan 01 00:00:00.042             devc_serlinflexd.7                 slog*     0  serlinflexd_interrupt_attach: Attaching to interrupt 114 Jan 01 00:00:00.047                        iopkt.8          main_buffer*     0  tcpip starting Jan 01 00:00:00.047                        iopkt.8          main_buffer      0  smmu support is disabled Jan 01 00:00:00.049                        iopkt.8          main_buffer      0  initializing IPsec... Jan 01 00:00:00.049                        iopkt.8          main_buffer      0   done   Jan 01 00:00:00.049                        iopkt.8          main_buffer      0  IPsec: Initialized Security Association Processing.   Jan 01 00:00:00.051                        iopkt.8          main_buffer      0  devnp-pfe-2.so pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw,pfe0_mode=sgmii,pfe0_phy=0,pfe1_mode=sgmii,pfe1_phy=1 Jan 01 00:00:00.052                 io_pkt_v6_hc.8                 slog*     0  INF[src/pfe_drv.c:1377]: VERSION INFO Driver version: 1.4.0 Driver commit hash: 2f3265a49ac18f94ba5e48254c8f870fe7bfc511 PFE_CFG_MULTI_INSTANCE_SUPPORT: 0 PFE_CFG_LOCAL_IF: 6 PFE_CFG_MASTER_IF: 6 PFE_CFG_SC_HIF: 1 PFE_CFG_HIF_RING_LENGTH: 256 PFE_CFG_PFE0_PROMISC: 1 PFE_CFG_PFE1_PROMISC: 1 PFE_CFG_PFE2_PROMISC: 1     Jan 01 00:00:00.052                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1384]: --- Safe IRQ enabled. No InterrupAttach() or InterruptAttach_r() allowed.   Jan 01 00:00:00.052                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_fw.c:83]: 42792 bytes read   Jan 01 00:00:00.053                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_fw.c:89]: Loaded firmware file: /proc/boot/s32g_pfe_class.fw   Jan 01 00:00:00.053                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1477]: MII mode configuration for pfe0/EMAC0 not found. Using SGMII.   Jan 01 00:00:00.053                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1477]: MII mode configuration for pfe1/EMAC1 not found. Using SGMII.   Jan 01 00:00:00.053                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1477]: MII mode configuration for pfe2/EMAC2 not found. Using RGMII.   Jan 01 00:00:00.053                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1495]: Issuing PFE peripheral reset...   Jan 01 00:00:00.274                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1496]: PFE reset OK.   Jan 01 00:00:00.274                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:3519]: PFE CBUS p0x46000000 mapped @ v0x38f2e23000   Jan 01 00:00:00.274                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:3524]: HW version 0x101   Jan 01 00:00:00.274                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hw_feature.c:95]: Silicon S32G3   Jan 01 00:00:00.274                 io_pkt_v6_hc.8                 slog      0  WRN[hw/s32g/pfe_platform_master.c:3536]: Fail-Stop mode disabled   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2687]: PFE_ERRORS:Parity instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2702]: PFE_ERRORS:Watchdog instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2718]: PFE_ERRORS:Bus Error instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2731]: PFE_ERRORS:FW Fail Stop instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2744]: PFE_ERRORS:Host Fail Stop instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2757]: PFE_ERRORS:Fail Stop instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2770]: PFE_ERRORS:ECC Err instance created   Jan 01 00:00:00.275                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:1766]: BMU1 buffer base: p0xc0000000   Jan 01 00:00:00.277                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:1810]: BMU2 buffer base: p0x83000000 (0x200000 bytes)   Jan 01 00:00:00.279                 io_pkt_v6_hc.8                 slog      0  INF[src/oal_irq_qnx.c:117]: PFE BMU IRQ Worker started (IRQ ID: 226)   Jan 01 00:00:00.279                 io_pkt_v6_hc.8                 slog      0  WRN[hw/s32g/pfe_platform_master.c:2194]: The option 'g2_ordered_class_writes' is disabled.   Jan 01 00:00:00.279                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x88000). Pool ready.   Jan 01 00:00:00.279                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x8c000). Pool ready.   Jan 01 00:00:00.281                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2239]: Firmware .elf detected   Jan 01 00:00:00.281                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2248]: Uploading CLASS firmware   Jan 01 00:00:00.281                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_pe.c:609]: Selected FW loading OPs to load 8 PEs in parallel   Jan 01 00:00:00.285                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_pe.c:1945]: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"   Jan 01 00:00:00.288                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_pe.c:2422]: [FW VERSION] 1.7.0, Build: Jun  2 2023, 13:48:57 (nogitaaa), ID: 0x31454650   Jan 01 00:00:00.406                 io_pkt_v6_hc.8                 slog      0  WRN[hw/s32g/pfe_platform_master.c:2312]: VLAN ID incorrect or not set. Using default VLAN ID = 0x01.   Jan 01 00:00:00.406                 io_pkt_v6_hc.8                 slog      0  WRN[hw/s32g/pfe_platform_master.c:2318]: VLAN stats size incorrect or not set. Using default VLAN stats size = 20.   Jan 01 00:00:00.406                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_l2br.c:1181]: Software vlan hash table @ p0x20001228     Jan 01 00:00:00.406                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_l2br.c:1286]: Fall-back bridge domain @ 0x20000a7c (class)   Jan 01 00:00:00.406                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_l2br.c:1287]: Default bridge domain @ 0x20000a74 (class)   Jan 01 00:00:00.406                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:2412]: Routing table created, Hash Table @ p0x80014000, Pool @ p0x8001c000 (65536 bytes)   Jan 01 00:00:00.407                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64   Jan 01 00:00:00.408                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64   Jan 01 00:00:00.409                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64   Jan 01 00:00:00.508                 io_pkt_v6_hc.8                 slog      0  INF[hw/s32g/pfe_platform_master.c:3705]: Feature err051211_workaround: DISABLED   Jan 01 00:00:00.509                        iopkt.8          main_buffer      0  pfe0   Jan 01 00:00:00.509                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2152]: pfe0: Using PHY mode: MDIO=0, ADDR=0, CLAUSE=0, RESET=0   Jan 01 00:00:00.509                 io_pkt_v6_hc.8                 slog      0  INF[src/oal_irq_qnx.c:117]: PFE HIF0 IRQ Worker started (IRQ ID: 222)   Jan 01 00:00:00.509                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1795]: Adding 00:0a:0b:0c:0d:66 to pfe0   Jan 01 00:00:00.511                        iopkt.8          main_buffer      0  pfe1   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe0 not found. Using 1 Gbps/full-duplex.   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 0   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2363]: New PFE device: 0, ID: 0   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2152]: pfe1: Using PHY mode: MDIO=1, ADDR=0, CLAUSE=0, RESET=0   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/oal_irq_qnx.c:117]: PFE HIF1 IRQ Worker started (IRQ ID: 223)   Jan 01 00:00:00.511                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1795]: Adding 00:1a:1b:1c:1d:66 to pfe1   Jan 01 00:00:00.513                        iopkt.8          main_buffer      0  pfe2   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe1 not found. Using 1 Gbps/full-duplex.   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 1   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2363]: New PFE device: 1, ID: 2   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2145]: pfe2: Using static PHY mode, RESET=0   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/oal_irq_qnx.c:117]: PFE HIF2 IRQ Worker started (IRQ ID: 224)   Jan 01 00:00:00.513                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:1795]: Adding 00:2a:2b:2c:2d:66 to pfe2   Jan 01 00:00:00.515                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe2 not found. Using 1 Gbps/full-duplex.   Jan 01 00:00:00.515                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 2   Jan 01 00:00:00.515                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started   Jan 01 00:00:00.515                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2363]: New PFE device: 2, ID: 4   Jan 01 00:00:00.530                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2702]: Adding 00:0a:0b:0c:0d:66 to pfe0   Jan 01 00:00:00.530                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2707]: Unable to assign MAC address 00:0a:0b:0c:0d:66 to the pfe0   Jan 01 00:00:00.530                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode   Jan 01 00:00:00.538                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_mdio.c:427]: pfe0: PHY @ bus 0 addr 0 not found. Switching to static mode.   Jan 01 00:00:00.538                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2829]: EMAC speed change for SGMII is currently not supported.   Jan 01 00:00:00.538                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0   Jan 01 00:00:00.540                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode   Jan 01 00:00:00.540                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2829]: EMAC speed change for SGMII is currently not supported.   Jan 01 00:00:00.542                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 01:00:5e:00:00:01 to emac0   Jan 01 00:00:00.544                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0   Jan 01 00:00:00.544                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17   Jan 01 00:00:00.544                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0   Jan 01 00:00:00.544                 io_pkt_v6_hc.8                 slog      0  WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17   Jan 01 00:00:00.544                 io_pkt_v6_hc.8                 slog      0  INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode   Jan 01 00:00:00.554               spi_master.24585               normal*     0  Starting spi-master resource manager Jan 01 00:00:00.558               spi_master.24587               normal*     0  Starting spi-master resource manager Jan 01 00:00:00.561               spi_master.24588               normal*     0  Starting spi-master resource manager Jan 01 00:00:00.565               spi_master.24589               normal*     0  Starting spi-master resource manager Jan 01 00:00:00.582          devb_sdmmc_mx8x.24595                 slog*  1800  devb-sdmmc-mx8x 1.00A (Jun 23 2026 09:45:48) Jan 01 00:00:00.583          devb_sdmmc_mx8x.24595                 slog      0  libcam.so (Jun 22 2020 21:33:15) bver 7010003 Jan 01 00:00:00.594          devb_sdmmc_mx8x.24595                 slog   1800  sdio_cd:  insertion path 0, cd state 0x1 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800  SD CID: Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    MID 0x27, OID 0x5048, PNM SD32G Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    PRV 0x62, PSN 0x6c62d132, MDT 4-2023 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800  SD CSD: Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    CSD_STRUCTURE 1, SPEC_VERS 0, CCC 0x5b5 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    TAAC 14, NSAC 0, TRAN_SPEED 50 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    C_SIZE 59023, C_SIZE_MULT 0 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    READ_BL_LEN 9, WRITE_BL_LEN 9 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    ERASE GRP_SIZE 0, GRP_MULT 0, SIZE 127 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    blksz 512, sectors 60440576, dtr 25000000 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800  SD SW CAPS: Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    bus mode 0x3, cmd sys 0x1 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    drv type 0x1, curr limit 0x1 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800    dtr 50000000 Jan 01 00:00:00.644          devb_sdmmc_mx8x.24595                 slog   1800  CFG:  Timing HS, DTR 50000000, Bus Width 4 bit   Jan 01 00:00:00.645          devb_sdmmc_mx8x.24595                 slog    100  cam-disk.so (Jun 22 2020 21:33:17) Jan 01 00:00:00.647          devb_sdmmc_mx8x.24595                 slog      0  scsi_interpret_sense (sdmmc ptl-0:0:0):  cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=1a, error=70, sense=5, asc=24, ascq=0 Jan 01 00:00:00.647          devb_sdmmc_mx8x.24595                 slog      0  scsi_interpret_sense (sdmmc ptl-0:0:0):  cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=5a, error=70, sense=5, asc=24, ascq=0 Jan 01 00:00:00.647          devb_sdmmc_mx8x.24595                 slog      0  scsi_interpret_sense (sdmmc ptl-0:0:0):  cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=5a, error=70, sense=5, asc=24, ascq=0 Jan 01 00:00:01.827          devb_sdmmc_mx8x.24595                 slog   1000  fs-qnx6: Allocation strategy 0 Jan 01 00:00:01.827          devb_sdmmc_mx8x.24595                 slog   1000  fs-qnx6: Use btree directory 0 Jan 01 00:00:01.828          devb_sdmmc_mx8x.24595                 slog   1000  fs-qnx6: fs-qnx6: trim (0,1048576,2) was not requested, and is NOT supported Jan 01 00:00:01.833               io_usb_otg.36885                 slog*     0  main(453)[tid:1]: io-usb-otg (Jun 13 2020 20:10:17) args: -d hcd-ehci-mx28 ioport=0x44064100,irq=243,ulpi,no_stream,verbose=5  Jan 01 00:00:01.835           devf_qspi_s32g.36884                 slog*     0  (devf  t1::f3s_qspi_ident:73) Page size: 256 Jan 01 00:00:01.835           devf_qspi_s32g.36884                 slog      0  (devf  t1::f3s_qspi_ident:74) Total chip size: 0x4000000, Unit size: 0x10000 Jan 01 00:00:01.839               io_usb_otg.36885                 slog      0  ehci_init: Initialiaing with sever version: 2  Jan 01 00:00:01.839               io_usb_otg.36885                 slog      0  ehci_controller_init(4303): devu-hcd-ehci-mx28.so (Apr 19 2024 13:44:54):  args ulpi,no_stream,verbose=5 Jan 01 00:00:01.840               io_usb_otg.36885                 slog      8  usb_enum_port(94)[tid:1]: busno 0, parent -1, port 0, High speed Jan 01 00:00:01.840               io_usb_otg.36885                 slog     11  usb_client_descriptor_get(198)[tid:1]: (type 1, index 0, length 😎 Jan 01 00:00:01.840               io_usb_otg.36885                 slog     12  usb_device_set_address(245)[tid:1]: b:0 devno 0 Jan 01 00:00:01.840               io_usb_otg.36885                 slog     11  usb_client_descriptor_get(198)[tid:1]: (type 1, index 0, length 18) Jan 01 00:00:01.841               io_usb_otg.36885                 slog     11  usb_client_descriptor_get(198)[tid:1]: (type 2, index 0, length 9) Jan 01 00:00:01.841               io_usb_otg.36885                 slog     11  usb_client_descriptor_get(198)[tid:1]: (type 2, index 0, length 25) Jan 01 00:00:01.841               io_usb_otg.36885                 slog      8  usb_enum_port(141)[tid:1]: vid 0x0000, did 0x0000 enumerated(busno 0, devno 0:0) Jan 01 00:00:01.841               io_usb_otg.36885                 slog     11  hub_state_inserted(569)[tid:1]: bdentry 0, dentry 0 0 Jan 01 00:00:01.841               io_usb_otg.36885                 slog     13  hub_configuration_enable(263)[tid:1]: 1 Jan 01 00:00:01.943               io_usb_otg.36885                 slog      0  usbh_timeout_init(203)[tid:1]: Complete Jan 01 00:00:01.954               io_usb_otg.36885                 slog      0  read_vid_pid: ULPI VID 0x0424 PID 0x0009 Jan 01 00:00:01.954               io_usb_otg.36885                 slog      0  s32g_phy_set_vbus: set_vbus off Jan 01 00:00:01.968               io_usb_otg.36885                 slog      0  s32g_phy_set_vbus: set_vbus on Jan 01 00:00:01.979               io_usb_otg.36885                 slog      0  ehci_get_port_status(3568 0x44064100): port=0, tpstatus 10100 e_pstatus 8c001000 Jan 01 00:00:01.979               io_usb_otg.36885                 slog      8  usb_enum_port_extract(172)[tid:7]: (busno 0, pdevno 0, portno 1) Jan 01 00:00:01.979               io_usb_otg.36885                 slog      8  usb_enum_port_extract(192)[tid:7]: status (2) Jan 01 00:00:01.983               devb_umass.36886                 slog*   900  devb-umass 1.00A (Jun 22 2020 21:33:41) Jan 01 00:00:01.984               devb_umass.36886                 slog      0  libcam.so (Jun 22 2020 21:33:15) bver 7010003 Jan 01 00:00:01.985               io_usb_otg.36885                 slog      0  usbdi_client_connect(58)[tid:5]: pid 36886 proc=proc/boot/devb-umass usbdi_client 32eebb9a80 Jan 01 00:00:01.986               io_usb_otg.36885                 slog      0  usbdi_resmgr_connect(310)[tid:5]: usbdi_resmgr_connect: pid 36886 usbdi_client 32eebb9a80  Jan 01 00:00:01.986               devb_umass.36886                 slog      0  usbdi debug path /pps/usb/debug/ doesn't exist   Process 49177 (slog2info) exited status=0. # ifconfig   lo0: flags=8049 mtu 33136 inet 127.0.0.1 netmask 0xff000000 inet6 ::1 prefixlen 128 inet6 fe80::1%lo0 prefixlen 64 scopeid 0x1 pfe0: flags=8843 mtu 1500 capabilities=1f enabled=0 address: 00:0a:0b:0c:0d:66 media: Ethernet none (1000baseT full-duplex) status: active inet 0.0.0.0 netmask 0xff000000 broadcast 255.255.255.255 inet6 fe80::20a:bff:fe0c:d66%pfe0 prefixlen 64 scopeid 0x11 pfe1: flags=8802 mtu 1500 capabilities=1f enabled=0 address: 00:1a:1b:1c:1d:66 media: Ethernet none (1000baseT full-duplex) status: no carrier pfe2: flags=8802 mtu 1500 capabilities=1f enabled=0 address: 00:2a:2b:2c:2d:66 media: Ethernet none (1000baseT full-duplex) status: no carrier   Process 57369 (ifconfig) exited status=0. #  Re: S32G399A-RDB3 QNX PFE Driver Problems Ok, so I replaced s32g_pfe_class.fw and s32g_pfe_util.fw with the files from PFE-FW_S32G_1.6.0.zip here: https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=14074877 Uboot parameters: setenv boot_qnx_atf 'mmc dev 0; fatload mmc 0:1 0x83e00000 s32g399a-rdb3.dtb; run atf_fdt_0to3; run atf_fdt_4to7; fatload mmc 0:1 0x80080000 ifs-s32g399a-rdb.ui; pfeng enable; s32ccgmac disable; s32ccgmac enable; bootm 0x80080000 - 0x83E00000' setenv atf_fdt_0to3 'fdt addr 0x83e00000; fdt resize; fdt set /cpus/cpu@1 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@100 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@101 cpu-release-addr <0x0 0xa0000010>;' setenv atf_fdt_4to7 'fdt set /cpus/cpu@2 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@3 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@102 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@103 cpu-release-addr <0x0 0xa0000010>;' setenv release_cpus 'run cpu_trap; mp 1 release 0xa0000000; mp 2 release 0xa0000000; mp 3 release 0xa0000000; mp 4 release 0xa0000000; mp 5 release 0xa0000000; mp 6 release 0xa0000000; mp 7 release 0xa0000000;' setenv cpu_trap 'dcache off; mw.l 0xa0000000 0xd503205f; mw.l 0xa0000004 0x58000060; mw.l 0xa0000008 0xb4ffffc0; mw.l 0xa000000C 0xd61f0000; mw.q 0xa0000010 0x00000000; dcache on;' setenv bootcmd 'run boot_qnx_atf' setenv hwconfig "pcie0:mode=rc,clock=ext;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=2G5" setenv pfeng_mode 'enable,sgmii,sgmii,rgmii' setenv s32cc_gmac_mode disable saveenv Note: I removed the release_cpus command from boot_qnx_atf because then I would havef a cpu 1 error. Doesn't look much better to me: NOTICE:  BL2: v2.5(release):bsp37.0_rc6-2.5 NOTICE:  BL2: Built : 09:12:21, Jun 13 2023 NOTICE:  BL2: Booting BL31     U-Boot 2020.04+g156b168010 (Jun 09 2023 - 10:14:25 +0000)   CPU:   NXP S32G399A rev. 1.1 Model: NXP S32G399A-RDB3 DRAM:  3.5 GiB MMC:   FSL_SDHC: 0 Loading Environment from MMC... OK Configuring PCIe0 as RootComplex PCIe0: Failed to get link up PCI: Failed autoconfig bar 1c In:    serial@401c8000 Out:   serial@401c8000 Err:   serial@401c8000 Board revision: RDB3 Revision F Net:   EQOS phy: rgmii @ 1   Warning: eth_eqos (eth0) using random MAC address - 16:ec:a0:4e:1d:7c eth0: eth_eqosFailed to get speed of XPCS for emac1_xpcs PFE: emac0: sgmii emac1: sgmii emac2: rgmii , eth1: eth_pfeng Hit any key to stop autoboot:  3  2  1  0  switch to partitions #0, OK mmc0 is current device 50640 bytes read in 17 ms (2.8 MiB/s) 11950600 bytes read in 534 ms (21.3 MiB/s) ## Booting kernel from Legacy Image at 80080000 ...    Image Name:       Image Type:   AArch64 Linux Kernel Image (uncompressed)    Data Size:    11950536 Bytes = 11.4 MiB    Load Address: 80080000    Entry Point:  80080000    Verifying Checksum ... OK ## Flattened Device Tree blob at 83e00000    Booting using the fdt blob at 0x83e00000    Loading Kernel Image    Using Device Tree in place at 0000000083e00000, end 0000000083e0ffff    fixup: pfe0 set to 00:01:be:be:ef:11    fixup: pfe1 set to 00:01:be:be:ef:22    fixup: pfe1: update phy addr to 0x8    fixup: pfe2 set to 00:01:be:be:ef:33   Starting kernel ...   Reserving RAM region for PFE driver on EVB/RDB Done. ClockCycles samples:  0 43642864  1 43642864  2 43642864  3 43642864  4 43642864  5 43642864  6 43642864  7 43642864 All ClockCycles offsets within tolerance Welcome to QNX Neutrino 7.1.0 on the NXP S32G399A RDB Board!! Starting watchdog... Starting serial driver ... Starting Networking driver (/dev/socket)...   Process 4107 (ifconfig) exited status=0.   Process 10 (sh) exited status=0.   Process 9 (dhclient) exited status=0. cp: Can't open source file.  (/proc/boot/libfci_cli)   Process 20489 (cp) exited status=1. Starting SPI driver (/dev/spi0,1,2,3,4,5)... Starting I2C 0/1/2/3/4 driver (/dev/i2c0,1,2,3,4)... Starting USDHC0 memory card driver... [00]     SIM="SDMMC" HBA="imx" [00,0,0] type=00 ver=05 resp=00                       SDMMC:   Process 24596 (chkqnx6fs) exited status=0.   Process 28692 (mount) exited status=0. Starting QSPI Flash driver... Starting USB host driver (/dev/usb/*) Detected QSPI Flash: Macronix MX25UW512, JEDEC 0xC2 - 0x813A, Size: 0x4000000 Launching devb-umass for /dev/usb/* ... # ifconfig   lo0: flags=8049 mtu 33136 inet 127.0.0.1 netmask 0xff000000 inet6 ::1 prefixlen 128 inet6 fe80::1%lo0 prefixlen 64 scopeid 0x1 pfe0: flags=8843 mtu 1500 capabilities=1f enabled=0 address: 00:0a:0b:0c:0d:66 media: Ethernet none (1000baseT full-duplex) status: active inet 0.0.0.0 netmask 0xff000000 broadcast 255.255.255.255 inet6 fe80::20a:bff:fe0c:d66%pfe0 prefixlen 64 scopeid 0x11 pfe1: flags=8802 mtu 1500 capabilities=1f enabled=0 address: 00:1a:1b:1c:1d:66 media: Ethernet none (1000baseT full-duplex) status: no carrier pfe2: flags=8802 mtu 1500 capabilities=1f enabled=0 address: 00:2a:2b:2c:2d:66 media: Ethernet none (1000baseT full-duplex) status: no carrier   Process 40985 (ifconfig) exited status=0. #  Process 36891 (sleep) exited status=0. sh: /var/cetitec2/startup.sh: No such file or directory   Process 53273 (sh) terminated signo=0 code=0 by process 0 value=0.   # ifconfig    lo0: flags=8049 mtu 33136 inet 127.0.0.1 netmask 0xff000000 inet6 ::1 prefixlen 128 inet6 fe80::1%lo0 prefixlen 64 scopeid 0x1 pfe0: flags=8843 mtu 1500 capabilities=1f enabled=0 address: 00:0a:0b:0c:0d:66 media: Ethernet none (1000baseT full-duplex) status: active inet 0.0.0.0 netmask 0xff000000 broadcast 255.255.255.255 inet6 fe80::20a:bff:fe0c:d66%pfe0 prefixlen 64 scopeid 0x11 pfe1: flags=8802 mtu 1500 capabilities=1f enabled=0 address: 00:1a:1b:1c:1d:66 media: Ethernet none (1000baseT full-duplex) status: no carrier pfe2: flags=8802 mtu 1500 capabilities=1f enabled=0 address: 00:2a:2b:2c:2d:66 media: Ethernet none (1000baseT full-duplex) status: no carrier   # slog2info | grep pfe Jan 01 00:00:00.051 iopkt.8 main_buffer 0 devnp-pfe-2.so pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog* 0 INF[src/pfe_drv.c:1377]: VERSION INFO Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1384]: --- Safe IRQ enabled. No InterrupAttach() or InterruptAttach_r() allowed. Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog 0 INF[src/pfe_fw.c:83]: 49480 bytes read Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog 0 INF[src/pfe_fw.c:89]: Loaded firmware file: /proc/boot/s32g_pfe_class.fw Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1477]: MII mode configuration for pfe0/EMAC0 not found. Using SGMII. Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1477]: MII mode configuration for pfe1/EMAC1 not found. Using SGMII. Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1477]: MII mode configuration for pfe2/EMAC2 not found. Using RGMII. Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1495]: Issuing PFE peripheral reset... Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1496]: PFE reset OK. Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:3519]: PFE CBUS p0x46000000 mapped @ v0x1abef95000 Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:3524]: HW version 0x101 Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hw_feature.c:95]: Silicon S32G3 Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:3536]: Fail-Stop mode disabled Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2687]: PFE_ERRORS:Parity instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2702]: PFE_ERRORS:Watchdog instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2718]: PFE_ERRORS:Bus Error instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2731]: PFE_ERRORS:FW Fail Stop instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2744]: PFE_ERRORS:Host Fail Stop instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2757]: PFE_ERRORS:Fail Stop instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2770]: PFE_ERRORS:ECC Err instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:1766]: BMU1 buffer base: p0xc0000000 Jan 01 00:00:00.277 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:1810]: BMU2 buffer base: p0x83000000 (0x200000 bytes) Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:2194]: The option 'g2_ordered_class_writes' is disabled. Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x88000). Pool ready. Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x8c000). Pool ready. Jan 01 00:00:00.281 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2239]: Firmware .elf detected Jan 01 00:00:00.281 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2248]: Uploading CLASS firmware Jan 01 00:00:00.281 io_pkt_v6_hc.8 slog 0 INF[src/pfe_pe.c:609]: Selected FW loading OPs to load 8 PEs in parallel Jan 01 00:00:00.285 io_pkt_v6_hc.8 slog 0 INF[src/pfe_pe.c:1945]: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" Jan 01 00:00:00.288 io_pkt_v6_hc.8 slog 0 INF[src/pfe_pe.c:2422]: [FW VERSION] 1.6.0, Build: Mar 15 2023, 12:37:54 (), ID: 0x31454650 Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:2312]: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:2318]: VLAN stats size incorrect or not set. Using default VLAN stats size = 20. Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[src/pfe_l2br.c:1181]: Software vlan hash table @ p0x20001208 Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[src/pfe_l2br.c:1286]: Fall-back bridge domain @ 0x20000a44 (class) Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[src/pfe_l2br.c:1287]: Default bridge domain @ 0x20000a3c (class) Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2412]: Routing table created, Hash Table @ p0x80014000, Pool @ p0x8001c000 (65536 bytes) Jan 01 00:00:00.407 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64 Jan 01 00:00:00.408 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64 Jan 01 00:00:00.409 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64 Jan 01 00:00:00.508 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:3705]: Feature err051211_workaround: DISABLED Jan 01 00:00:00.509 iopkt.8 main_buffer 0 pfe0 Jan 01 00:00:00.509 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2145]: pfe0: Using static PHY mode, RESET=0 Jan 01 00:00:00.510 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1795]: Adding 00:0a:0b:0c:0d:66 to pfe0 Jan 01 00:00:00.512 iopkt.8 main_buffer 0 pfe1 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe0 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2363]: New PFE device: 0, ID: 0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2145]: pfe1: Using static PHY mode, RESET=0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1795]: Adding 00:1a:1b:1c:1d:66 to pfe1 Jan 01 00:00:00.514 iopkt.8 main_buffer 0 pfe2 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe1 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 1 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2363]: New PFE device: 1, ID: 2 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2145]: pfe2: Using static PHY mode, RESET=0 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1795]: Adding 00:2a:2b:2c:2d:66 to pfe2 Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe2 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 2 Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2363]: New PFE device: 2, ID: 4 Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2702]: Adding 00:0a:0b:0c:0d:66 to pfe0 Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2707]: Unable to assign MAC address 00:0a:0b:0c:0d:66 to the pfe0 Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2829]: EMAC speed change for SGMII is currently not supported. Jan 01 00:00:00.532 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.534 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.534 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2829]: EMAC speed change for SGMII is currently not supported. Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 01:00:5e:00:00:01 to emac0 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode # slog2info  | grep io_pkt_v6_hc Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog* 0 INF[src/pfe_drv.c:1377]: VERSION INFO Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1384]: --- Safe IRQ enabled. No InterrupAttach() or InterruptAttach_r() allowed. Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog 0 INF[src/pfe_fw.c:83]: 49480 bytes read Jan 01 00:00:00.052 io_pkt_v6_hc.8 slog 0 INF[src/pfe_fw.c:89]: Loaded firmware file: /proc/boot/s32g_pfe_class.fw Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1477]: MII mode configuration for pfe0/EMAC0 not found. Using SGMII. Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1477]: MII mode configuration for pfe1/EMAC1 not found. Using SGMII. Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1477]: MII mode configuration for pfe2/EMAC2 not found. Using RGMII. Jan 01 00:00:00.053 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1495]: Issuing PFE peripheral reset... Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1496]: PFE reset OK. Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:3519]: PFE CBUS p0x46000000 mapped @ v0x1abef95000 Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:3524]: HW version 0x101 Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hw_feature.c:95]: Silicon S32G3 Jan 01 00:00:00.274 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:3536]: Fail-Stop mode disabled Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2687]: PFE_ERRORS:Parity instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2702]: PFE_ERRORS:Watchdog instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2718]: PFE_ERRORS:Bus Error instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2731]: PFE_ERRORS:FW Fail Stop instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2744]: PFE_ERRORS:Host Fail Stop instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2757]: PFE_ERRORS:Fail Stop instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2770]: PFE_ERRORS:ECC Err instance created Jan 01 00:00:00.275 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:1766]: BMU1 buffer base: p0xc0000000 Jan 01 00:00:00.277 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:1810]: BMU2 buffer base: p0x83000000 (0x200000 bytes) Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:2194]: The option 'g2_ordered_class_writes' is disabled. Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 INF[src/oal_irq_qnx.c:117]: PFE BMU IRQ Worker started (IRQ ID: 226) Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x88000). Pool ready. Jan 01 00:00:00.279 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x8c000). Pool ready. Jan 01 00:00:00.281 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2239]: Firmware .elf detected Jan 01 00:00:00.281 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2248]: Uploading CLASS firmware Jan 01 00:00:00.281 io_pkt_v6_hc.8 slog 0 INF[src/pfe_pe.c:609]: Selected FW loading OPs to load 8 PEs in parallel Jan 01 00:00:00.285 io_pkt_v6_hc.8 slog 0 INF[src/pfe_pe.c:1945]: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8" Jan 01 00:00:00.288 io_pkt_v6_hc.8 slog 0 INF[src/pfe_pe.c:2422]: [FW VERSION] 1.6.0, Build: Mar 15 2023, 12:37:54 (), ID: 0x31454650 Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:2312]: VLAN ID incorrect or not set. Using default VLAN ID = 0x01. Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 WRN[hw/s32g/pfe_platform_master.c:2318]: VLAN stats size incorrect or not set. Using default VLAN stats size = 20. Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[src/pfe_l2br.c:1181]: Software vlan hash table @ p0x20001208 Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[src/pfe_l2br.c:1286]: Fall-back bridge domain @ 0x20000a44 (class) Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[src/pfe_l2br.c:1287]: Default bridge domain @ 0x20000a3c (class) Jan 01 00:00:00.406 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:2412]: Routing table created, Hash Table @ p0x80014000, Pool @ p0x8001c000 (65536 bytes) Jan 01 00:00:00.407 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64 Jan 01 00:00:00.408 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64 Jan 01 00:00:00.409 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_chnl.c:1997]: Initializing RX buffer pool. Depth: 256; Buffer Size: 2048; Cache Line Size: 64 Jan 01 00:00:00.508 io_pkt_v6_hc.8 slog 0 INF[hw/s32g/pfe_platform_master.c:3705]: Feature err051211_workaround: DISABLED Jan 01 00:00:00.509 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2145]: pfe0: Using static PHY mode, RESET=0 Jan 01 00:00:00.509 io_pkt_v6_hc.8 slog 0 INF[src/oal_irq_qnx.c:117]: PFE HIF0 IRQ Worker started (IRQ ID: 222) Jan 01 00:00:00.510 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1795]: Adding 00:0a:0b:0c:0d:66 to pfe0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe0 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2363]: New PFE device: 0, ID: 0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2145]: pfe1: Using static PHY mode, RESET=0 Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/oal_irq_qnx.c:117]: PFE HIF1 IRQ Worker started (IRQ ID: 223) Jan 01 00:00:00.512 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1795]: Adding 00:1a:1b:1c:1d:66 to pfe1 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe1 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 1 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2363]: New PFE device: 1, ID: 2 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2145]: pfe2: Using static PHY mode, RESET=0 Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/oal_irq_qnx.c:117]: PFE HIF2 IRQ Worker started (IRQ ID: 224) Jan 01 00:00:00.514 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:1795]: Adding 00:2a:2b:2c:2d:66 to pfe2 Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2298]: Speed/duplex configuration for pfe2 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:336]: Attempt to register HIF client: 2 Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF driver started Jan 01 00:00:00.516 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2363]: New PFE device: 2, ID: 4 Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2702]: Adding 00:0a:0b:0c:0d:66 to pfe0 Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2707]: Unable to assign MAC address 00:0a:0b:0c:0d:66 to the pfe0 Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.531 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2829]: EMAC speed change for SGMII is currently not supported. Jan 01 00:00:00.532 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.534 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.534 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2829]: EMAC speed change for SGMII is currently not supported. Jan 01 00:00:00.536 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 01:00:5e:00:00:01 to emac0 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:00:00.538 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Process 172057 (slog2info) exited status=0. Jan 01 00:01:01.630 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:00:00:00:01 to emac0 Jan 01 00:01:01.630 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:00:00:00:01 into emac0: 17 Jan 01 00:01:01.630 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2443]: Adding 33:33:ff:0c:0d:66 to emac0 Jan 01 00:01:01.630 io_pkt_v6_hc.8 slog 0 WRN[src/pfe_drv.c:2450]: unable to add 33:33:ff:0c:0d:66 into emac0: 17 Jan 01 00:01:01.630 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2495]: Removing 01:00:5e:00:00:01 from emac0 Jan 01 00:01:01.632 io_pkt_v6_hc.8 slog 0 INF[src/pfe_phy_if.c:2716]: Address 01:00:5e:00:00:01 removed from emac0 Jan 01 00:01:01.632 io_pkt_v6_hc.8 slog 0 INF[src/pfe_drv.c:2663]: pfe0: Disabling promiscuous mode Re: S32G399A-RDB3 QNX PFE Driver Problems Hello, @Seneca  Thanks for your post. By default, the S32G PFE QNX Driver Version 1.4.0 is compatible with S32G PFE Firmware Standard Version 1.6.0, would you mind testing it again with this PFE FW version instead? BR Chenyin Re: S32G399A-RDB3 QNX PFE Driver Problems Ok, so I downloaded the  BSP_nxp-s32g-evb_br-710_be-710_SVN984052_JBN51 package you mentioned, modified the .build file and add the  kprintf("Reserving RAM region for PFE driver on EVB/RDB\n"); as_add_containing(0x80000000,0x80000000 + 0x4000000 - 1,AS_ATTR_RAM, "pfe_ddr","ram"); to src/hardware/startup/boards/s32g/s32g399a-rdb/s32g_init_raminfo.c and replace my ifs file with the resulting ifs-s32g399a-rdb.ui. Unfortunately, it doesn't seem to execute the pfe_ddr allocation from above.  Is there anything I need to modify for the uboot parameters or else for this new image to work? Regards Re: S32G399A-RDB3 QNX PFE Driver Problems Hello, @Seneca  Thanks for your reply. I suggest referencing the integration manual strictly, refer to the part you mentioned, the following need to be modified before building the QNX BSP. BR Chenyin Re: S32G399A-RDB3 QNX PFE Driver Problems Greetings, do you know if NXP provides SDCard images that already have the uboot modifications necessary for PFE as in board_cleanup_before_linux? I don't know what packages like binaries_auto_linux_bsp37.0_s32g3_pfe do. Regards Re: S32G399A-RDB3 QNX PFE Driver Problems And what was the PFE firmware version used? JBN51 needs NXP BSP39 which comes with PFE Firmware 1.8.0. But section 2.1.3 of the Pfe Driver 1.7.0 release notes states that only PFW FW 1.10.0 was tested with this release. Re: S32G399A-RDB3 QNX PFE Driver Problems Hello, @Seneca  Thanks for your reply. The tested BSP version is BSP39 combine with QNX driver version 1.7.0 and QNX SDP 7.1 BSP JBN51 BR Chenyin Re: S32G399A-RDB3 QNX PFE Driver Problems Greetings, I intend to try the following combination: BSP 33 PFE Driver 1.2.0 PFE FW 1.3.0 Is this officially supported? Regards Re: S32G399A-RDB3 QNX PFE Driver Problems Greetings, I intend to try the following combination: BSP 33 PFE Driver 1.2.0 PFE FW 1.3.0 Is this officially supported? Regards Re: S32G399A-RDB3 QNX PFE Driver Problems Hello. @Seneca  Thanks for your reply. 1. For the combination, I suggest referencing the documents included in the QNX PFE drivers directly, which included the recommended/tested combination. Other combination may or may not work, you may test it accordingly if indeed needed. 2. From the available information, for QNX PFE drive 1.2, the supported PFE FW is 1.2 with BSP30 used for test BR Chenyin Re: S32G399A-RDB3 QNX PFE Driver Problems Hello Chenyin, can you tell me which NXP BSP Version was used by the person who tested the PFE Driver 1.7.0 with the QNXJBN51? Regards Re: S32G399A-RDB3 QNX PFE Driver Problems Hello, @Seneca  Sorry that there are not such images for publicly downloaded. For "binaries_auto_linux_bsp37.0_s32g3_pfe", seems it is the name of the tgz file from: If so, it includes the pre-built binaries of Linux BSP provisioned by NXP, there are not any QNX related images included.  BR Chenyin Re: S32G399A-RDB3 QNX PFE Driver Problems Hello, @Seneca  Thanks for your reply. Would you mind providing the full booting log including all u-boot env information for further checking? BR Chenyin  Re: S32G399A-RDB3 QNX PFE Driver Problems Note: io pkt is not started at the moment. Starting it will not remove the no carrier problem though. U-Boot 2022.04 (Jul 01 2026 - 16:53:39 +0200) SoC: NXP S32G399A rev. 1.1 CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz Model: NXP S32G399A-RDB3 DRAM: 3.5 GiB Core: 306 devices, 25 uclasses, devicetree: board MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@401c8000 Out: serial@401c8000 Err: serial@401c8000 Board revision: RDB3 Revision F PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class __________________________________________________________________________ pcie@40400000 RootComplex | `-- 01:00.00 0x1957 0x4300 Bridge device 0x04 Net: eth0: ethernet@4033c000 Found PFE version 0x0101 (S32G3) , eth1: pfe0, eth2: pfe1, eth3: pfe2 Hit any key to stop autoboot: 2  1  0 => printenv atf_fdt_0to3=fdt addr 0x83e00000; fdt resize; fdt set /cpus/cpu@1 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@100 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@101 cpu-release-addr <0x0 0xa0000010>; atf_fdt_4to7=fdt set /cpus/cpu@2 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@3 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@102 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@103 cpu-release-addr <0x0 0xa0000010>; baudrate=115200 board_rev=F boot_mtd=booti boot_qnx_atf=mmc dev 0; fatload mmc 0:1 0x83e00000 s32g399a-rdb3.dtb; run atf_fdt_0to3; run atf_fdt_4to7; fatload mmc 0:1 0x80080000 ifs-s32g399a-rdb.ui; bootm 0x80080000 - 0x83E00000 bootargs=root=/dev/ram rw earlycon loglevel=7 bootcmd=run boot_qnx_atf bootdelay=2 console=ttyLF0 cpu_trap=dcache off; mw.l 0xa0000000 0xd503205f; mw.l 0xa0000004 0x58000060; mw.l 0xa0000008 0xb4ffffc0; mw.l 0xa000000C 0xd61f0000; mw.q 0xa0000010 0x00000000; dcache on; eth1addr=00:04:9f:be:ef:00 eth2addr=00:04:9f:be:ef:01 eth3addr=00:04:9f:be:ef:02 ethaddr=0e:46:58:92:0b:68 fdt_addr=0x83000000 fdt_enable_hs400es=fdt addr ${fdt_addr}; fdt rm /soc/mmc no-1-8-v; fdt resize; fdt_file=s32g399a-rdb3.dtb fdt_high=0xffffffffffffffff fdt_override=; fdtcontroladdr=ffa96000 flashboot=echo Booting from flash...; run flashbootargs;mtd read Kernel ${loadaddr};mtd read DTB ${fdt_addr};mtd read Rootfs ${ramdisk_addr};${boot_mtd} ${loadaddr} ${ramdisk_addr} ${fdt_addr}; flashbootargs=setenv bootargs console=${console},${baudrate} root=/dev/ram rw earlycon ;setenv flashsize 0x04000000; hwconfig=serdes0:mode=pcie,clock=ext;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=2G5;xpcs1_1:speed=1G image=Image initrd_high=0xffffffffffffffff ipaddr=10.0.0.100 loadaddr=0x80000000 loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}; run fdt_override; loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadtftpfdt=tftp ${fdt_addr} ${fdt_file}; loadtftpimage=tftp ${loadaddr} ${image}; mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon mmcboot=echo Booting from mmc ...; run mmcargs; if run loadfdt; then run fdt_fixups; ${boot_mtd} ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; mmcdev=0 mmcpart=1 mmcroot=/dev/mmcblk0p2 rootwait rw netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp earlycon netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then ${boot_mtd} ${loadaddr} - ${fdt_addr}; else if test ${boot_fdt} = try; then ${boot_mtd}; else echo WARN: Cannot load the DT; fi; fi; else ${boot_mtd}; fi; netmask=255.255.255.0 nfsboot=echo Booting from net using tftp and nfs...; run nfsbootargs;run loadtftpimage; run loadtftpfdt;${boot_mtd} ${loadaddr} - ${fdt_addr}; nfsbootargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs rw ip=${ipaddr}:${serverip}::${netmask}::eth0:off nfsroot=${serverip}:/tftpboot/rfs,nolock,v3,tcp earlycon pfe1_phy_addr=8 pfeng_mode=enable,sgmii,sgmii,rgmii ramdisk_addr=0x90000000 release_cpus=run cpu_trap; mp 1 release 0xa0000000; mp 2 release 0xa0000000; mp 3 release 0xa0000000; mp 4 release 0xa0000000; mp 5 release 0xa0000000; mp 6 release 0xa0000000; mp 7 release 0xa0000000; script=boot.scr serverip=10.0.0.1 skip_scmi_reset_agent=1 stderr=serial@401c8000 stdin=serial@401c8000 stdout=serial@401c8000 Environment size: 3581/8188 bytes => boot switch to partitions #0, OK mmc0 is current device 59970 bytes read in 7 ms (8.2 MiB/s) 9362112 bytes read in 394 ms (22.7 MiB/s) ## Booting kernel from Legacy Image at 80080000 ... Image Name: Image Type: AArch64 Linux Kernel Image (uncompressed) Data Size: 9362048 Bytes = 8.9 MiB Load Address: 80080000 Entry Point: 80080000 Verifying Checksum ... OK ## Flattened Device Tree blob at 83e00000 Booting using the fdt blob at 0x83e00000 Loading Kernel Image Using Device Tree in place at 0000000083e00000, end 0000000083e11fff fixup: pfe1: update phy addr to 0x8 Starting kernel ... board_cleanup_before_linux: QNX PFE code. ethernet@4033c000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! phy_startup() failed: -110FAILED: -110 Found PFE version 0x0101 (S32G3) Found PFE version 0x0101 (S32G3) pfe2 Waiting for PHY auto negotiation to complete......... TIMEOUT ! pfeng_netif pfe1: Failed to establish XPCS link on PFE1 ## Setting pfe_ts clock ... ## Setting ftm0_sys clock ... ## Setting ftm0_ext clock ... ## Setting ftm1_sys clock ... ## Setting ftm1_ext clock ... Reserving RAM region for PFE driver on EVB/RDB ClockCycles samples: 0 166386615 1 166386614 2 166386615 3 166386615 4 166386615 5 166386615 6 166386616 7 166386615 All ClockCycles offsets within tolerance Welcome to QNX Neutrino 7.1.0 on the NXP S32G399A RDB Board!! Starting watchdog... Starting serial driver ... Starting Networking driver (/dev/socket)... Utarting SPI driver (/dev/spi0,1,2,3,4,5)... Starting I2C 0/1/2/3/4 driver (/dev/i2c0,1,2,3,4)... Starting USDHC0 memory card driver... [00] Starting QSPI Flash driver... SIM="SDMMC" HBA="imx" [00,0,0] type=00 ver=05 resp=00 SDMMC: Starting USB host driver (/dev/usb/*) Detected QSPI Flash: Macronix MX25UW512, JEDEC 0xC2 - 0x813A, Size: 0x4000000 Launching devb-umass for /dev/usb/* ... U# slogi 2info Jan 01 00:00:00.022 random.4 low* 0 qcrypto: loading configuration file '/etc/qcrypto.conf' [qcrypto_common.c(190)] Jan 01 00:00:00.023 random.4..0 slog* 700 Random is using the Fortuna PRNG Jan 01 00:00:00.031 random.4 low 0 qcrypto: 'openssl' plugin loaded [qcrypto_plugins.c(354)] Jan 01 00:00:00.031 random.4..0 slog 700 Selecting timer as an entropy source Jan 01 00:00:00.031 random.4..0 slog 700 Registered path names Jan 01 00:00:00.031 random.4..0 slog 700 random: starting resmgr Jan 01 00:00:00.031 random.4..0 slog 700 random: Daemonizing the process Jan 01 00:00:00.041 devc_serlinflexd.7 slog* 0 serlinflexd_interrupt_attach: Attaching to interrupt 114 Jan 01 00:00:10.146 spi_master.8 normal* 0 Starting spi-master resource manager Jan 01 00:00:10.149 spi_master.9 normal* 0 Starting spi-master resource manager Jan 01 00:00:10.152 spi_master.10 normal* 0 Starting spi-master resource manager Jan 01 00:00:10.155 spi_master.11 normal* 0 Starting spi-master resource manager Jan 01 00:00:10.158 spi_master.12 normal* 0 Starting spi-master resource manager Jan 01 00:00:10.161 spi_master.13 normal* 0 Starting spi-master resource manager Jan 01 00:00:10.177 devb_sdmmc_mx8x.19 slog* 1800 devb-sdmmc-mx8x 1.00A (Jul 1 2026 14:10:37) Jan 01 00:00:10.178 devb_sdmmc_mx8x.19 slog 0 libcam.so (Jun 22 2020 21:33:15) bver 7010003 Jan 01 00:00:10.189 devb_sdmmc_mx8x.19 slog 1800 sdio_cd: insertion path 0, cd state 0x1 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 SD CID: Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 MID 0x27, OID 0x5048, PNM SD32G Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 PRV 0x62, PSN 0x6c62d196, MDT 4-2023 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 SD CSD: Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 CSD_STRUCTURE 1, SPEC_VERS 0, CCC 0x5b5 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 TAAC 14, NSAC 0, TRAN_SPEED 50 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 C_SIZE 59023, C_SIZE_MULT 0 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 READ_BL_LEN 9, WRITE_BL_LEN 9 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 ERASE GRP_SIZE 0, GRP_MULT 0, SIZE 127 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 blksz 512, sectors 60440576, dtr 25000000 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 SD SW CAPS: Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 bus mode 0x3, cmd sys 0x1 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 drv type 0x1, curr limit 0x1 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 dtr 50000000 Jan 01 00:00:10.239 devb_sdmmc_mx8x.19 slog 1800 CFG: Timing HS, DTR 50000000, Bus Width 4 bit Jan 01 00:00:10.240 devb_sdmmc_mx8x.19 slog 100 cam-disk.so (Jun 22 2020 21:33:17) Jan 01 00:00:10.242 devb_sdmmc_mx8x.19 slog 0 scsi_interpret_sense (sdmmc ptl-0:0:0): cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=1a, error=70, sense=5, asc=24, ascq=0 Jan 01 00:00:10.242 devb_sdmmc_mx8x.19 slog 0 scsi_interpret_sense (sdmmc ptl-0:0:0): cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=5a, error=70, sense=5, asc=24, ascq=0 Jan 01 00:00:10.242 devb_sdmmc_mx8x.19 slog 0 scsi_interpret_sense (sdmmc ptl-0:0:0): cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=5a, error=70, sense=5, asc=24, ascq=0 Jan 01 00:00:10.248 io_usb_otg.21 slog* 0 main(453)[tid:1]: io-usb-otg (Jun 13 2020 20:10:17) args: -d hcd-ehci-mx28 ioport=0x44064100,irq=243,ulpi,no_stream,verbose=5 Jan 01 00:00:10.250 devf_qspi_s32g.20 slog* 0 (devf t1::f3s_qspi_ident:73) Page size: 256 Jan 01 00:00:10.250 devf_qspi_s32g.20 slog 0 (devf t1::f3s_qspi_ident:74) Total chip size: 0x4000000, Unit size: 0x10000 Jan 01 00:00:10.254 io_usb_otg.21 slog 0 ehci_init: Initialiaing with sever version: 2 Jan 01 00:00:10.254 io_usb_otg.21 slog 0 ehci_controller_init(4292): devu-hcd-ehci-mx28.so (Aug 15 2023 16:44:48): args ulpi,no_stream,verbose=5 Jan 01 00:00:10.254 io_usb_otg.21 slog 8 usb_enum_port(94)[tid:1]: busno 0, parent -1, port 0, High speed Jan 01 00:00:10.255 io_usb_otg.21 slog 11 usb_client_descriptor_get(198)[tid:1]: (type 1, index 0, length 😎 Jan 01 00:00:10.255 io_usb_otg.21 slog 12 usb_device_set_address(245)[tid:1]: b:0 devno 0 Jan 01 00:00:10.255 io_usb_otg.21 slog 11 usb_client_descriptor_get(198)[tid:1]: (type 1, index 0, length 18) Jan 01 00:00:10.255 io_usb_otg.21 slog 11 usb_client_descriptor_get(198)[tid:1]: (type 2, index 0, length 9) Jan 01 00:00:10.255 io_usb_otg.21 slog 11 usb_client_descriptor_get(198)[tid:1]: (type 2, index 0, length 25) Jan 01 00:00:10.256 io_usb_otg.21 slog 8 usb_enum_port(141)[tid:1]: vid 0x0000, did 0x0000 enumerated(busno 0, devno 0:0) Jan 01 00:00:10.256 io_usb_otg.21 slog 11 hub_state_inserted(569)[tid:1]: bdentry 0, dentry 0 0 Jan 01 00:00:10.256 io_usb_otg.21 slog 13 hub_configuration_enable(263)[tid:1]: 1 Jan 01 00:00:10.358 io_usb_otg.21 slog 0 usbh_timeout_init(203)[tid:1]: Complete Jan 01 00:00:10.369 io_usb_otg.21 slog 0 read_vid_pid: ULPI VID 0x0424 PID 0x0009 Jan 01 00:00:10.369 io_usb_otg.21 slog 0 s32g_phy_set_vbus: set_vbus off Jan 01 00:00:10.383 io_usb_otg.21 slog 0 s32g_phy_set_vbus: set_vbus on Jan 01 00:00:10.394 io_usb_otg.21 slog 0 ehci_get_port_status(3557 0x44064100): port=0, tpstatus 10100 e_pstatus 8c001000 Jan 01 00:00:10.394 io_usb_otg.21 slog 8 usb_enum_port_extract(172)[tid:7]: (busno 0, pdevno 0, portno 1) Jan 01 00:00:10.394 io_usb_otg.21 slog 8 usb_enum_port_extract(192)[tid:7]: status (2) Jan 01 00:00:10.398 devb_umass.22 slog* 900 devb-umass 1.00A (Jun 22 2020 21:33:41) Jan 01 00:00:10.399 devb_umass.22 slog 0 libcam.so (Jun 22 2020 21:33:15) bver 7010003 Jan 01 00:00:10.400 io_usb_otg.21 slog 0 usbdi_client_connect(58)[tid:5]: pid 22 proc=proc/boot/devb-umass usbdi_client 51ba29fa80 Jan 01 00:00:10.400 io_usb_otg.21 slog 0 usbdi_resmgr_connect(310)[tid:5]: usbdi_resmgr_connect: pid 22 usbdi_client 51ba29fa80 Jan 01 00:00:10.400 devb_umass.22 slog 0 usbdi debug path /pps/usb/debug/ doesn't exist Jan 01 00:00:14.507 qconn.24 slog* 0 Couldn't initialize listen service: tcp (Address family not supported by protocol family) Re: S32G399A-RDB3 QNX PFE Driver Problems Hello, @Seneca  Thanks for sharing the log. There seems serdes issues existed during the booting phase, may I know if you had done the following modification? (to comment out the init_serdes() function) BR Chenyin Re: S32G399A-RDB3 QNX PFE Driver Problems Note: I not both pfe0 and pfe2 work at the same time. And when I ping them from an external machine it assigns pfe0 a funny mac address: arp -a | grep 192 ? (192.168.0.200) at 22:33:44:55:66:77 [ether] on enx00e04c680383 ? (192.168.0.202) at on enx00e04c680383 This is from qnx slog2info: Jan 01 00:00:58.251 iopkt.4121 main_buffer 0 duplicate IP address 192.168.0.200 sent from link address 22:33:44:55:66:77 Re: S32G399A-RDB3 QNX PFE Driver Problems Ok some more news: When I start the network client manually io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw and set a static ip for pfe0 ifconfig pfe0 192.168.0.200 netmask 255.255.255.0 ifconfig pfe0 down ifconfig pfe0 up I actually get a ping to an external address. Nevertheless, in ifconfig pfe0 still shows ethernet none. It seems to me there are problems negotiating interface speed # slog2info | grep pfe0 Jan 01 00:00:25.515 iopkt.4121 main_buffer 0 /proc/boot/devnp-pfe-2.so pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw Jan 01 00:00:25.517 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:1460]: MII mode configuration for pfe0/EMAC0 not found. Using SGMII. Jan 01 00:00:25.647 iopkt.4121 main_buffer 0 pfe0 Process 98332 (slog2info) exited status=0. Jan 01 00:00:25.647 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2124]: pfe0: Using static PHY mode, RESET=0 Jan 01 00:00:25.647 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2286]: Speed/duplex configuration for pfe0 not found. Using 1 Gbps/full-duplex. Jan 01 00:00:58.251 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2606]: pfe0: Disabling promiscuous mode Jan 01 00:00:58.251 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2606]: pfe0: Disabling promiscuous mode Jan 01 00:00:58.251 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2606]: pfe0: Disabling promiscuous mode Jan 01 00:00:58.251 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2606]: pfe0: Disabling promiscuous mode Jan 01 00:01:05.966 io_pkt_v6_hc.4121 slog 0 INF[src/pfe_drv.c:2606]: pfe0: Disabling promiscuous mode For Pfe2 it might already fail in uboot in the board_cleanup_before_linux pfe2 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Edit: I can also obtain a ping from pfe2 but it also seems to have problems negotiating the correct speed. I wonder if the above timeout is correct.

MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) Hi, I am using MCUXpresso Config Tools v26.x with an MCXN547 project and configuring an ADC -> eDMA transfer using the eDMA peripheral component. Configuration: eDMA Channel API mode: Transactional (transfer configuration) eDMA request: ADC1 FIFO A request Submit transfer: Enabled Auto stop request: Enabled Peripheral request: Enabled The generated code in peripherals.c contains: status = EDMA_SubmitTransfer(&DMA0_CH0_Handle, DMA0_CH0_Transfers_config, 1U); assert(status == kStatus_Success); However, no declaration for status is generated. As a result, the project fails to compile with: error: 'status' undeclared (first use in this function) Expected generated code would be either: status_t status; status = EDMA_SubmitTransfer(...); or: assert(kStatus_Success == EDMA_SubmitTransfer(...)); Has anyone seen this issue before? Is this a known code-generation bug in Config Tools, or is there an additional configuration option required when using "Submit transfer"? I can provide the generated peripherals.c and .mex configuration if needed. Thanks. Board Design MCXN Re: MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) Hi Thnaks for the fast responds. Yes, I have v26.03 of the tool Processors: MCXN547 (26.03.20) - MCX MCXN MCUXpresso SDK version 25.13.00 Package: mcuxsdk-core Version: 2.0.0 The 'Loop all transfeer' in the DMA0- Transfeer Configuration ad this code to DMA0_init() /* DMA0 loop transfer submit */ status = EDMA_SubmitLoopTransfer(&DMA0_CH0_Handle, DMA0_CH0_Transfers_config, 1U); assert(status == kStatus_Success); Where 'status' is not declared anywhere. Re: MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) Hi @tjo_dk  Thank you for your post! Could you please share the which package of MCXN547 are you using? Which version of Config tools are you using? is it 26.03? Which SDK version do you have installed?  Please share this information to replicate the setup on my end. Re: MCUXpresso generates invalid eDMA code when "Submit transfer" is enabled (MCXN547 ) Hi @tjo_dk, I tried to replicate the issue using the same configuration you are using. However, on my side, the code preview already includes the declaration of the status variable in the DMA0_init function.

imx93 sai - 简单音频卡设备树设置 您好，我正在查找以下设备的 simple-audio-card 的设备树设置： -imx93 是主控 音频编解码器为从属 TDM 16 插槽/32 位 并且必须满足以下时间要求： 任何提示都将不胜感激。 Linux Re: imx93 sai - simple-audio-card devicetree settings 你好， 遗憾的是，我们没有用于将 i.MX93 的 SAI 端口配置为 TDM 从设备的设备树示例。 您可以参考这篇文章： https://community.nxp.com/t5/i-MX-Processors/How-should-I-write-a-dts-file-to-use-16ch-TDM-with-quot-simple/mp/1625768#M203519 顺祝商祺！