Multi Source Translation Content

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Multi Source Translation Content

讨论

排序依据:
S32K324 write DFlash by FEE Hello, There is a question about S32K324 write DFlash by FEE: I plan to write approximately 50 bytes of data into the DFalsh of S32K324 using the FEE method. Since the hardware power supply on the circuit board has a backup time of around 0.743ms, I need to save the critical data within this time frame. Is it feasible to write to the DFlash using the FEE method? If it is not feasible, are there any other options? Thanks. Re: S32K324 write DFlash by FEE Hi@mmyjh_123 For a power-off backup window of 0.743 milliseconds, FEE is not safe. Even "close to 1 millisecond," the write execution time for a single Fls_MainFunction block already exceeds your available hold time. You could try using C40_Ip. Using Quad-page (1024 bits) program time, a 50-byte write would theoretically take 450 microseconds. However, within 0.743 milliseconds, any erase operation during an emergency hold is impossible; erasing an 8 KB sector could take up to 30 milliseconds. Therefore, when implementing this functionality using C40_Ip, always erase the DFLASH address to be programmed during idle periods. Furthermore, if the board can detect input voltage drops before the MCU power failure, commit operations should begin at the earliest possible threshold. Otherwise, add a large capacity capacitor/backup power to ensure the guaranteed window covers the worst-case software path and flash programming margin. The above is only a theoretical analysis; multiple real-world tests are recommended, ensuring sufficient design margins. Re: S32K324 write DFlash by FEE Ok, thanks a lot.
查看全文
I.MX93 - UUU emmc/sdcard LIBUSB_ERROR_TIMEOUT Error Hi NXP Team, We are trying to flash an i.MX93 board using a .wic image file provided by our team. We have two i.MX93 boards with the same hardware revision (SCH-96411 REV_B2). On one board, we are able to successfully flash the .wic image. However, when attempting to flash the same image on the second board, we encounter an error. We have tested both: emmc_all (for eMMC flashing) sd_all (using an SD card) In both cases, the same issue occurs on the second board. We would appreciate your support in troubleshooting and resolving this issue. Please let us know if you need any additional logs, error messages, or board information. Providing both uuu command and debugProviding both uuu command and debugProviding both uuu command and debugProviding both uuu command and debug uuu supported listuuu supported listuuu supported listuuu supported list i.mx93 usb identifiedi.mx93 usb identifiedi.mx93 usb identifiedi.mx93 usb identified Re: I.MX93 - UUU emmc/sdcard LIBUSB_ERROR_TIMEOUT Error Hi, Thank you for your interest in NXP Semiconductor products, It's good to have schematic identification, I would recommend confirming i.MX 93 top marking though. Confirm that they share TOP marking. Please download latest prebuilt image release from Linux. Finally, you are trying to flash both of them in serial download and do they have any fuses blown? Regards Re: I.MX93 - UUU emmc/sdcard LIBUSB_ERROR_TIMEOUT Error Hi Please find the attached images. We noticed some changes in the IC part numbers. We also tried flashing the SD card externally and then inserting it into the i.MX93 board, but we are still encountering the same issue. Additionally, we would like to bring to your attention that an image is already present in the eMMC, and the board is able to boot successfully from it. However, when we attempt to flash a new image, we encounter errors. Please find the attached debug logs below. One observation is that the preloaded image that came with the board is showing U-Boot SPL 2025.04, whereas the image we are attempting to use shows U-Boot SPL 2024.04. We downloaded the latest Linux 6.18.20_2.0.0 (i.MX93 EVK, FRDM) release. However, we could only find the 14x14 EVK WIC image and were unable to locate an 11x11 FRDM WIC image package. Could you please confirm whether the 14x14 image is the correct one to use for our board, or if there is a separate 11x11 FRDM image available? SD Card Boot: U-Boot SPL 2024.04+gde16f4f1722+p0 (Sep 02 2024 - 10:44:35 +0000) SOC: 0xa1009300 LC: 0x2040010 PMIC: PCA9451A PMIC: Over Drive Voltage Mode DDR: 3733MTS DDR: 3733MTS M33 prepare ok eMMC Boot: U-Boot SPL 2025.04-g99518e6b6f20 (Feb 02 2026 - 05:52:54 +0000) PMIC: PCA9451A PMIC: Over Drive Voltage Mode DDR: 3733MTS found DRAM 2CS_2GB DRAM matched M33 prepare ok Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x57800 by ROM_API NOTICE: TRDC init done NOTICE: BL31: v2.12.0(release):lf-6.18.2-1.0.0 NOTICE: BL31: Built : 07:53:18, Feb 10 2026 /****************************************************/ Regarding the fuse being blown, could you please let us know how we can verify whether the fuses have been programmed or blown on the board? Thank you. Issue board - imx93Issue board - imx93Issue board - imx93 Working board - imx93Working board - imx93Working board - imx93 Re: I.MX93 - UUU emmc/sdcard LIBUSB_ERROR_TIMEOUT Error I've got similar issues and per my understanding, the Chinese manufacturer who is behind FRDM series changed DDR RAM IC. This requires re-training DDR and update to u-boot, which was done for the board software, committed to nxp's u-boot repo, but the BSPs, Yocto layers and binary images on web site wasn't updated. Basically newer boards work with built-in u-boot only, everything your developers build with BSPs (and u-boot from 2024) will not even start due to invalid ddr configuration. You could confirm this issue by booting from board's u-boot, stop it using keyboard and then manually load your custom linux kernel and DT from the SD card.
查看全文
To simulate full load condition on the imx95lpddr5 evk How to simulate the full-load operating condition on the i.MX95 LPDDR5 EVK board. Is there any image available or pre-compiled application for this? I am using linux multimedia image. Re: To simulate full load condition on the imx95lpddr5 evk Hello, You can use this application note as reference: https://www.nxp.com/docs/en/application-note/AN14449.pdf There are different use case scenarios to reach high CPU load testing. I suggest you take a look in: CA55 CoreMark eIQ Benchmark (GPU) eIQ Benchmark (NPU) Best regards. 
查看全文
Support for mobile SDRAM (1V8) on RT1171CVM8B We are investigating the use of RT1171CVM8B on a new product. Does this i.MX RT family member support mobile (low power, 1.8V) SDRAM? It is not immediately clear from the datasheet, reference manual and available application notes and schematics that it does; it is inferred by the port drivers being specified for both 1V8 and 3V3 (NVCC_EMC1,2). It is also inferred from similar questions and answers in the affirmative for the i.MX RT1060 and RT1050. I would like to avoid a gotcha where some obscure part of the EMC or SDRAM interface fails with 1V8 parts;  Otherwise, why is it not clearly listed in the datasheet!? Kind regards, George Tzanatos. Re: Support for mobile SDRAM (1V8) on RT1171CVM8B Dear @georgetzanatos , The RT1171 does support Mobile SDRAM (low-power 1.8 V SDRAM). We agree that the current documentation does not state this explicitly. In the datasheet and reference manual, the memory protocol support and I/O voltage modes are described separately rather than being combined into a single "Mobile SDRAM support" statement. I understand your concern. Please feel free to use Mobile SDRAM on the RT1171. The key requirement is to configure the relevant NVCC_EMC1/2 power domains for 1.8V operation to match the SDRAM I/O voltage level.   Best Regards, Shelly
查看全文
MC9S08QG8 COMPILER, how do i get the c compiler for this chip well, i have a product developed with a MC9S08QG8 chip. i need to make some c code changes. i am using windows11. What software product do i use to generate the debugger for the chip. I am using a Wiztronics interface board from the pc usb port to the chip in my product. i have tried 8 different software packages, and none of them have the final debugger working. What softwage package do u suggest to use for debugging.  I am lost in ur devlopment center . Re: MC9S08QG8 COMPILER, how do i get the c compiler for this chip Hello The CodeWarrior tool version 11.1, is supported in windows 11, this tool supports different connections [P&E USB Multilink Universal / USB Multilink, P&E Cyclone, Open Source BDM, P&E Full chip simulation] You can download the tool from this link: CodeWarrior® for MCUs (Eclipse IDE) v11.1 I look for the MC9S08QG8 device and is available in this version. Best Regards, Luis
查看全文
FRDM-MCX N947 and OV5640 Camera I am currently porting a camera streaming pipeline (previously working on ESP32-S3) to the FRDM-MCXN947. The target resolution is 1080p capturing from an OV5640 camera module, processing via MCXN947 hardware accelerators, and streaming over SPI to an ESP32-C5 for Wi-Fi transmission. Hardware Pipeline: OV5640 Camera (DVP 8-bit) -> MCXN947 (FlexIO / SmartDMA) -> External PSRAM -> SPI -> ESP32-C5 -> Wi-Fi Current Progress & Setup SCCB / I2C Control: Fully functional. Camera register read/write operations succeed, and initialization passes. SmartDMA Baseline: Tested the stock NXP SDK SmartDMA examples for the OV7670 (using internal SRAM), which works as expected. Goal: Expand this to 1080p resolution using the OV5640 with external PSRAM buffering and FlexIO capture. Issue 1: FlexIO Pin Remapping & Invalid Data on D4/D5 When attempting 8-bit parallel capture via FlexIO, data lines D4 and D5 fail to read valid pixel data, while lines D0-D3, D6, and D7 behave correctly. Initial Pin Mapping: D0-D3: P1_4, P1_5, P1_6, P1_7 D4-D5: P3_4, P3_5 (Problematic: No valid pixel data) D6-D7: P1_10, P1_11 Control: VSYNC -> P1_18, HREF -> P1_19, XCLK -> P2_2 SCCB: SCL -> P3_2, SDA -> P3_3 Troubleshooting Attempted: I attempted remapping D4 and D5 to alternative pins and updated the corresponding FlexIO and Pin Mux configurations: Remapped D4: P2_8 Remapped D5: P2_9 Even with this remapping, D4 and D5 still do not capture valid data. Issue 2: SmartDMA Routing to External PSRAM for 1080p Because 1080p frame buffers exceed internal SRAM capacity, frames must be buffered into external PSRAM in real time. I am seeking best practices and configuration steps to configure SmartDMA to route incoming FlexIO camera data directly to external PSRAM without CPU intervention or frame tearing. Any insights, pin mapping suggestions, or reference code would be greatly appreciated! Board Design Communication & Control(I3C | I2C | SPI | FlexCAN | Ethernet | FlexIO) MCXN Re: FRDM-MCX N947 and OV5640 Camera Hi @DocMonster7  We have verified the official SDK example frdmmcxn947_smartdma_camera_flexio_mculcd_cm33_core0 on the FRDM-MCXN947 board with an OV7670 camera connected through the J9 camera interface. In this reference design, CAMERA_D4 and CAMERA_D5 are mapped to P3_4 and P3_5 respectively, and image capture works correctly. Based on this validation, P3_4 and P3_5 appear to be functioning correctly as camera data inputs. Therefore, the issue is unlikely to be caused by a limitation of these MCU pins themselves. We would recommend further checking the OV5640 hardware connections, signal integrity, pin mux configuration, and any modifications made to the original SmartDMA camera capture implementation. BR Harry
查看全文
IMX8MP linux uboot need to be set up with the default environment + extra variables IMX8MP linux uboot need to set up the default environmnet + few more variables after the flashing the bootloader via uuu. Use case: The IMX8MP SoM comes with default uboot from vendor. So for the first time writing need to flash the new uboot image, we set it to the default environment and set few more board specific environment variables on the factory process. So when I'm using the command, uuu -b emmc_all bl-imx8mp.bin image.wic.zst its using the builtin script uuu_version 1.4.149 # @_flash.bin | bootloader, which can extract from wic image # @_image [_flash.bin] | wic image burn to emmc. # This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ SDP: boot -f bl-imx8mp.bin -scanlimited 0x800000 # This command will be run when ROM support stream mode # i.MX8QXP, i.MX8QM SDPS: boot -scanterm -f bl-imx8mp.bin -scanlimited 0x800000 # These commands will be run when use SPL and will be skipped if no spl # SDPU will be deprecated. please use SDPV instead of SDPU # { SDPU: delay 1000 SDPU: write -f bl-imx8mp.bin -offset 0x57c00 SDPU: jump -scanlimited 0x800000 # } # These commands will be run when use SPL and will be skipped if no spl # if (SPL support SDPV) # { SDPV: delay 1000 SDPV: write -f bl-raptor-imx8mp.bin -skipspl -scanterm -scanlimited 0x800000 SDPV: jump -scanlimited 0x800000 # } FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${emmc_dev} FB: ucmd mmc dev ${emmc_dev} FB: flash -raw2sparse all image.wic.zst/* FB: flash -scanterm -scanlimited 0x800000 bootloader bl-imx8mp.bin FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 FB: done So my requirement is Flash the bootloader + rootfs / image Reset to defaults. Add new variables. Reboot with proper working new bootloader with expected env. But now its first flashing the rootfs and then the new bootloader. So when I executed env default -f -a, after it, it causes the default of environment of old bootloader in the SoM board. When it resetted, it starts then with new bootloader but with old defaults from old bootloader. Is there any suggestion to solve this issue? Re: IMX8MP linux uboot need to be set up with the default environment + extra variables Hello @jake4  Hope you are doing very well. You can try making your own custom script and add the below: FB: ucmd env default -f -a Example of complete script: uuu_version 1.4.149 SDP: boot -f bl-imx8mp.bin -scanlimited 0x800000 SDPS: boot -scanterm -f bl-imx8mp.bin -scanlimited 0x800000 SDPU: delay 1000 SDPU: write -f bl-imx8mp.bin -offset 0x57c00 SDPU: jump -scanlimited 0x800000 SDPV: delay 1000 SDPV: write -f bl-imx8mp.bin -skipspl -scanterm -scanlimited 0x800000 SDPV: jump -scanlimited 0x800000 FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${emmc_dev} FB: ucmd mmc dev ${emmc_dev} FB: flash -raw2sparse all image.wic.zst/* FB: flash -scanterm -scanlimited 0x800000 bootloader bl-imx8mp.bin FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 FB: ucmd env default -f -a FB: ucmd setenv board_version "1.0" FB: ucmd setenv my_custom_var "value" FB: ucmd saveenv FB: ucmd reset FB: done Best regards, Salas. Re: IMX8MP linux uboot need to be set up with the default environment + extra variables Hi @Manuel_Salas , We would have only eth fastboot enabled in the uboot , so we cant use the boot switch of SDP. Can you please let me know if there is a option with only the fastboot command. Thanks
查看全文
How use adjust SOI -EOI with use MC33 PT2000 IC just as topic, we need the help which can esstablished whole process , which use PT2000 to apply fule injection SOI -EOI measurement  H-Bridge Driver Small Engine Driver Solenoid Controller Re: How use adjust SOI -EOI with use MC33 PT2000 IC appreciated! Re: How use adjust SOI -EOI with use MC33 PT2000 IC Dear Kaijinbin,  there is an PT2000 end of injection detection application note available to download from the PT2000 product page, with a valid NDA.  If you don't have an NDA yet and you would like to sign one, please create a new ticket here and our representative for NDA matters will help you with the process.  Additionally please download the PT2000SWUG and PT2000-IDEUG from the FRDMPKPT2000EVM product page. You can download the PT2000 Developer Studio IDE and Software Files for Peak and Hold and DCDC software from the same page. You can then test the software example on the FRDMPKPT2000EVM Evaluation Board.  With Best Regards, Jozef
查看全文
Detail about S32K338 Good morning, I need to know if the S32K388 microcontroller has three independent cores, like the K324 (which has two), and if two of these cores can also be used in Lockstep. If I want one single core + one Lockstep core, should I use the K358? Thanks Re: Detail about S32K338 Hello @gianpiero_lenta , Lockstep operation is not a software-configurable feature that can be enabled between two independent cores. Instead, Lockstep is a dedicated hardware configuration implemented in specific S32K3 derivatives. Therefore, if your application requires one independent Cortex-M7 core together with a Lockstep Cortex-M7 pair, I recommend using the S32K358, which is designed with this hardware configuration. Best regards, Pavel
查看全文
rt1189 Boot Flow 1. As shown in the figure, does the "Authenticate Image" process verify the hash value during the SHA-512 hashing stage?  2. If I set the hash value, will the BootROM verify the image integrity? And if the BootROM verification fails, will it enter recovery mode? Re: rt1189 Boot Flow 1. Is hash verification enabled only when the signature authentication feature is enabled? How can hash verification be enabled independently? How can the device be transitioned into the OEM_CLOSED lifecycle state? 2. I will enable the Recovery Boot fuse. 3. My goal is to use an unencrypted image. The Boot ROM should calculate and verify the image hash. If the hash verification fails, the Boot ROM should enter the recovery boot flow and boot the recovery image from the LPSPI NOR Flash. Re: rt1189 Boot Flow Hi @yanyanwang , A1: Yes. RT1180 uses AHAB with two authentication layers: Signature layer: ECDSA (SHA-256 / SHA-384) verifies the Container header and image array entry (which stores each image's Hash). Hash layer: The ROM re-computes the digest of the loaded image body and compares it against the Hash stored in the image array entry. The SHA hashing stage in your figure is exactly this mandatory integrity check, which does verify the hash value. A2:The ROM always computes and compares the hash, but whether a failure is enforced depends on the device life cycle: the out-of-fab default is the Open configuration, where authentication runs but all authentication errors are ignored and the image still executes. Only after the device is moved to OEM_CLOSED will a hash mismatch actually block boot. Whether it enters recovery depends on the Recovery Boot fuse. if enabled, a primary-boot authentication failure triggers a re-load and re-authentication from the recovery device; if not enabled, the flow falls through to Serial Downloader / Fatal Mode / reset loop. Best regards, Gavin Re: rt1189 Boot Flow As shown in the figure above, if I only sign the image and do not encrypt it, will it be able to go through the bootrom verification flow? Additionally, with oem_close enabled, will it still be able to enter the bootrom verification flow?    
查看全文
关于FS2613芯片的选型 FS2613系列芯片功能是比较强大的,各个电源轨的数值和时序是可以编辑的。但我们没有太多软件开发的精力,也尽量不想自行OTP。请问有没有哪个型号,出厂的默认配置就是适配S32K358的?比如下图? Re: 关于FS2613芯片的选型 看附件 Re: 关于FS2613芯片的选型 嗯嗯,请问对于MFS2633AMDB2AD型号,默认上电后,以下各通道的输出电压分别是多少? VCORE、LDO1、LDO2、VREF、VBST;TRK1与TRK2跟随来源是哪里? Re: 关于FS2613芯片的选型 MFS2633AMDB2AD Search | NXP Semiconductors 你可以选择这个! Re: 关于FS2613芯片的选型 MFS2633AMDB2AD已停产,同等参数,我应该替换成:MFS2633HMDB2AD,对吧?
查看全文
iMX8 Nano Kernel updation from 5.15 to 6.18 Hi  While porting the kernel from 5.15 to 6.18 for the A53 core. facing an issue with rpmsg.  # dmesg -T | grep -Ei 'rpmsg|rproc' [Tue Oct 8 15:42:28 2024] imx rpmsg driver is registered. [Tue Oct 8 15:42:29 2024] imx-rproc imx8mn-cm7: error -ENOENT: Failed to enable clock [Tue Oct 8 15:42:29 2024] imx-rproc imx8mn-cm7: probe with driver imx-rproc failed with error -2 [Tue Oct 8 15:42:29 2024] remoteproc remoteproc0: releasing imx-rproc I am getting this error.When i searched this error online i was asked to add dummy clock in the dts as below  imx8mn-cm7 {     compatible = "fsl,imx8mn-cm7";     rsc-da = <0xb8000000>;     clocks = <&clk IMX8MN_CLK_DUMMY>;     mbox-names = "tx", "rx", "rxdb";     mboxes = <μ 0 1                                    μ 1 1                                    μ 3 1>;     memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;     status = "okay";   } Could u please let me is this the only the change required. What is the reason for this change. Regards Yadunath R Re: iMX8 Nano Kernel updation from 5.15 to 6.18 No — I would not treat clocks = <&clk IMX8MN_CLK_DUMMY>; as the only required change. It may be enough to get past the immediate -ENOENT: Failed to enable clock probe failure, but for i.MX8M Nano the important requirement is that the Cortex-M7 root clock must remain enabled when Linux loads/starts the M7 firmware. Reason: The imx-rproc node is expected to have a clock entry; AN5317 shows the i.MX8M remoteproc DTS node with compatible = "fsl,imx8mn-cm7" and a clocks = <...> property, plus mailbox and memory-region entries. Your error means the kernel 6.18 imx-rproc driver tried to get/enable the clock from that node and the clock lookup failed with -ENOENT , so probe aborted before remoteproc0 stayed registered. NXP’s AMP guidance says: “For i.MX 8M platforms, the root clock for M7/M4 must be kept always enabled by Linux to load the firmware code and start Cortex M7/M4.” It also says NXP Linux BSP keeps this root clock enabled when the M core is started from U-Boot; otherwise, if the M core is first started from Linux boot, drivers/clk/imx/clk-composite-8m.c must be updated to skip gate registration for the M core clock. So the change has two possible meanings: Dummy clock as compatibility workaround If kernel 6.18 imx-rproc requires a clocks property but the real M7 clock is intentionally not controlled through common clock framework, adding IMX8MN_CLK_DUMMY can satisfy the driver’s clock handle requirement and avoid -ENOENT . Real clock-control fix If Linux is actually responsible for loading/starting the M7, a dummy clock alone may hide the probe error but not guarantee the M7 clock is enabled. In that case you must ensure the M7/M4 root clock is kept on, either by the NXP BSP clock-driver handling or by the clk-composite-8m.c change described in AN5317. Also verify the rest of the remoteproc/rpmsg DTS, not only the clock line: imx8mn-cm7 {         compatible = "fsl,imx8mn-cm7";         rsc-da = <...>;         clocks = <&clk IMX8MN_CLK_DUMMY>;   /* or the correct M7 clock used by your BSP */         mbox-names = "tx", "rx", "rxdb";         mboxes = <μ 0 1>, <μ 1 1>, <μ 3 1>;         memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;         status = "okay"; }; The memory-region list is important because AN5317 states that this property must contain the memory sections used by the firmware ELF so remoteproc can reload it from sysfs. Recommended check path: If you start M7 from U-Boot , use the NXP flow such as prepare_mcore / bootaux , then boot Linux; AN5317 says this is the path where the BSP keeps the M core root clock enabled. If you start M7 from Linux remoteproc , confirm your 6.18 clock driver includes the NXP handling to keep the M core root clock always enabled; otherwise the dummy clock may only fix probe, not runtime start/load. Compare your DTS against the NXP imx8mn-*-rpmsg.dts for the same BSP release, especially clocks , mboxes , rsc-da , and reserved-memory layout. The dummy clock explains the immediate -ENOENT probe failure, but the real design requirement is to keep the i.MX8MN M7 root clock enabled; whether DTS alone is sufficient depends on whether your 6.18 BSP clock driver already preserves that clock.
查看全文
External Data Abort when calling Clock_Ip_Init() Hi there, I'm attempting to initialise some peripheral clocks using the RTD and S32 DS mex tool. (Note im generating the code in a M7 project, but actually building and running for a A53 project) However, an external data abort occurs inside Clock_Ip_Init(). Specifically, the call stack looks like this: Clock_Ip_Init -> Clock_Ip_InitClock() -> Clock_Ip_DisableCmuFcFceRefCntLfrefHfref(). This appears to be the first attempt to actually write to the CMU peripheral memory. The fault occurs on a LDR instruction on memory 0x4005'C028 which according the S32G3 memory map correctly resides within the CMU memory area. At this stage, the MMU is not enabled, but my understanding is an external data abort occurs outside the CPU/MMU and is probably linked to secure access or a "locked" peripheral. Am i right in saying the CMU needs to be made "accessible" from the A53 core in some manner prior calling Clock_Ip_Init()? If so, could you advise on the steps to do so? Best regards, Jonny Device = S32G399A Compiler = S32DS_GCC _11_4 Core = Cortex A53 Re: External Data Abort when calling Clock_Ip_Init() Hi,jonnyWHIS Thank you for contacting us. Do you intend to create bare-metal code running on the S32G A53 core in the S32DS IDE? BR Joey
查看全文
Unable to access MT29F64G08AECAB 8GB NAND Flash from T2081 processor Hi, I have a T2081 NXP processor connected to an external NAND Flash MT29F64G08AECAB via IFC. My goal is to run diagnostic test on this NAND Flash on code warrior or simply read the device and manufacturer ID of this device on Code Warrior (for which I have written the code). To achieve this goal, I have done the following already: 1. Configured LAW for the NAND IFC in the generated T2081QDS_init_core.tcl starting from 0xFF800000 and of size 1MB.  ## LAW3 to IFC - NAND   # LAWBARH   mem [CCSR_ADDR 0x000C30] = 0x00000000   # LAWBARL   mem [CCSR_ADDR 0x000C34] = 0xFF800000   # LAWAR   mem [CCSR_ADDR 0x000C38] = 0x81F00013 2. Also have configured the CSPR and FTIM registers corresponding to NAND like below : set NAND_CS   5 # NAND Flash, addr 0xFF800000, 1MB size, 8-bit NAND, ECC disable   # CSPR_EXT   mem [CCSR_ADDR [expr 0x12400C + $NAND_CS * 0x0C]] = 0x00000000   # CSPR   mem [CCSR_ADDR [expr 0x124010 + $NAND_CS * 0x0C]] = 0xFF800103   # AMASK   mem [CCSR_ADDR [expr 0x1240A0 + $NAND_CS * 0x0C]] = 0xFFFF0000   # CSOR   mem [CCSR_ADDR [expr 0x124130 + $NAND_CS * 0x0C]] = 0x01082100   # IFC_FTIM0   mem [CCSR_ADDR [expr 0x1241C0 + $NAND_CS * 0x30]] = 0x1E0B0507   # IFC_FTIM1   mem [CCSR_ADDR [expr 0x1241C4 + $NAND_CS * 0x30]] = 0x2929090B   # IFC_FTIM2   mem [CCSR_ADDR [expr 0x1241C8 + $NAND_CS * 0x30]] = 0x01203819   # IFC_FTIM3   mem [CCSR_ADDR [expr 0x1241CC + $NAND_CS * 0x30]] = 0x15000000 Note that there are 2 chip selects (CS5 and CS6) going from the processor to NAND and for the time being I am trying to access the first 4GB and hence configuring CS5 only. 3. Configured TLB: fine   1M TLB entry  5 : 0xFF800000 - 0xFF8FFFFF for NAND   cache-inhibited, guarded   reg ${CAM_GROUP}L2MMU_CAM5  = 0x5000000A1C08000000000000FF80000000000000FF800001 4. And since the device support for this MT29F64G08AECAB could not be found in the installed directory, I followed the manual and created a .xml for this device (for 4GB) which I have attached here. After doing all of this, when I run the diagnostic test for the NAND device on code warrior, I get the below error: As an alternative I tried to write a simple C code to read back the device id from this device. So I wrote the below code in code warrior and I have attached it here. And as a result when I read back the IFC_NAND_MDR register I get back 0x124E0000 which is not matching with the Device ID. I would like to know if I am doing something wrong or missing out something because I am unable to run the diagnostic test or read back the device id. I have attached the respective T2081QDS_init_core.tcl and also the respective schematics for reference. Regards, Nisarga R   QorIQ T2 Devices
查看全文
SPD 1.0.3 — eMcem.xdm XDM Schema Bug at Line 717 (EB Tresos Import Failure) I am reporting a bug in S32K3 Safety Peripheral Drivers (SPD) version 1.0.3, specifically in the eMcem module's XDM configuration file which prevents it from being imported into Elektrobit (EB) Tresos Studio. Environment ┌───────────────────┬─────────────────────────────────────────┐ │ Item │ Version / Path │ ├───────────────────┼─────────────────────────────────────────┤ │ MCU │ S32K344 (S32K3XX) │ ├───────────────────┼─────────────────────────────────────────┤ │ SPD │ S32K3_SPD 1.0.3 (S32K3_SAF_1.0.3_D2306) │ ├───────────────────┼─────────────────────────────────────────┤ │ RTD │ SW32K3_RTD 4.4 R21-11 3.0.0 P01 │ ├───────────────────┼─────────────────────────────────────────┤ │ EB Tresos │ 29.0.0 (installed at C:\EB\tresos) │ ├───────────────────┼─────────────────────────────────────────┤ │ S32 Design Studio │ 3.6.0 │ └───────────────────┴─────────────────────────────────────────┘ Issue Description When attempting to import the eMcem module (eMcem_TS_T40D34M10I3R0) into an EB Tresos project, the XDM parser throws the following error: ▎ "Invalid Attribute 'a' for tag 'a'" at line 717 of config/eMcem.xdm This prevents the eMcem module from being imported into any EB Tresos project entirely. Root Cause Analysis The file C:\NXP\S32K3_SPD_1.0.3\eclipse\plugins\eMcem_TS_T40D34M10I3R0\config\eMcem.xdm contains an invalid XDM schema structure at lines 715–718,in the RecoveryTimeoutEnabled parameter block: Buggy code (lines 715–718): VariantPreCompile The problem is the nested inside the element. According to the XDM schema (http://www.tresos.de/_projects/DataModel2/08/attribute.xsd), an element cannot contain another element as a child. The correct structure used by all other occurrences in the same file (e.g., the ReactionType parameter at lines 684–687)is: Correct code: VariantPreCompile This is the only occurrence of this malformed nesting in the entire eMcem.xdm file (20+ other IMPLEMENTATIONCONFIGCLASS blocks are correctly formed). It is clearly a copy-paste error during the SPD packaging process. Verification - The Bist module (Bist_TS_T40D34M10I3R0) and SafetyBase module (SafetyBase_TS_T40D34M10I3R0) from the same SPD 1.0.3 package do not have this bug —their .xdm files are correctly structured and import into EB Tresos without any errors. - I confirmed that the Bist.xdm file has zero occurrences of nested inside . Why This Is a Deadlock The META-INF/CRYPTOMANIFEST.MF and META-INF/CRYPTOMANIFESTSIG.MF files in the eMcem plugin contain DSA cryptographic signatures (Key ID: Freescale, Provider: dreisoft.tresos.launcher2.CryptoKeyProvider) for key plugin files including config/eMcem.xdm. Any modification to the .xdm file —even a single-line fix —breaks the DSA signature verification, causing EB Tresos to reject the module with a license/integrity error. This creates an irrecoverable deadlock: - Cannot import with the bug —XDM schema validation fails - Cannot fix the bug —DSA signature verification fails →license error - Cannot remove the signatures —EB Tresos fails to start (plugin integrity check) Request Please provide one of the following: 1. A hotfix release of SPD (or at minimum, a corrected eMcem.xdm file with updated CRYPTOMANIFEST signatures) compatible with our environment 2. An updated SPD version (e.g., 1.0.4 or newer) that includes this fix 3. A license re-activation or workaround that allows us to apply the necessary one-line fix to eMcem.xdm without triggering the DSA signature validation failure 4. Confirmation of whether a newer SPD version exists that resolves this issue, along with download/upgrade instructions This issue is blocking our S32K344 safety software integration, specifically the eMcem (Extended Microcontroller Error Manager) module configuration in EB Tresos. Additional Note The SPD 1.0.3 Release Notes state compatibility with RTD 3.0.0 / 3.0.0 P07. We are using RTD 4.4 (SW32K3_RTD_4.4_R21-11_3.0.0_P01). Could you also confirm the compatibility status between SPD 1.0.3 and RTD 4.4, and advise if a newer SPD version is required for RTD 4.x integration? --- Thank you for your assistance. Please let me know if you need any additional information or logs. Best regards. Re: SPD 1.0.3 — eMcem.xdm XDM Schema Bug at Line 717 (EB Tresos Import Failure) Hello @WuDiDi, The issue is also present in SPD 1.0.4. I can see that it has been fixed in SPD 1.0.5 and SPD 1.0.6: SPD version 1.0.5 is compatible with S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 5.0.0 and 4.0.0. Version 4.0.0 is supported for all derivatives except S32K3E ones (S32K39x and S32K36x). SPD version 1.0.6 is compatible with S32K3 Real-Time Drivers Version 7.0.0 + 6.0.0. Could you update to a newer RTD/SPD version? Many RTD, SPD bug has been fixed since version 1.0.3. Please note that NXP does not provide hotfixes for outdated software versions. Regarding SPD 1.0.3 compatibility, we can only guarantee functionality with the RTD version explicitly specified in the release notes. Compatibility with other RTD versions is not guaranteed. Regards, Daniel
查看全文
GUI Guider 2.0 图片存储类型选择Flash,无法显示
查看全文
需要S32DS的激活码 s32ds 安装的激活码 需要签署NDA 需要用到公司邮箱 没有公司邮箱 请确认下 怎么申请
查看全文
FS32K144UAT0VLLT哪个Time具备Input capture功能? 经理: 请教问题: (1)FS32K144UAT0VLLT规格书显示具备8个独立TIME,只看到FTM0,FTM1,FTM2,还有哪些也是TIME? (2)FS32K144UAT0VLLT的哪个TIME具备Input capture功能? 谢谢! Re: FS32K144UAT0VLLT哪个Time具备Input capture功能? Robin_Shen 你好,补充问题: 1. S32K-RM Rev14.2的Table 47-1. FTM instances and features 表格里,“Fault inputs"是什么参数? 2. S32K-RM Rev14.2手册多少页显示每个FTM都具备input capture功能? 谢谢! Re: FS32K144UAT0VLLT哪个Time具备Input capture功能? A1. 就是支持几路外部Fault输入,以S32K144为例Table 47-1写了支持4路,你可以在左侧表格看到FTM0_FLT0\1\2\3 这4路。 A2. 每个FTM都支持的功能,通常不会特地写出来。你按照Table 47-5. Channel Modes Selection配置寄存器就能实现47.5.5 Input Capture Mode 提到的input capture 模式了。
查看全文
PCA9615 I am writing to ask for help with the circuits at either end of dI2C communication - between two PCBs across a twisted wire bundle (DSDAP & DSDAM; DSCLP &  DSCLM; two GND; and two 5V lines). Leading up to this I decided to test Gemini so I regretably relied on AI to generate the parts of the two PCBs that related to the dI2C comms. Attached are the parts of the schematics associated with the dI2C. Unsuprisingly there is no comms between the boards, but my laziness and I have to say stupidity (leason learnt) has cost me a lot of time. I finally referred to the datasheet and the user manual for the demo board and one obvious difference is that there are 600 Ohm resistors between the positive lines (DSCLP and DSDAP) and VDD(B), the same from the negative lines (DSCLM and DSDAM) and VSS, and 120 Ohms between the respective positive and negative lines which apparently result in 100 Ohms between the positive and negative lines (I know that 1/600 + 1/120 = 1/600 + 5/600 = 100, but I can't see it electrically- maybe because I'm a mechanical engineer ??). Is the error (maybe one of a number of errors) caused by not having what may be considered a 600 Ohm pull up resistor, a 600 Ohm pull down resistor and a 120 Ohm resistor between the respective pair of wries (characteristic impedance of a 28 AWG twisted wire pair is about 100 Ohms cabling used in internal data links and USB/Ethernet configurations and 78 Ω to 95 Ω for standard spacing configurations using PVC or FEP insulated wires), but instead a simplified and likely erroneous version of just a single 100 Ohm resitor at either end of the connecting wire on the dI2C side of the PCA9615?  That is one significant difference between what AI gave me and what I see in Figs 1, 7, 8 and 9 of the datasheet. Another difference is that AI suggested different capacitor arrangements for the two PCBs whereas there's only one type of arrangement on the demo board (which I assume gets used on both sides of the dI2C connecting line). Further, there appears to be two capacitors for each of the VDDA pin and the VDDB pin - both ceramic capacitors (although my first thought was that the two yellow capacitors would have been tantalum type). Can I use the capacitor arrangement provided in the demo user manual and ignore what AI provided and shown in the attached? Another issue is that on the master side (on which I am using a 3.3V microcontroller) originally Ai instructed that the enable pin be conencted to the 5V line, but after having had the boards made, the lack of any function across the two boards in part prompted the AI to determined that the enable pin on the master side should have been connected to the 3.3V line (VDD(A) on the master board was connected to the 3.3V line). It then requested that all all supply to the enable pin on the master PCB be cut completely as a test. Can you please advise what supply, if any all, should be channeled to the EN pin? I will not be hot swapping any electrical hardware during test or final operation. I am considering implementing the above changes, but would really appreciate your help before I proceed further with costly boards. Re: PCA9615 Just a further thing regarding the capacitors, only decoupling capacitors were suggested for both VDDA and VDDB pins on the master PCB. Decoupling capacitors were also suggested for the slave PCB, but two additional capacitors were also suggested for the VDDB pin on slave PCB.  Re: PCA9615 Hello! Thank you for the detailed explanation. Please note that NXP provides an evaluation board for the PCA9615 family that can be used as a reference design for your implementation. We strongly recommend comparing your schematic against the PCA9615 evaluation board and its associated user manual, as the design includes the recommended differential I²C termination network, biasing resistors, decoupling capacitors, and EN pin connections that have been validated by NXP. Using the evaluation board schematic as a baseline is often the best approach when designing a custom PCA9615-based system, as it minimizes the risk of configuration or layout issues and follows the recommendations provided in the datasheet and application documentation. We suggest reviewing the evaluation board schematic and updating your design accordingly before committing to another PCB revision. https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/ic-i3c-bus-repeaters-buffers-and-extenders/pca9616pw-demo-board:OM13523UL Hope this helps!
查看全文
Reinstalling the S32DS environment and SDK package has caused previous projects to fail to compile Reinstalling the S32DS environment and SDK package has caused previous projects to fail to compile. In the past, my project used S32DS V2.2 and SDK RTM 2.0.0. Now, after reinstallation, I am using S32DS.ARM.2018.R1 and have also installed SDK RTM 2.0.0. But now I can't compile the project. It seems that it can't recognize the project itself. You can see the details in the picture. Re: Reinstalling the S32DS environment and SDK package has caused previous projects to fail to compi Hi @yangcao1234  Please note that S32K1 SDK RTM 2.0.0 was released specifically for S32DS for ARM 2018.R1 Update 6. It was not intended to be used with S32DS for ARM 2.2, and compatibility with that version is not guaranteed. BR, VaneB
查看全文