2413629_en-US

[#1]

I.MX95 LVDS clock output can not be changed

Hello everyone,

Q1:
I am working on single port LVDS display in the kernel lf-6.12y. I added my own panel config in driver/gpu/drm/panel/panel-simple.c, but the clock always be around 150Mhz when I was measuring the clock pins. But the other signals were working.

But, In the lf-6.18y, the clock can output correctly, and in dual-port mode clock changing is also ok in the both versions. Is it a known problem or my mistake. Because some reasons I hope I can solve this problem in lf-6.12y. 

The following are my settings

panel-simple.c:

static const struct display_timing lt9211_test_timing = {
.pixelclock = { 35916000, 35916000, 35916000 },
.hactive = { 280, 280, 280 },
.hfront_porch = { 40, 40, 40, },
.hback_porch = { 60, 60, 60 },
.hsync_len = { 30, 30, 30 },
.vactive = { 1424, 1424, 1424 },
.vfront_porch = { 15, 15, 15 },
.vback_porch = { 17, 17, 17},
.vsync_len = { 4, 4, 4 },
.flags = DISPLAY_FLAGS_DE_HIGH,
};

static const struct panel_desc lt9211_test = {
.timings = &lt9211_test_timing,
.bpc = 8,
.num_timings = 1,
.size = {
.width = 292,
.height = 111,
},
.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
.bus_flags = DRM_BUS_FLAG_DE_HIGH,
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};

my lvds config in the device-tree
&{/}{
    lvds1_panel {
        //compatible = "3ascreen,sa123hwv-l51";
       compatible = "lt9211_test";
       backlight = <&lvds_backlight>;
       status = "okay";
       port {
           panel_in: endpoint {
               remote-endpoint = <&lvds1_out>;
           };
       };
    };

Q2:
Under some conditions, the LVDS common voltage will not be aligned between the data lanes and clock in the same hardware. Or some signal missing like LVDS1 D3P has signal but D3N doesn't. Do you have ideas why this happened? Could some programs cause this?

Q3:
Is any config can shift the LVDS clock phase.

Thanks

Re: I.MX95 LVDS clock output can not be changed

Q1: It is likely a known lf-6.12y LVDS clock driver limitation/bug , not your panel-simple.c timing mistake. In single-port LVDS the driver/clock path is likely forcing or rounding to about 148.5/150 MHz . Since lf-6.18y works, the practical fix is to backport the LVDS/LDB clock changes from lf-6.18y to lf-6.12y , or patch the 6.12y LVDS driver/PLL clock table to allow your 35.916 MHz pixel clock.

git diff lf-6.12.y..lf-6.18.y -- \

drivers/gpu/drm/bridge/imx/imx95-ldb.c

drivers/phy/freescale/phy-fsl-imx8mp-lvds.c

drivers/clk/imx/clk-imx95-blk-ctl.c \

arch/arm64/boot/dts/freescale/imx95.dtsi \

arch/arm64/boot/dts/freescale/imx95-*-lvds*

Q2: If one LVDS pair side is missing, like D3P has signal but D3N has no signal , that is usually not caused by panel timing . Check:

• LVDS channel enablement: LVDS0/LVDS1 mismatch
• fsl,data-width / fsl,data-mapping
• PHY enablement
• connector or PCB open/short
• soldering issue
• termination/probing method
• possible damaged LVDS output pin

Software can cause wrong channel/lane/data-width setup, but one side of a differential pair missing strongly suggests hardware, pad, routing, termination, or measurement issue .

Q3: For i.MX8MP LVDS, there is no normal device-tree config to shift LVDS clock phase . Fix clock frequency/timing/PHY setup instead.

Re: I.MX95 LVDS clock output can not be changedThank you so much.
The lvds patch is so helpful.