MPC5777c - eTPU resolver ATO setting Hello. I got some question for MPC5777c and eTPU resolver. 1. SDADC I want to get Resolver's SIN and COS signal through this process : SDADC -> eDMA -> eTPU. There are SDADC_0, SDADC_1, SDADC_2, SDADC_3 eDMA_B channel request allocation on MPC5777c Reference Manual . There are SDADC_1, SDADC_2, SDADC_3, SDADC_4 trigger inputs on MPC5777c Reference Manual . Source Code doesn't have SDADC_0. Q1.  Why are the numbers of SDADC modules different when used as "SDADC trigger inputs" and when used in "eDMA_B channel request allocation"? Q2. In this case, SDADC -> eDMA -> eTPU Which SDADC_x, SDADC_y should I use to get the SIN and COS signals of the resolver through this process? 2.eTPU resolver ATO Channel Setting I'm trying to apply eTPU Resolver for my SW. The code in the figure below is included in etpuRDCCUG.pdf. ETPU_RESOLVER_ATO_CHAN /* chan_num_dma - etpuA1 generate dma request on channel DMA_A 28 */ Q3. Does this code mean that I need to use dma to access etpu to use ATO? Thanks for always helping me. Have a great day. Re: MPC5777c - eTPU resolver ATO setting The table is wrong, following is correct (reserved values should be at the end, not in the middle): SDADC modules are supposed to be marked as SDADC_1 to SDADC_4 (not 0-3). So in the table 4-6 it is incorrect (I have never noticed to be honest). Here I shared example code in the past: https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-SDADC-eTPU-triggered-GHS714/ta-p/1101495 However please be aware that once enabled the SDADC keeps running. There is no “Single conversion mode”. This requires that the CDATA register be continually drained by DMA or ISR. eTPU triggering is only related to synchronous start of these modules, nothing else. From SDADC to eTPU there may be signal about valid data available or conversion watchdog limit and opposite way, eTPU may gate interrupt or DMA transfers.

IMX93QSB - JTAG Flashing/Debugging via USB-C (FTDI FT4232H) on Windows/Linux Hello Everyone, I hope you're doing well. I’m currently seeking assistance on how to perform JTAG flashing and debugging on the IMX93QSB using the USB-C debug port. Specifically, I would like to know if this can be done using an FTDI FT4232H (Port A configured as JTAG) through the USB-C port. Is this functionality supported on both Windows 10/11 and Linux? I’ve reviewed the Reference Manual but couldn’t find clear guidance on this feature. Could someone confirm whether this is feasible, and if so, provide the necessary steps to make it work? Thank you in advance for your help! Re: IMX93QSB - JTAG Flashing/Debugging via USB-C (FTDI FT4232H) on Windows/Linux Hello, It is possible to debug using both methods, SEGGER J-Link and OpenOCD. Best regards. Re: IMX93QSB - JTAG Flashing/Debugging via USB-C (FTDI FT4232H) on Windows/Linux Hello, thank you for the clarification. Just to confirm, is debugging possible only with a SEGGER J-Link, or is it also feasible to use the USB-C port with FTDI FT4232H chip (configured with Port A as JTAG)? I’d like to understand if this setup would work for debugging, and if so, whether there are any specific configurations required. Thanks in advance for your assistance. BR Sergio Re: IMX93QSB - JTAG Flashing/Debugging via USB-C (FTDI FT4232H) on Windows/Linux Hello, It is not be possible to flash the board using JTAG, please note that JTAG in the i.MX devices, excluding the RT family, is used for the debug purpose only. Regarding OpenOCD, please take a look in the next presentation. Best regards.

Any special care is needed when I access to P3T1750DPZ over I2C? Hello,  Just to make sure, when I access to P3T1750DPZ over I2C as I2C target,  Any special care is needed to put this parts in I2C mode? (Strapping a pin, programming a register) Based on Figure 3, I believe that there are not special care is needed.  This part should respond to I2C controller as typical I2C target device when  I2C controller access to P3T1750DPZ with start condition. Regards, Norihiro Michigami AVNET Re: Any special care is needed when I access to P3T1750DPZ over I2C? You are correct. Thanks!

How Can I Set ICU(External Interrupt)? Hello, I am working with the S32K314 MCU and using S32DS version 3.5. In the [06_S32K3xx_Pins_and_Clocks_with_RTD_Training] document, it mentions that when updating the code in the Siul2_Icu Configuration part, the following files should be generated:   However, in my case, these files are not generated as expected. As a result, I am unable to use the parameters referenced in the example. How can I resolve this issue? Re: How Can I Set ICU(External Interrupt)? Always thank you @VaneB  Re: How Can I Set ICU(External Interrupt)? Hi @malove  I am afraid that the most viable option is to unistall the RTD version 3.0.0 from S32DS an install the version 4.0.0. Then generate a new project and then copy the application source files from your pre-existing project as well as any customizations you made to the project properties. Sorry for the inconvenience Re: How Can I Set ICU(External Interrupt)? thank you for answer @VaneB  How do I proceed to update RTD 3.0.0 to 4.0.0? Re: How Can I Set ICU(External Interrupt)? Hi @malove  Sorry for any inconvenience this may cause. The Siul2_Icu_Ip_BlinkLed was not provided in S32K3 Real-Time Drivers Version 3.0.0. I suggest you use the latest RTD versions. Re: How Can I Set ICU(External Interrupt)? Thank you for answer @VaneB  But, I still have some question. 1. I can't find 'Siul2_Icu_Ip_BlinkLed' example in my example from project 2. I am curious about what should be entered as an argument for Siul2_Icu_Ip_EnableInterrupt. The parameters in the photo I attached when asking a question are based on an old version, so what should I replace them with in the current version? Re: How Can I Set ICU(External Interrupt)? Hi @malove  This training presentation was done with an older version of RTD, so there are significant changes in newer versions. In this case, the names of the structures and definitions generated by ConfigTools differ from those mentioned in the presentation, for example: Use Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals); Instead of Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS0, g_pin_mux_InitConfigArr0); I suggest you to check the Siul2_Icu_Ip_BlinkLed example code (provided with the RTDs) for a better reference. BR, VaneB

Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Hello, On the S32K3x4 and 3x8 devices, can the pads that are configured as external WKPU inputs act as interrupt inputs when the device is awake or active? If yes, do they also share the same interrupt channels as the EIRQ[0-31] input channels? Thanks Sai Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Appreciate the clarification. I am accepting this response as a solution. Will reach out if further questions arise. Thanks Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Hi@spalukuru Here, PTD29 can be configured as WKPU[52], but can I use this to also generate interrupt? (enable IRER)(IREQ->IRER, my mistake in last reply) Yes. Just need to enable both the IRER(Interrupt Request Enable Register) in WKPU module and ISER(Interrupt Set Enable Register) in NVIC module. Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Thanks for the explanation with the example. In the same context, could you please help me understand what the case will be for this another example scenario - Here, PTD29 can be configured as WKPU[52], but can I use this to also generate interrupt? (enable IREQ) Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Hi@spalukuru The wakeup sources go to (red) and Interrupt controller(blue) separately. Thus, a wakeup event is able to occur without the enablement of NVIC module. A wakeup event is also capable to generate an interrupt event. For example:PTD20 If PTD20 is configured as EIRQ[25] first, and WKPU is enabled before entering sleep mode, then its wakeup will not affect EIRQ. Secondly, you can also configure PTD20 as WKPU port only. If IRER bit is enabled, it will also generate an NVIC interrupt. Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Hello, Thank you for the quick response. I understand there are 60 external pin wake up sources (WKPU[0]-WKPU[59]). If I want any of these external wake sources to act as an interrupt when the system is awake, does it take over or bother any of the 32 external interrupt channels (EIRQ[0:31]) that are - for example - already assigned to other sources? Thanks spalukuru Re: Can we use S32K3x4 and S32K3x8 External Wake up inputs as Interrupt inputs? Hi@spalukuru I thank the answer is yes, you can take a look at the below two diagram and the route is all to Interrupt Controller. So i thank for a pin used as external WKPU,if you enable IRER, it should be work as normal GPIO way.

Question about S32 Debug probe Error code Hello Team   May I ask one question about S32 Debug probe(with S32E)?   When I used the made project with S32 Debug probe, it is showing like below Error code :200 at the using Lunch Group for S32 Debugger. Also Console is showing like below. However if I used below S32 Debugger with M33, it is working well. I think that error is occurring with R core side...but I did not have any more information about the error.  May I ask, did you know about Error code : 200? Thank you. Debugging | Flash Programming Eclipse IDE Usage and Settings Re: Question about S32 Debug probe Error code Thanks Alexandra! Re: Question about S32 Debug probe Error code Hi @Luke_Chun , You can see additional information about the root cause of the failure in the GDB traces console. If the GDB traces does not appear in your eclipse console, then you need to make it visible from here: Window->Preferences look for GDB and make sure you have 'Show the GDB traces...' checked: Then you should see something like this in the IDE Console: As you can see I was able to reproduce your scenario - you have the board set up to as M33 boot core, and so this core will be enabled after power on (the R52 cores will be disabled). In order to debug the rest of the cores, the debugger will enable those cores - all this logic is encapsulated in some python scripts that are being run when you press the debug button - in the S32Debugger launch configuration, Initialization script. And so we have multiple python scripts for different scenarios: single core debug, multicore, attach from first instruction. In multicore use case, if the s32z2e2_generic_bareboard.py is used on the initial core , only that core will be enabled. Even if the same script is being set on the secondary cores, the enabling part of the secondary cores will be skipped.  The recommendation in multicore scenarios is to use on the initial core, M33 on you use case this python script: s32z2e2_generic_bareboard_all_cores.py .Just press Browse next to the script name got to s32z2e2 folder and choose this script. So your Debug Configuration on the M33 core, that is the initial core (the first core that will be launched in the debug session) should have this setting: Please give it a try. Hope this helps! Best regards, Alexandra

Binaries not found in rootfs even after adding recipe Hi, I am working on LX2160ARDB and trying to install some specific packages on it. I am using LLDP 6.1.22 SDK currently. To install u-boot-tools, i2c-tools and lksctp-tools, I tried these 2 ways. 1. Adding in the local.conf file IMAGE_INSTALL:append = " lksctp-tools u-boot-tools i2c-tools" 2. Adding in the ls-image-main.bb file IMAGE_INSTALL:append = " lksctp-tools u-boot-tools i2c-tools" When I build the image ls-image-main in both cases, image is getting built and generating the rootfs tar file. But the binaries related to these packages are nowhere present in the rootfs. Like i2c-tools should have i2cset, i2cget etc and u-boot-tools will have fw_printenv, fw_setenv and lksctp-tools will have checksctp. But none of these can be found anywhere in rootfs. I can find these recipes in the pn-buildlist when i use bitbake -g ls-image-main Kindly help me with this issue. Thanks in Advance Re: Binaries not found in rootfs even after adding recipe Thanks for your information. You need to add "lksctp-tools-utils" and "u-boot-fw-utils" in the list. Re: Binaries not found in rootfs even after adding recipe This worked but I also added the same in IMAGE_INSTALL:append previously, guess it should be placed before ${LAYERSCAPE_DEMO_SAMPLES}? @yipingwang  Re: Binaries not found in rootfs even after adding recipe Please remove i2c-tools in YOCTO-DEPENDS-LIST in sources/meta-nxp-desktop/recipes-extended/ubuntu/ubuntu-base-image.inc Please edit sources/meta-nxp-desktop/recipes-fsl/images/ls-image-main.bb as the following. IMAGE_INSTALL:append = " \         ${LAYERSCAPE_NETWORK_TOOLS} \         iperf2 \         makedevs lmsensors-sensors \         lksctp-tools lksctp-tools-utils u-boot-tools i2c-tools u-boot-fw-utils \         ${LAYERSCAPE_DEMO_SAMPLES} \ " $ bitbake ls-image-main

[Security] About CSEC Driver Dear NXPs： void CSEC_DRV_Init(csec_state_t * state) { DEV_ASSERT(state != NULL); g_csecStatePtr = state; g_csecStatePtr->cmdInProgress = false; INT_SYS_EnableIRQ(FTFC_IRQn); OSIF_TimeDelay(0U); } Q1: What is the purpose of OSIF_TimeDelay(0U); here? Q2: Can this function OSIF_TimeDelay(0U) be deleted? Re: [Security] About CSEC Driver Hi @Gideon  if you don't use FreeRTOS, you can delete it. Regards, Lukas

bitbake hang at Parsing recipes: 66% |#### I am using bitbake to compile Yocto, and I frequently encounter an issue where the compilation gets stuck at 66% during the parsing stage. It then hangs indefinitely, and I have to restart my computer multiple times to get it to proceed. Otherwise, it just stays stuck there and doesn't move forward. below is the error information, bitbake u-boot -c compile Loading cache: 100% |##############################################################| Time: 0:00:00 Loaded 5396 entries from dependency cache. Parsing recipes: 66% |######################################## | ETA: 0:00:00 wait some time will report error, ERROR: ExpansionError during parsing /home/oven/sandy/connevo/d02a_connevo_a53_sw/sources/meta-alb/recipes-extended/opendds/opendds_git.bb Traceback (most recent call last): File "/home/oven/sandy/connevo/d02a_connevo_a53_sw/sources/poky/bitbake/lib/bb/fetch2/__init__.py", line 1214, in srcrev_internal_helper(ud= , d= , name='default'): if srcrev == "AUTOINC": > srcrev = ud.method.latest_revision(ud, d, name) Could you please help me resolve this issue? thanks. Re: bitbake hang at Parsing recipes: 66% |#### Hello Guilherme, I tried many times, it seems your solution can solve me problem, thanks. Re: bitbake hang at Parsing recipes: 66% |#### Hello, @xlfd_1981  Thanks for your reply. It is suggested using the Ubuntu20.04 for building the BSP as what you have done.  I suggest trying executing the command "bitbake opendds -c cleanall", and then retry the test.  Also thank Guilherme for his valuable suggestions. BR Chenyin Re: bitbake hang at Parsing recipes: 66% |#### thanks chenyin, Yes, I use Ubuntu20.04 for the Yocto build, this version can appear this issue? Re: bitbake hang at Parsing recipes: 66% |#### Hello @xlfd_1981 , This issue occurs very frequently, specially when the connectivity to GitHub is not stable. The problem is in the recipe: meta-alb/recipes-extended/opendds/opendds_git.bb Particularly in the following statement: SRCREV = "${AUTOREV}" By using AUTOREV, it means they will poll the OpenDDS GitHub repository at the start of every build for checking if there are any updates. This is usually a bad idea. Fortunately, the solution is simple. Simply replace "${AUTOREV}" by a specific commit id, for instance: SRCREV = "58d1c0ca1c74986507773d50cce88fa1c8afb435"  And the problem goes away. Best regards, Guilherme Re: bitbake hang at Parsing recipes: 66% |#### Hello, @xlfd_1981  Thanks for your post. Sorry that I did not reproduce such issue, may I know if you are working with Ubuntu20.04 for the Yocto build? BR Chenyin BR Chenyin

Ubootコンソールについて ファイル「S32G2_LinuxBSP_42.0_Test_Specification.pdf」内 いつもこう言っています。 Ubootコンソールで登録NCF_S0確認してください md.l 0x4030C080 1 たとえば、「6.1.2テスト手順」 ステップス： 1. Linuxコンソールを起動します 2. adcを読み取るコマンドを実行します(少なくとも数日間実行する必要があります) エコー 1 > /sys/bus/iio/devices/iio:device0/scan_elements/in_voltage4_en エコー 4096 > /sys/bus/iio/devices/iio:device0/buffer/length つつ： する エコー 1 > /sys/bus/iio/devices/iio:device0/buffer/enable hexdump -e '"iio0 :" 8/2 "%04x " "\n"' /dev/iio:device0 |ヘッド-512 echo ワンショットが終わった! エコー 0 > /sys/bus/iio/devices/iio:device0/buffer/enable 完成です 3. UbootコンソールNCF_S0登録を確認します md.l 0x4030C080 1 ステップ1では、すでにLinuxコンソールを使用していますが、Ubootコンソールで登録NCF_S0確認するにはどうすればよいですか?再起動後? Re: Ubootコンソールについて devmem2をありがとう、それを手に入れました。

i.MX 8M Plus CPU module​ Hi, I just want to buy i.MX 8M Plus CPU module​ which comes with imx8m-plus dev board. Where to buy? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: i.MX 8M Plus CPU module​ Hi @vivek338  We don't provide individual CPU module, you can order another EVK.

Debugging issue Hi  I am facing an issue with S32D, when I am trying to debug,it gives me this error: I have reinstalled the S32D and Pemiro drivers,but still have the same issue. Re: Debugging issue Hi @Ayaz  Please create a blank "S32DS Application Project" and see if you get the same error. Also, try with an example code. Additionally, can you please try the following? Turn the switch off disconnect the 12-volts reconnect the 12-volts turn the switch on This power-up procedure manages that SBC starts with the disabled watchdog. Four orange LEDs indicate active 12, 5, 3.3, and 1.5 V power supply domains. Re: Debugging issue Hi This is not the first time, and I figured that the issue was from the evaluation board (S32k344 Q172), when I am switching to (S32k344 T172). I did not have this issue anymore, do you have any idea, how to fix this? Re: Debugging issue Hi @Ayaz  What project are you flashing to the target? Is it one of the example projects or a custom one? Is this the first time you ever tried or did it work previously and now fail? Are you using custom boards? Or is it an NXP board? B.R. VaneB

S32DS for flashing code into MPC5674F hi , I am using MPC5674F controller, using S32DS IDE with gcc compiler. I have 2 executable , one is boot and another is application executable.  How do i load both application with JTAG without erasing the boot software partion,  whenever i try to load any software it erases complete flash.  please help me how to achieve it, i am not able to find the documentation for the same. thanks Re: S32DS for flashing code into MPC5674F You may find it described in the following thread: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Debug-multiple-elf-files-in-S32-Design-Studio-with-GDB/ta-p/1121160

about Uboot Console In file "S32G2_LinuxBSP_42.0_Test_Specification.pdf" always said that: Check NCF_S0 register on the Uboot console md.l 0x4030C080 1 for example in "6.1.2 Test Procedure" Steps: 1. Boot to linux console 2. Run command to read the adc (need to run for a least a few day) echo 1 > /sys/bus/iio/devices/iio:device0/scan_elements/in_voltage4_en echo 4096 > /sys/bus/iio/devices/iio:device0/buffer/length while : do echo 1 > /sys/bus/iio/devices/iio:device0/buffer/enable hexdump -e '"iio0 :" 8/2 "%04x " "\n"' /dev/iio:device0 | head -512 echo One shot finished! echo 0 > /sys/bus/iio/devices/iio:device0/buffer/enable done 3. Check NCF_S0 register on the Uboot console md.l 0x4030C080 1 In step 1, I'm already in Linux console, how can I check NCF_S0 register on the Uboot console? after reboot? Re: about Uboot Console Thanks for devmem2, got it. Re: about Uboot Console Hello, @liujialu_2024  Thanks for your post. I do not think so, from my opinion, from step 3, I suggest checking the register status by using the devmem2 in Linux. BR Chenyin

bitbakeは解析レシピでハングアップ:66% |#### 私はbitbakeを使用してYoctoをコンパイルしていますが、解析段階でコンパイルが66%で止まるという問題に頻繁に遭遇します。その後、無期限にハングし、続行するにはコンピューターを複数回再起動する必要があります。そうしないと、そこに留まり、前進しません。 以下はエラー情報です。 bitbake u-boot -c コンパイル キャッシュの読み込み: 100% |##############################################################| Time: 0:00:00 Loaded 5396 entries from dependency cache. Parsing recipes: 66% |######################################## |到着予定時刻: 0:00:00 しばらく待つとエラーが報告されます。 エラー:/home/oven/sandy/connevo/d02a_connevo_a53_sw/sources/meta-alb/recipes-extended/opendds/opendds_git.bbの解析中にExpansionError トレースバック(最後の最後の呼び出し): ファイル「/home/oven/sandy/connevo/d02a_connevo_a53_sw/sources/poky/bitbake/lib/bb/fetch2/.py」、1214行目、srcrev_internal_helper(ud=__init__ 、d=, name='default')にあるDataSmartオブジェクト: srcrev == "AUTOINC"の場合: > srcrev = ud.method.latest_revision(ud,d, 名前) この問題を解決するのを手伝ってもらえますか?感謝。 日時:bitbakeハングで解析レシピ:66%|#### こんにちは、ギリェルメ、 私は何度も試しました、それはあなたの解決策が私の問題を解決できるようです、ありがとう。 日時:bitbakeハングで解析レシピ:66%|#### ありがとうChenyin、 はい、YoctoビルドにUbuntu20.04を使用していますが、このバージョンでこの問題が発生する可能性がありますか?

S32G399a u-boot hang at Loading Environment from MMC... OK Hello NXP experts I am using bsp41.0 ro debug s32g399a board, selet nor-flash boot mode, refer your user manual, modify ATF CLOCK config from 1.4G to 1.2G, #elif defined(PLAT_s32g3) #define S32GEN1_A53_MAX_FREQ            (1300 * MHZ) #define S32GEN1_A53_MIN_FREQ            (48 * MHZ) #define S32GEN1_ARM_PLL_VCO_MAX_FREQ        (2400 * MHZ) #define S32GEN1_ARM_PLL_PHI0_MAX_FREQ       (1200 * MHZ) #define S32GEN1_A53_FREQ            (1200 * MHZ) #define S32GEN1_ARM_PLL_VCO_FREQ        (2600 * MHZ) #define S32GEN1_ARM_PLL_PHI0_FREQ       (1200 * MHZ) #define S32GEN1_XBAR_2X_FREQ            (800 * MHZ) #define S32GEN1_PERIPH_PLL_PHI0_MIN_FREQ    (100 * MHZ) #define S32GEN1_PERIPH_PLL_PHI2_MIN_FREQ    (40 * MHZ) and align from 16 to 64 test step: 1. burn M7 bootloader(with de_init configuration) to nor-flash 2. select nor-flash boot mode 3. download bin file to nor-flash will FT tool 4. burn to SD-CARD with below command, dd if=fip.s32 of=/dev/sdb bs=512 skip=1 seek=1 conv=fsync,notrunc 5. power up,  u-boot hang at below lines, NOTICE: Reset status: Power-On Reset NOTICE: BL2: v2.10.0 (release):bsp41.0-2.10-dirty NOTICE: BL2: Built : 09:36:29, Oct 24 2024 NOTICE: BL2: Booting BL31 U-Boot 2022.04+g4744d0e2c8+p0 (Oct 24 2024 - 17:47:25 +0800) SoC: NXP S32G399A rev. 1.1 CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz Model: NXP S32G399A-RDB3 DRAM: 3.5 GiB Core: 306 devices, 25 uclasses, devicetree: board MMC: FSL_SDHC: 0 Loading Environment from MMC... OK please help to check from your side, thanks.   回复： S32G399a u-boot hang at Loading Environment from MMC... OK hi,xlfd_1981 Thank you for your reply and finding out the problem. BR Joey 回复： S32G399a u-boot hang at Loading Environment from MMC... OK thanks i have fixed this issue, your user manual have some mistake, the correct config is below, #define S32GEN1_A53_MAX_FREQ            (1300 * MHZ) #define S32GEN1_A53_MIN_FREQ            (48 * MHZ) #define S32GEN1_ARM_PLL_VCO_MAX_FREQ        (2600 * MHZ) #define S32GEN1_ARM_PLL_PHI0_MAX_FREQ       (1200 * MHZ) #define S32GEN1_A53_FREQ            (1200 * MHZ) #define S32GEN1_ARM_PLL_VCO_FREQ        (2400 * MHZ) #define S32GEN1_ARM_PLL_PHI0_FREQ       (1200 * MHZ) #define S32GEN1_XBAR_2X_FREQ            (800 * MHZ) #define S32GEN1_PERIPH_PLL_PHI0_MIN_FREQ    (100 * MHZ) #define S32GEN1_PERIPH_PLL_PHI2_MIN_FREQ    (40 * MHZ) 回复： S32G399a u-boot hang at Loading Environment from MMC... OK hi,xlfd_1981 Thank you for your interest in NXP Semiconductor products and the opportunity to serve you, I will gladly help you with this. you are using the Logger Demo and S32G_Bootloader_G3_LLCELOGGER_V1_2023_12_06.pdf? Please check the following configuration settings during operation. 1. Regarding the clk_enable() function leading to U-Boot hanging at Loading Environment from MMC. Please check if the LLCE Logger Demo has already removed CLOCK INIT. The bootloader has already been configured for clock, so reconfiguring the MCA L driver may cause conflicts. You can refer to the S32G_Bootloader_G3_LLCELOGGER_V1_2023_12_06 document, section 2.5/3.5, for a solution to resolve the clock conflicts between the bootloader, MCA L driver, and Linux. 2. Additionally, please check if there is any conflict between the SRAM mirrored load run address and the diagram below. Wish it helps you. If you still have question about it,please kindly let me know. BR Joey   回复： S32G399a u-boot hang at Loading Environment from MMC... OK Nxp Experts please help analyze this issue,thanks your user manual only mention about ATF codes updated, not mention uboot and kernel, so uboot and kernel need updated? How to update? 回复： S32G399a u-boot hang at Loading Environment from MMC... OK pls, we config m7 bootloader clock confict referring to S32G_Bootloader_G3_LLCELOGGER_V1_2023_12_06 documents, and I found the serdes module clk_enable() function leading u-boot hang at Loading Environment from MMC... OK, so may be clock confict between m7 abnd a53,  looking forward to your response, thanks.

关于Uboot控制台 在文件“S32G2_LinuxBSP_42.0_Test_Specification.pdf”中 总是说： 在Uboot控制台上检查NCF_S0寄存器 md.l 0x4030C080 1 例如在“6.1.2测试程序” 步骤： 1. 启动到 Linux 控制台 2.运行命令读取adc（需要运行至少几天） echo 1> /sys/bus/iio/devices/iio:device0/scan_elements/in_voltaic4_en echo 4096 > /sys/bus/iio/devices/iio:device0/buffer/length 尽管 ： 做 echo 1> / sys / bus / iio / devices / iio：device0 / buffer / enable hexdump -e '“iio0：”8/2“％04x”“\ n”'/ dev / iio：device0 | head -512 echo 一击完毕！ echo 0 > /sys/bus/iio/devices/iio:device0/buffer/enable 完毕 3. 在Uboot控制台上检查NCF_S0寄存器 md.l 0x4030C080 1 在步骤 1 中，我已经在 Linux 控制台中，如何在重启后检查 Uboot 控制台上的 NCF_S0 寄存器？ 回复：关于Uboot控制台 感谢 devmem2，明白了。

i.MX 6UltraLite MAC address Hi, I have a board with i.MX 6UltraLite (MCIMX6G2CVM05AB) and a LAN connection by the PHY transceiver KSZ8081RNBIA-TR of Microchip. I see the MAC address changes every time a reset the board. So I need some explanation: - Is the i.MX 6UltraLite who generates the MAC address? - Is there a way to have a univoque value for the MAC address? Best regards, Andrea Communication & Control(I3C | I2C | SPI | FlexCAN | Ethernet | FlexIO) Re: i.MX 6UltraLite MAC address Hello @AndreaB-17  If you want an unique MAC address you can burn the fuses: 21B_C620  -> Value of OTP Bank4 Word2 (MAC Address) (OCOTP_MAC0) 21B_C630 -> Value of OTP Bank4 Word3 (MAC Address) (OCOTP_MAC1) You can do it in U-boot with fuse prog. Best regards. Salas.

bitbake 在解析配方时挂起：66% |#### 我正在使用 bitbake 编译 Yocto，并且经常遇到编译在解析阶段卡在 66% 的问题。然后它会无限期挂起，我必须多次重新启动计算机才能使其继续。否则，它就只能停留在那里，无法前进。 以下是错误信息， bitbake u-boot -c 编译 加载缓存：100% |################################################################## ##| Time: 0:00:00 Loaded 5396 entries from dependency cache. Parsing recipes: 66% |## ######################################### | 预计到达时间：0:00:00 等一段时间会报错， 错误：解析 /home/oven/sandy/connevo/d02a_connevo_a53_sw/sources/meta-alb/recipes-extended/opendds/opendds_git.bb 时出现 ExpansionError 回溯（最近一次调用最后一次）： 文件“/home/oven/sandy/connevo/d02a_connevo_a53_sw/sources/poky/bitbake/lib/bb/fetch2/ __init__ .py”，第 1214 行，位于 srcrev_internal_helper（ud= ，d= ，name='default'）： 如果 srcrev == “AUTOINC”： > srcrev = ud.method.latest_revision(ud,d，名称） 你能帮我解决这个问题吗？谢谢。 回复：bitbake 挂在解析配方处：66% |#### 你好，Guilherme， 我尝试了很多次，看来您的解决方案可以解决我的问题，谢谢。 回复：bitbake 挂在解析配方处：66% |#### 谢谢chenyin， 是的，我使用Ubuntu20.04 进行 Yocto 构建，这个版本会出现这个问题吗？

Unwanted debugging -gdwarf-4 option set automatically in library projects by MCUXpresso Building headless (via CDT's generic org.eclipse.cdt.managedbuilder.core.headlessbuild application) or opening a project's properties in the GUI adds the -gdwarf-4 option to the com.crt.advproject.gcc.lib.release.option.debugging.other setting of the currently active configuration in library projects. While this setting also seems to be the default for executables, it does not get re-added there and I am not sure if it has the same effects when linking as with libraries. But with static libraries the resulting binaries are actually different as the debug info gets embedded into the object files that end up in the library, which is obviously unwanted. Re: Unwanted debugging -gdwarf-4 option set automatically in library projects by MCUXpresso I got your point. I'll recheck the way the Dwarf-related flag is enforced and do some improvements based on your inputs. We'll see if this fits in the upcoming IDE v11.10.0 release. Thanks, Adrian Re: Unwanted debugging -gdwarf-4 option set automatically in library projects by MCUXpresso The problem is that this actually enforces debug information to be present in the binary (no matter what the other "Debug level" is set to), which is undesired in our case. Software overriding developers is never a good idea. A warning would be more appropriate IMHO. Checking the "Debug level" for non-"none" before setting the value would also improve things (for my case at least). Re: Unwanted debugging -gdwarf-4 option set automatically in library projects by MCUXpresso Indeed, the IDE changes the implicit Dwarf format used by GCC. As you noticed, Dwarf 4 is now used instead of the default Dwarf 5. Long story short, this should not affect the actual code that's being generated, only the debug information is affected. We decided to enforce Dwarf 4 for debugging purposes, because of the many issues we've encountered with GDB, not being able to fully interpret Dwarf 5 (for now). If you want, you can always specify "-gdwarf-5" in the "Other debugging flags" field and the IDE will not change it in this case. Regards, Adrian Re: Unwanted debugging -gdwarf-4 option set automatically in library projects by MCUXpresso I have this issue as well.  On Mac OS Sonoma Version 14.2.1 with MCUXpresso IDE v11.9.0 [Build 2144] [2024-01-05] and MCUXpresso SDK Version 2.15.00 (801 2024-01-15) for MIMXRT1060-EVKB. Any new SDK Example project has the -gdwarf-4 debug option set in the IDE even though this flag is not specified in the config of the example (XML) or in the .cproject file. Re: Unwanted debugging -gdwarf-4 option set automatically in library projects by MCUXpresso Hello @stefanct  For better resolve your issue, please tell us your chip number. And detail steps about how to reproduce you issue.  BR Alice