S32G-VNP-RDB3 multi-core startup failed！ Hi nxp, 我们正在参照 AN13750.pdf 文档配置 S32G-VNP-RDB3 A 核 和 M 核启动环境。 软件配置如下： 1. EB tresos 29： 关闭 Crypto 、cryptoDal 和 RM。关闭 Secure boot  配置 bootloader ： 在 EBtresosStudio_EBtresosStudio29\workspace\Bootloader_S32G3XX_ASR_4.4_M7_noRM2\output 下面把 Crypto 、cryptoDal 和 RM 相关的 .c 和 .h 文件删除，不然会报错。 2. Integration_Reference_Examples_S32G3_2023_02 配置如下： Integration_Reference_Examples_S32G3_2023_02\code\framework\realtime\swc\bootloader\platforms\S32G3XX\src\Bootloader_Specific.c 加上配置： #define ASM_KEYWORD(x) __asm__ volatile(x)  // 不加会报错 ASM_KEYWORD 没定义  Bootloader.c 修改一句：static volatile uint32 ENABLE_BREAKPOINT_AT_MAIN = 1U; 3. S32DS 3.5 IVT 配置如下： 烧录： Then flash as per AN13750 explains: Erase from 0x0 to 0x400000. Then flash as follows: 0x0 -> Blob of the IVT shown previously 0x100000 -> fip.bin 0x200000 -> IPCF_Example_multi_instance_S32G399_M7_0.bin 烧录完成后，拨码启动，出现  pcie@40400000:RC/EP configuration not set correctly 报错，系统卡住 麻烦可以帮忙分析一下原因？谢谢！ Re: S32G-VNP-RDB3 multi-core startup failed！ Hi @chenyin_h , 手动进入 Linux 后，IPCF 的相关测试是正常的，没有发现有什么问题。 Re: S32G-VNP-RDB3 multi-core startup failed！ 您好 这种倒计时stuck的现象我没有遇见过，但应该是不正常的。 请问您手动进入Linux后，IPCF的相关测试是否正常？有没有其他问题发生？ BR Chenyin Re: S32G-VNP-RDB3 multi-core startup failed！ HI @chenyin_h  我按照你的说法，hwconfig 改为如下： hwconfig=serdes0:mode=disabled;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=2G5 但是启动后会卡在 uboot 倒计时 2 处，如下所示： 按回车进入 uboot 命令行，输入 boot 命令才能完成启动 linux，这样是正常的吗？ Re: S32G-VNP-RDB3 multi-core startup failed！ 您好 根据log所示，有可能是PCIe相关某些地方与M核程序有冲突，您可以简单这样尝试一下：先不要从flash启动bootloader，而是直接使用SD启动A核，在U-Boot中通过改变hwconfig的方式把disable PCIe，然后再重新使用flash来启动bootloader。这样有可能可以规避以上系统卡住的问题。 BR Chenyin

ICUモジュールを使用してPWMをキャプチャする場合、ISRルーチンが使用されますか 親愛なるNXPの専門家: ICUとeMIOSモジュールを使用してPWM信号をキャプチャしたいのですが。 チップはS32K312で、4 つの入力ピンは PTD13、PTD14、PTD17、PTE5 で、PTD13 を eMIOS チャネル 20 に、PTD 14 を eMIOS チャネル 21 に、PTD 17 を eMIOS チャネル 18 に、PTE5 を eMIOS チャネル 19 に割り当てます。 測定にはSAICを選びます。 割り込みについての質問をしたいのですが、つまり、割り込みをPWM信号をキャプチャするために使用 する必要がある かどうか、ポーリング機能、たとえばIcu_GetPulseWidth％を使用する場合にPWM信号がキャプチャされますか。 どうもありがとうございます

SJA1110 100BASE-T1 PHYマスター/スレーブの設定方法は? S32G-VNP-RDB2、BSP 42.0に搭載。 LinuxユーザースペースでSJA1110 100BASE-T1 PHYマスター/スレーブを設定するにはどうすればよいですか? Re:100BASE-T1 PHYマスター/スレーブSJA1110設定する方法は? たとえば、ボード上のJ100ケーブルの「100BASE-T1TRX8」TRX53の配線。 DSAを有効にし、インターフェイスtrx8(スレーブモードのデフォルト)を起動した後、次のようにマスターモードに設定します。 ethtool -s trx8 master-slave forced-master Re:100BASE-T1 PHYマスター/スレーブSJA1110設定する方法は? ご返信ありがとうございます。 しかし、「pfe-slave」は「100BASE-T1スレーブ」ではありません。 私の質問は、SJA1110 の 100BASE-T1 PHY をマスター/スレーブ モードに設定する方法です。

How to set SJA1110 100BASE-T1 PHY Master/Slave? On board S32G-VNP-RDB2 , BSP 42.0. How to set SJA1110 100BASE-T1 PHY master/slave in Linux user space? Re: How to set SJA1110 100BASE-T1 PHY Master/Slave? for example, the wires "100BASE-T1 TRX8" of J53 Cable on the board. after enable DSA and up the interface trx8(default in slave mode), set it to be master mode like this: ethtool -s trx8 master-slave forced-master Re: How to set SJA1110 100BASE-T1 PHY Master/Slave? Hello, @liujialu_2024  Thanks for your clarification and sorry for my previous misunderstanding on it. I could understand now that you are interested in the PHY Master/Slave, as far as I know,  PHY management for these ports can be done only from SJA1110 firmware, I do not think it could not be set from Linux user space directly with default S32G BSP. Actually the issue is not directly related with S32G, but SJA1110, for detailes, I suggest post your questions to the following board: https://community.nxp.com/t5/Other-NXP-Products/bd-p/other There should be more professional support for the internal components/features of SJA1110 itself. I apologize for your inconvenience. BR Chenyin Re: How to set SJA1110 100BASE-T1 PHY Master/Slave? Hello, @liujialu_2024  Thanks for your reply. PFE master/slave is a feature of PFE(A IP of S32G), while the 100BASE-T1 is a PHY(included in the SJA1110 Switch). There is not a feature called "100BASE-T1 slave". On RDBs, the PFE0 connected to port4 of the SJA1110 by default, while the PFE0 is configured as multi-instance(for example, M core master, A core slave), for example in one configuration, T100BASE-T1(port6) is connected to the network segment that targeted to the A core side, AR8035 PHY(port 2) connected to the network segment that targeted to the M core side,  then the traffic from T100BASE-T1 could be routed to the port4, then to A core via PFE0(PFE-slave),while the traffic from AR8035 could be routed to M core side also via PFE0(PFE master). Hope it will help.   BR Chenyin Re: How to set SJA1110 100BASE-T1 PHY Master/Slave? Thanks for your reply. But "pfe-slave" is not "100BASE-T1 slave". My question is how to set the 100BASE-T1 PHYs in SJA1110 to Master/Slave Mode. Re: How to set SJA1110 100BASE-T1 PHY Master/Slave? Hello, @liujialu_2024  Thanks for your post. For enabling the master/slave feature on RDB2, you may reference the chapter 7.3.4 from BSP42.0 UM. PFE master/slave is the function for PFE, on RDB2, by default, the PFE0 connect to the SJA1110, then the T100 port from sja1110 could be used for testing this feature. BR Chenyin

如何设置 SJA1110 100BASE-T1 PHY 主/从？ 板载S32G-VNP-RDB2 ，BSP 42.0。 如何在Linux用户空间中设置SJA1110 100BASE-T1 PHY主/从？ 回复：如何设置 SJA1110 100BASE-T1 PHY 主/从？ 例如，板上J53 Cable的线“100BASE-T1 TRX8”。 启用 DSA 并启动接口 trx8（从属模式的默认设置）后，将其设置为主模式，如下所示： ethtool -s trx8 master-slave forced-master 回复：如何设置 SJA1110 100BASE-T1 PHY 主/从？ 感谢您的回复。 但是“pfe-slave”不是“100BASE-T1 slave”。 我的问题是如何将 SJA1110 中的 100BASE-T1 PHY 设置为主/从模式。

will ISR routine be taken used if I take use of ICU module to capture PWM dear NXP experts: I want to take use of ICU and eMIOS module to capture PWM signal: the chip is S32K312 and the four input pins are PTD13、PTD14、PTD17 and PTE5 and I assign PTD13 to eMIOS channel 20；assign PTD 14 to eMIOS channel 21；assign PTD 17 to eMIOS channel 18；assign PTE5  to eMIOS channel 19。 I choose SAIC for measurement. I want to consult a question about the interrupt which I mean whether interrupt is must be taken use to capture the PWM signal and will PWM signal be captured if I take use of polling  function  for example Icu_GetPulseWidth()。 thanks a lot Re: will ISR routine be taken used if I take use of ICU module to capture PWM Hi @yin_qiu  When the eMIOS channel is configured for time measurements on input signals, the UC will captures and stores the value of the counter when the change of state occurs at the input. For SAIC mode it captures the value of the counter bus on an edge match (Rising, Falling or Toggle) of an input signal. For example if the IcuMesurementMode is defined as ICU_MODE_SIGNAL_MEASUREMENT and the IcuSignalMesurementProperty is ICU_DUTY_CYCLE, when the interrupt happends the Emios_Icu_Ip_IrqHandler() is executed, witch calls Emios_Icu_Ip_SignalMeasurementHandler(), that handles the signal measurement type interrupt. Then to acces the mesure values you can call Emios_Icu_Ip_GetDutyCycleValues() function.  NOTE: The function that will handle the interrupt will depend on IcuMesurementMode. BR, VaneB

Does 88W9098 support VHT, 40MHz at 2.4GHz band Dear sirs About 88W9098, does it support VHT, 40MHz with uAP / STA mode at 2.4GHz band? Thanks Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hello @Christine_Li  Thanks for your feedback.  I have no more question about this case.  you could close it.  Thanks Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  I just double confirmed with our internal team,  20 MHz VHT is also disabled for 2.4 GHz in our recent release. The feature is disabled from FW side. Please let me know whether have any other concerns on this case. Other wise, I will close this ticket for now. Please feel free to create new case to us if you need any help from us in the future. Have a nice day~ Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  Sorry for my late reply because of our internal India team is in public Diwali holiday last week. I received our internal team's feedback as below: The release now you are using(PCIE-WLAN-UART-BT-9098-U16-X86-17.68.1.p136.19-17.26.1.p136.19-MXM5X17366_P7_V0V1-MGPL) is very old(Released in 2022). Can you please help verify with the latest release(PCIE-WLAN-UART-BT-9098-U16-X86-17.68.1.p149.50-17.26.1.p149.50-MXM5X17405_P40_V0V1-MGPL)? VHT is already disabled in 2.4 GHz in most recent releases. Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hello @Christine_Li  The driver I used for vht 20/40 test is  PCIE-WLAN-UART-BT-9098-U16-X86-17.68.1.p136.19-17.26.1.p136.19-MXM5X17366_P7_V0V1-MGPL Thanks Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  Can you please let me know which release you verified VHT 20MHz in 2.4GHz? So that we can track internally and give you an answer about this. Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin   88W9098 and 88Q9098 follow the same SW, so yes It will be for both. Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hello @Christine_Li  One more question,  As you mentioned, the VHT is not supported in 2.4G and datasheet will be revised.  Is this revise/change also put on 88Q9098? Thanks Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hello @Christine_Li  Thanks for confirmation.  Does it means the VHT 20MHz we now succeed to activated will be disabled in future firmware? Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  I received our internal team's feedback as below: ====== We have discussed this topic and confirmed the VHT capability is not supported on the 2.4GHz, We are working internally to revise the datasheets. ======= Please do not hesitate to let me know if you have any other concerns related to this topic. Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  Thanks for you reply. Today, I checked it locally, and tried to set it to support VHT 40MHz in 2.4GHz, but seems there is no any VHT info in the association request frame(trying to connect to AP which is working in 2.4G 40MHz.). May I know how did you check for 20MHz(You mentioned successfully in 2.4GHz 20MHz)?  And also for your information, I escalated this issue into our internal AE team to ask further support. Once have any updates, I will let you know. Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hello @Christine_Li  Could you please help to confirm if 88W9098 VHT could support 40MHz in 2.4GHz band ? If yes, then we can setup again and  capture the log for you to see the issue? If it's not supported, then we will not go on this topic.  Thanks Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  Thanks for your reply. I got your point, could you provide the related successful sniffer logs for VHT 20MHz in 2.4GHz and failed sniffer logs for VHT 40MHz in 2.4GHz to me for further checking? Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hello @Christine_Li  Yes, we knew the 802.11ac VHT usually applied in 5GHz band.  However, in 88W9098 data sheet (page2) , it note "88W9098 also supports 802.11ac capabilities in the 2.4GHz band"  As we tested, the vht , 20MHz could be activated in 2.4ghz and linked with the other 88W9098.  However, in vht 40MHz, it seems the ap mode still could be setup but sta could not link with it. We would like to know if vht only support 20MHz in 2.4GHz band? Thanks Regards Moore Lin Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  As you know, VHT is required STA works in 5GHz, not 2.4GHz. So 88W9098 doesn't support VHT 40MHz at 2.4GHz, but support VHT 40MHz at 5GHz. Best regards, Christine. Re: Does 88W9098 support VHT, 40MHz at 2.4GHz band Hi, @Moore_Lin  Thanks for creating case to us. I will check it and reply to you soon. Best regards, Christine.

88W9098 是否支持 VHT、2.4GHz 频段 40MHz 敬启者 关于 88W9098，它是否支持 2.4GHz 频段的 VHT、40MHz 和 uAP / STA 模式？ 谢谢！ 此致 林摩尔 回复：88W9098 是否支持 VHT、2.4GHz 频段 40MHz 你好@Christine_Li 感谢您的反馈。 我对这个案子没有其他疑问了。 你可以关闭它。 谢谢！ 此致 林摩尔 回复：88W9098 是否支持 VHT、2.4GHz 频段 40MHz 你好@Christine_Li 我用于 vht 20/40 测试的驱动程序是 PCIE-WLAN-UART-BT-9098-U16-X86-17.68.1.p136.19-17.26.1.p136.19-MXM5X17366_P7_V0V1-MGPL 谢谢！ 此致 林摩尔 回复：88W9098 是否支持 VHT、2.4GHz 频段 40MHz 你好@Christine_Li 还有一个问题， 正如您所提到的，2.4G 不支持 VHT，并且数据表将被修改。 此修改/更改也适用于 88Q9098 吗？ 谢谢！ 此致 林摩尔 回复：88W9098 是否支持 VHT、2.4GHz 频段 40MHz 你好@Christine_Li 谢谢您的确认。 这是否意味着我们现在成功激活的 VHT 20MHz 将在未来的固件中被禁用？ 此致 林摩尔 回复：88W9098 是否支持 VHT、2.4GHz 频段 40MHz 你好@Christine_Li 您能否帮忙确认 88W9098 VHT 是否可以支持 2.4GHz 频段的 40MHz？ 如果是，那么我们可以重新设置并捕获日志以便您查看问题？ 如果不支持，那么我们就不会继续讨论这个话题。 谢谢！ 此致 林摩尔 回复：88W9098 是否支持 VHT、2.4GHz 频段 40MHz 你好@Christine_Li 是的，我们知道 802.11ac VHT 通常应用于 5GHz 频段。 然而，在 88W9098 数据表（第 2 页）中，它指出“88W9098 还支持 2.4GHz 频段的 802.11ac 功能” 正如我们所测试的，vht，20MHz 可以在 2.4ghz 下激活并与其他 88W9098 链接。 然而，在 vht 40MHz 中，似乎仍然可以设置 ap 模式，但 sta 无法与其链接。 我们想知道 vht 是否仅支持 2.4GHz 频段的 20MHz？ 谢谢！ 此致 林摩尔

在 PN7160 中存储 Wi-Fi 凭证 我正在使用 PN7160，我的设置如下： Karo QS93 SoM，运行嵌入式 Linux。 PN7160 NFC控制器。 它们通过 I2C 连接。 我已经完成了‘基本’设置。我正在使用 libnfc-nci 库和 nfcDemoApp。我可以成功轮询并检测 NFC 标签，也可以将其置于共享模式，以便我可以共享例如网络链接，这样当我将手机放在控制器上时，就会弹出一个窗口转到该链接。 有一件事我无法完成，那就是将 Wi-Fi 凭证存储到 NFC 控制器中。我试过： ./nfcDemoApp share --type=mime -m "application/vnd.wfa.wsc" -d " " 这似乎有点作用。当我在 Karo QS93 上运行此命令并在打开 NXP TagInfo 应用程序的情况下将手机触碰到 NFC 控制器时，我看到它正确接收了我的 WiFi SSID 和密码。 我尝试了其他方法： ./nfcDemoApp share --type=URI -u "wifi: ?T=WPA2&P= " 这也为我提供了 NXP TagInfo 应用程序中的结果。 但是，我想要实现的是，当我将手机靠近 NFC 控制器时，手机上会显示提示，询问我是否要连接到该 Wi-Fi 网络。使用 PN7160 可以实现这一点吗？如果可以，我是否缺少一些配置？或者我现在做错了？ 任何帮助都将不胜感激！ 回复：在 PN7160 中存储 Wi-Fi 凭证 我发现了它为什么不起作用。苹果无法扫描存储在 NFC 标签上的 Wi-Fi 凭证。例如，带有网络链接的 NFC 标签确实有效，但 Wi-Fi 对 Apple 不起作用。 回复：在 PN7160 中存储 Wi-Fi 凭证 PN7161 支持 PN7160 的所有功能以及“增强型非接触式轮询”。对于卡模拟演示，它们的行为相同。我猜这是IOS的兼容性问题。这个演示只是一个参考代码，客户可以根据自己的需要进行修改。我为此创建了一张内部票。但我无法得到确切的时间。 回复：在 PN7160 中存储 Wi-Fi 凭证 很抱歉造成混淆，但我实际上使用的是 PN7161，而不是我之前所说的 PN7160。 回复：在 PN7160 中存储 Wi-Fi 凭证 您能否更详细地介绍一下使用 Apple 手机进行的测试？没有提示确认或根本不起作用？是 iOS 版本问题，还是某些日志问题？ 回复：在 PN7160 中存储 Wi-Fi 凭证 好的！软件团队有答案的时候能告诉我吗？

Store Wi-Fi credentials in PN7160 I'm working with the PN7160, my setup is as follows: Karo QS93 SoM, running Embedded Linux. PN7160 NFC controller. They are connected over I2C. I have the 'basic' setup working. I'm using the libnfc-nci library, with the nfcDemoApp. I can successfully poll and detect an NFC tag and also I can put it into share mode, so that I can share for example a weblink, so that when I put my phone to the controller, I get a popup to go to that link. There is one thing I can't get to work, which is storing Wi-Fi credentials into the NFC controller. I tried: ./nfcDemoApp share --type=mime -m "application/vnd.wfa.wsc" -d " "  This seems to - kind of - work. When I run this command on the Karo QS93 and tap my phone to the NFC controller with the NXP TagInfo application open, I see that it correctly received my WiFi SSID and Password. Something else I tried: ./nfcDemoApp share --type=URI -u "wifi: ?T=WPA2&P= " This also gives me results in the NXP TagInfo application. However, what I am trying to achieve, is that when I tap my phone to the NFC controller, I get a prompt on my phone asking if I want to connect to that Wi-Fi network. Is this possible with the PN7160, and if yes am I missing some configuration? Or am I just doing it wrong now? Any help is appreciated! Re: Store Wi-Fi credentials in PN7160 I found out why it doesn't work. Apple just can not scan Wi-Fi credentials stored on an NFC tag. A NFC tag with weblink for example does work, just Wi-Fi it doesn't work for Apple. Re: Store Wi-Fi credentials in PN7160 The PN7161 supports all features of PN7160 plus "Enhanced Contactless Polling.  For the card emulation demo, they behave the same.    I guess it is  compatibility issue for IOS.  this demo is only a reference code, customer can modify it according to their needs.   I created an internal ticket for this.  but I can not get an exact time for it.   Re: Store Wi-Fi credentials in PN7160 I'm sorry for the confusion, but I am actually using the PN7161, not the PN7160 as I said before. Re: Store Wi-Fi credentials in PN7160 Hi Daniel, The Apple Phone has IOS 17.4.1. It doesn't get the prompt to connect to Wi-Fi at all. Also when using the app NXP TagInfo, nothing is received in there. We didn't try it yet with just storing plain text in the NFC controller (acting as tag), and trying to read that with the Apple Phone (in order to check: is the issue the phone itself, or the type of data stored in the tag). In the attachment, there are the configuration files libnfc-nci.conf & libnfc-nxp.conf with the settings we use right now. I have two questions: 1. Is it possible that some wrong settings in these configuration files, result in Apple Phone not working with NFC controller? 2. Will the PN7160 even work with Apple at all? I read something about PN7161 having ECP (Enhanced Contactless Polling), which PN7160 does not have. Is that needed to be able to work with Apple Phone? I look forward to your answers! Re: Store Wi-Fi credentials in PN7160 could you please be more detail about the test with Apple phone?  no prompt confirmation or not work at all?  the ios version, or some logs? Re: Store Wi-Fi credentials in PN7160 Alright! Can you please let me know when the software team has an answer? Re: Store Wi-Fi credentials in PN7160 You are right.  This is a known issue as far as I know,  I have already reported it to our software team. But I can not guarantee the time.  Regards Daniel Re: Store Wi-Fi credentials in PN7160 Hi, I got it working now, by using the ndef_emulation_example from the libnfc-nci_examples GitHub and modifying that to store Wi-Fi credentials. But now that you mention this Android/Apple thing: I noticed that it seems that only Android phones are capable of scanning the PN7160 acting as a tag, and they get the prompt to connect to the network. One person with an Apple has tried it, and it didn't work for him. What did work for the Apple person, was when we programmed Wi-Fi credentials into the NFC Sample Card (NTAG) that was provided with the PN7160 devkit. In that case, both Android and Apple could scan the card. Do you have any explanation for this? Can the PN7160 even work with Apple? Re: Store Wi-Fi credentials in PN7160 Hi   kowalski: Do you use Android phone or Apple phone? Regards Daniel

88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか 拝啓 88W9098について、VHT、2.4GHz帯のuAP / STAモードで40MHzをサポートしていますか? ありがとうございます よろしくお願いします。 ムーア・リン 日時:88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか こんにちは@Christine_Li  ご意見ありがとうございました。 このケースについては、これ以上疑問はありません。 あなたはそれを閉じることができます。 ありがとうございます よろしくお願いします。 ムーア・リン 日時:88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか こんにちは@Christine_Li  vht 20/40テストに使用したドライバーは PCIE-WLAN-UART-BT-9098-U16-X86-17.68.1.p136.19-17.26.1.p136.19-MXM5X17366_P7_V0V1-MGPLの ありがとうございます よろしくお願いします。 ムーア・リン 日時:88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか こんにちは@Christine_Li  もう1つの質問があります。 おっしゃるように、VHTは2.4Gではサポートされておらず、データシートは改訂されます。 この改訂/変更は 88Q9098 にも適用されますか? ありがとうございます よろしくお願いします。 ムーア・リン 日時:88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか こんにちは@Christine_Li  確認していただきありがとうございます。 これは、現在アクティブ化に成功しているVHT20MHzが将来のファームウェアで無効になるということですか? よろしくお願いします。 ムーア・リン 日時:88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか こんにちは@Christine_Li  88W9098 VHTが2.4GHz帯域で40MHzをサポートできるかどうかを確認するのを手伝ってくれませんか? はいの場合は、再度セットアップしてログをキャプチャして問題を確認できますか? サポートされていない場合は、このトピックには触れません。 ありがとうございます よろしくお願いします。 ムーア・リン 日時:88W9098はVHT、2.4GHz帯域で40MHzをサポートしていますか こんにちは@Christine_Li  はい、802.11ac VHTが通常5GHz帯域に適用されることは知っていました。 ただし、88W9098 のデータシート (2 ページ) には、「88W9098 は 2.4GHz 帯域の 802.11ac 機能もサポートする」と記載されています テストしたところ、vht , 20MHz は 2.4GHz でアクティブにし、他の 88W9098 とリンクできました。 ただし、vht 40MHzでは、APモードはまだ設定できるようですが、staはそれとリンクできませんでした。 vhtが2.4GHz帯域で20MHzのみをサポートしているかどうか知りたいのですが? ありがとうございます よろしくお願いします。 ムーア・リン

Wi-Fi資格情報をPN7160に保存します 私はPN7160を使用しており、セットアップは次のとおりです。 Karo QS93 SoM、組み込みLinuxを実行。 PN7160 NFCコントローラー。 これらはI2Cを介して接続されます。 「基本」セットアップが機能しています。私はlibnfc-nciライブラリをnfcDemoAppと一緒に使用しています。NFCタグを正常にポーリングして検出でき、また、共有モードにして、たとえばWebリンクを共有できるようにして、電話をコントローラーにつなげると、そのリンクに移動するためのポップアップが表示されるようにすることもできます。 私が仕事に取り掛からないことが1つあります、それはNFCコントローラーにWi-Fi資格情報を保存することです。やってみました： ./nfcDemoApp share --type=mime -m "application/vnd.wfa.wsc" -d " " これは - ある種 - うまくいくようです。Karo QS93でこのコマンドを実行し、NXP TagInfoアプリケーションを開いた状態で電話をNFCコントローラーにタップすると、WiFiSSIDとパスワードが正しく受信されたことがわかります。 私が試した他の何か: ./nfcDemoApp share --type=URI -u "wifi: ?T=WPA2&P= " これにより、NXP TagInfoアプリケーションでも結果が得られます。 しかし、私が達成しようとしているのは、電話をNFCコントローラーにタップすると、そのWi-Fiネットワークに接続するかどうかを尋ねるプロンプトが電話に表示されることです。これはPN7160で可能ですか、また可能な場合は、いくつかの構成が欠落していますか?それとも、私は今それを間違っているだけですか? どんな助けでも大歓迎です! Re:PN7160にWi-Fi資格情報を保存する なぜうまくいかないのかがわかりました。Appleは、NFCタグに保存されているWi-Fi資格情報をスキャンできません。たとえば、Webリンク付きのNFCタグは機能しますが、Wi-FiだけではAppleでは機能しません。 Re:PN7160にWi-Fi資格情報を保存する PN7161は、PN7160のすべての機能に加えて、「拡張非接触ポーリング」をサポートしています。カード エミュレーション デモでは、同じように動作します。IOSの互換性の問題だと思います。 このデモは参照コードにすぎず、お客様は必要に応じて変更できます。このために内部チケットを作成しました。しかし、私はそれのための正確な時間を得ることができません。 Re:PN7160にWi-Fi資格情報を保存する 混乱させてしまい申し訳ありませんが、実は先ほどのPN7160ではなく、PN7161を使っています。 Re:PN7160にWi-Fi資格情報を保存する Appleの電話でのテストについて詳しく教えてください。迅速な確認がないか、まったく機能しませんか? iOSバージョン、または一部のログ? Re:PN7160にWi-Fi資格情報を保存する 了解致しました！ソフトウェアチームから回答があったら教えていただけますか?

Flash erase in S32 Design studio Hi, I am working with S32K344 T172 EVB, and I accidentally issued the flash memory of the device. Now, when I try to flash my binary to the board via S32 Design Studio IDE, I receive the message: I also tried to enable Full chip erase, but then it said that the Mass erase not support Can anyone please help me to resolve this issue so that I can re-flash my board? Thanks Debugging | Flash Programming Re: Flash erase in S32 Design studio Hi @quangvuanh  I am afraid that when the Flash configuration is set to AB_SWAP, it is not possible to go back to the FULL_MEM configuration. Hence, only an AB_SWAP HSE Firmware image can be used in this configuration. Re: Flash erase in S32 Design studio I took the board from my colleague and now I dont know what was the last thing being flashed into the device. We will check again on our side. About HSE FW, what can I do to check the version of it? The FW was loaded into S32K3x4 EVB board before delivery, right? Update: I checked with my colleague and he has loaded another HSE firmware to the board HSE_FW_S32K3XX_0_2_1_0, with AB_SWAP algorithm. Well, I think now I know where the issue is Question:  Is there any way back so that I can reload HSE FULL_MEM to my board @VaneB ? Re: Flash erase in S32 Design studio Hi @quangvuanh  What was the last thing you uploaded to your device? How did you do it? Also, what type of HSE FW does your device have? Do you have a standard one or is premium one? Re: Flash erase in S32 Design studio @VaneB , Here are the registers ' values Re: Flash erase in S32 Design studio Hi @quangvuanh  It seems that the device is currently going into recovery mode. Can you please look for the registers FSR and GSR of the MU_B? That may help us identify if there is anything wrong occurring with the initialization of the HSE FW. B.R. VaneB Re: Flash erase in S32 Design studio Hi @VaneB  I follow your guideline, then the program pause here -> seem that your assumption is correct And the value stored at 0x4039C028  Re: Flash erase in S32 Design studio Hi @quangvuanh  In the debug configurations go to the Startup tab    and select the following:   With this, instead of loading the executable, it will simply be attached to the microcontroller, and with this, you can try to pause to see in which memory address it was running. If it is at address 0x20400100 or similar, it means that it is in recovery mode. Additionally, if you manage to pause the microphone, you could share an image of memory address 0x4039C028 to see the HSE GPR. Re: Flash erase in S32 Design studio Thanks @VaneB for replying me I think I am using HSE Arp, with this setup I can flash to other S32K344 EVBs Re: Flash erase in S32 Design studio Hi @quangvuanh  S32K3 devices do not support mass erase as shown in the last shared image.  Are you using HSE FULL MEM or AB SWAP? It looks like you are using the wrong program.  B.R. VaneB

S32K1xx devices, Current timer value issue Hi, At document 'S32K1xx Series Reference Manual, Rev. 13, 04/2020', 48.1.5 Current timer value, to read the register CVALn, it is recommended reading it during an LPIT interrupt service routine. Does this mean one of channel's ISR can read exact CVALs for other channel's? I want to manage the calibration of channel 1's CVAL at channel 0's ISR. Regards, Re: S32K1xx devices, Current timer value issue Thank you. The triple vote method is working. Regards, Re: S32K1xx devices, Current timer value issue Hi No, it is still recommended to use the triple vote method to read CVAL. Please refer to the discussion: Tolerance of LPIT CVAL (Current timer value)  Sorry for the inconvenience we bring you! Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

CMSIS LPSPI Driver Hello everyone, I am using SDK example mcxn9xxevk_cmsis_lpspi_edma_b2b_transfer_master for MCX-N947-EVK. I am trying to achieve SPI read and write in 16 clock cycles as shown in picture for the accelerometer ism330dlc. I have setup ARM_SPI_SS_MASTER_SW for the SPI SS pin control and tried to set it low/high manual before sending and receiving packet. The sequence of transmission is defined in platform_write and platform_read function. /* * Copyright 2017 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_device_registers.h" #include "fsl_debug_console.h" #include "fsl_lpspi_cmsis.h" #include "pin_mux.h" #include "clock_config.h" #include "board.h" #include "ism330dlc_reg.h" /******************************************************************************* * Definitions ******************************************************************************/ /* Master related */ #define DRIVER_MASTER_SPI Driver_SPI1 #define EXAMPLE_LPSPI_DEALY_COUNT 0xfffffU #define EXAMPLE_LPSPI_MASTER_DMA_BASEADDR DMA0 #define EXAMPLE_LPSPI_DMA_CLOCK kCLOCK_Dma0 #define EXAMPLE_LPSPI_CLOCK_FREQ CLOCK_GetLPFlexCommClkFreq(1u) #define TRANSFER_SIZE 64U /* Transfer dataSize */ #define TRANSFER_BAUDRATE 500000U /* Transfer baudrate - 500k */ /******************************************************************************* * Prototypes ******************************************************************************/ /* LPSPI user SignalEvent */ void LPSPI_MasterSignalEvent_t(uint32_t event); /******************************************************************************* * Variables ******************************************************************************/ AT_NONCACHEABLE_SECTION_INIT(uint8_t masterRxData[TRANSFER_SIZE]) = {0}; AT_NONCACHEABLE_SECTION_INIT(uint8_t masterTxData[TRANSFER_SIZE]) = {0}; volatile bool isTransferCompleted = false; volatile bool isMasterOnTransmit = false; volatile bool isMasterOnReceive = false; volatile uint32_t g_systickCounter = 20U; /******************************************************************************* * Code ******************************************************************************/ int32_t platform_write(void *handle, uint8_t Reg, const uint8_t *Bufp, uint16_t len); int32_t platform_read(void *handle, uint8_t Reg, uint8_t *Bufp, uint16_t len); uint32_t LPSPI1_GetFreq() { return EXAMPLE_LPSPI_CLOCK_FREQ; } void SysTick_Handler(void) { if (g_systickCounter != 0U) { g_systickCounter--; } } void LPSPI_MasterSignalEvent_t(uint32_t event) { if (true == isMasterOnReceive) { isMasterOnReceive = false; } if (true == isMasterOnTransmit) { isMasterOnTransmit = false; } isTransferCompleted = true; } /*! * @brief Main function */ int main(void) { /* attach FRO 12M to FLEXCOMM4 (debug console) */ CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); /* attach FRO 12M to FLEXCOMM1 */ CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); /* Enable DMA clock. */ CLOCK_EnableClock(EXAMPLE_LPSPI_DMA_CLOCK); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); /* DMA Mux init and EDMA init */ edma_config_t edmaConfig = {0}; EDMA_GetDefaultConfig(&edmaConfig); #if defined(BOARD_GetEDMAConfig) BOARD_GetEDMAConfig(edmaConfig); #endif EDMA_Init(EXAMPLE_LPSPI_MASTER_DMA_BASEADDR, &edmaConfig); #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT) DMAMUX_Init(EXAMPLE_LPSPI_MASTER_DMA_MUX_BASEADDR); #endif uint32_t errorCount; uint32_t loopCount = 1U; uint32_t i; static uint8_t whoamI=0; stmdev_ctx_t dev_ctx; /** xxxxxxx is the used part number **/ dev_ctx.write_reg = platform_write; dev_ctx.read_reg = platform_read; dev_ctx.handle = &DRIVER_MASTER_SPI; /*LPSPI master init*/ DRIVER_MASTER_SPI.Initialize(LPSPI_MasterSignalEvent_t); DRIVER_MASTER_SPI.PowerControl(ARM_POWER_FULL); //DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER, TRANSFER_BAUDRATE); DRIVER_MASTER_SPI.Control(ARM_SPI_MODE_MASTER | ARM_SPI_CPOL0_CPHA0| ARM_SPI_DATA_BITS(8)| ARM_SPI_MSB_LSB| ARM_SPI_SS_MASTER_SW,TRANSFER_BAUDRATE); DRIVER_MASTER_SPI.Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE); while (1) { ism330dlc_xl_data_rate_set(&dev_ctx, ISM330DLC_XL_ODR_12Hz5); /* Delay */ if (SysTick_Config(SystemCoreClock / 1000U)) { while (1) { } } /* Delay 1 ms */ g_systickCounter = 1U; while (g_systickCounter != 0U) { } } } int32_t platform_write(void *handle, uint8_t reg, const uint8_t *bufp, uint16_t len) { isTransferCompleted = false; isMasterOnTransmit = true; DRIVER_MASTER_SPI.Control(ARM_SPI_CONTROL_SS,ARM_SPI_SS_ACTIVE); DRIVER_MASTER_SPI.Send(®, 1U); while (!isTransferCompleted) { } isTransferCompleted = false; isMasterOnTransmit = true; DRIVER_MASTER_SPI.Send((uint8_t*) bufp, 1U); DRIVER_MASTER_SPI.Control(ARM_SPI_CONTROL_SS,ARM_SPI_SS_INACTIVE); while (!isTransferCompleted) { } return 0; } int32_t platform_read(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len) { reg|=0x80; isTransferCompleted = false; isMasterOnTransmit = true; DRIVER_MASTER_SPI.Control(ARM_SPI_CONTROL_SS,ARM_SPI_SS_ACTIVE); DRIVER_MASTER_SPI.Send(®, 1U); while (!isTransferCompleted) { } isTransferCompleted = false; isMasterOnReceive = true; DRIVER_MASTER_SPI.Receive((uint8_t*) bufp,len); while (!isTransferCompleted) { } DRIVER_MASTER_SPI.Control(ARM_SPI_CONTROL_SS,ARM_SPI_SS_INACTIVE); return 0; } the ism330dlc_xl_data_rate_set function implementation is: int32_t ism330dlc_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_xl_t val) { ism330dlc_ctrl1_xl_t ctrl1_xl; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); if (ret == 0) { ctrl1_xl.odr_xl = (uint8_t) val; ret = ism330dlc_write_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); } return ret; } this function call platform_write and platform_read for the ism330dlc_write_reg/ism330dlc_read_reg. The yellow marked one is the read cycle and the read one is the write cycle. The CS pin is pulled back to high after sending the register value for reading register value from the slave. Please guide.   Communication & Control(I3C | I2C | SPI | FlexCAN | Ethernet | FlexIO) MCXN Re: CMSIS Driver SPI I shifted to SDK example mcxn9xxevk_lpspi_edma_b2b_transfer_master. The CS pin is pulled high after each byte transfer in the default example.  To solve this, I added this before beginning of every transfer. Now, the CS is kept low during the whole transmission. LPSPI_SetPCSContinous(EXAMPLE_LPSPI_MASTER_BASEADDR, (uint8_t)1); Re: CMSIS Driver SPI Hi, I have checked your code, it appears this is not SDK example code. If you want to set the SPI in master mode and use DMA to transfer code, I suppose that you can not use a GPIO as CS signal to select slave spi device. You have to use FC_PCSx signal to connect /CS of slave SPI, which is driven automatically when the SPI master transfers data, it toggles for each byte or word. If you do want to use GPIO pin, I suppose you can clear the GPIO before the DMA transfers data, after all data has been transferred, you can set the GPIO. The drawback of the method is GPIO is kept low during the transferring process. This is the pin assignment for SPI_PCSx Hope it can help you BR XiangJun Rong Re: CMSIS Driver SPI

NMI Handler (Non Maskable Interrupt) not triggering in S32K388 Hi Team, We are using the S32K388 eval board. We want to trigger the non-maskable interrupt when the pin PTD3 value changes. We have configured PTD3 pin mode as SYSTEM_NMI_B. The pin PTD24 is configured as the GPIO output mode. We have connected the PTD3 & PTD24 via a wire on the IO matrix of the Eval board. The code is written to toggle the PTD24 pin. Since this pin is connected to PTD3 which is configured as SYSTEM_NMI_B, we were expecting the breakpoint kept inside the NMI_Handler function to hit. But the breakpoint is never hit. We also have enabled this interrupt using the API NVIC_EnableIRQ(NonMaskableInt_IRQn). We are using the example code of Icu driver and did the changes as per our requirement. Is there any other configuration parameter/ any code changes we need to do in order to enable this NMI interrupt? S32K3 #NMI #Interrupt #ICU Re: NMI Handler (Non Maskable Interrupt) not triggering in S32K388 Configured the WakeupNMI configurations in the Icu module. And referred this in one of the IcuChannels. After this the NMI handler is being triggered. Re: NMI Handler (Non Maskable Interrupt) not triggering in S32K388 Hi Team, Can someone from NXP check this please? Re: NMI Handler (Non Maskable Interrupt) not triggering in S32K388 Hi Team, Can you please look into this query?

Clocks in S32G2 platform Hi, I am sorry if this is a dumb question. I am just starting with embedded projects. I am trying to make sense of the RM of the S32G2 platform to implement interfacing with an eMMC and I saw the term 'clk_src_0' mentioned a lot of times but nowhere is it defined what 'clk_src_0' or 'clk_src_2' is. Can you please let me know what that is ? Is it a generic term to mention the main clock source or is it something else ? So much thanks. Re: Clocks in S32G2 platform Thank you so much for this. I was searching the whole document for the string 'clk_src_0' and came up with nothing. Thanks again!! Re: Clocks in S32G2 platform Hi @Arbabmir, You can find the definition of the clock source numbers at the 24. Clock Generation Module Chapter. [page 859, S32G2 Reference Manual, Rev. 8, 02/2024] The table it refers to is at the 23. Clocking Chapter. [page 801, S32G2 Reference Manual, Rev. 8, 02/2024] To see all the clocks sources please refers to this table at the reference manual.

iMX8QXP I2C RPBUS configuration Hi NXP Team, We are using iMX8QXP as our SoC with our custom design. In the EVK when we disable the i2c_rpbus_5, i2c_rpbus_15 nodes in the imx8x-mek-rpmsg.dtsi file we are facing failure in booting of A35. We are using the default power mode application in the M4 side. Hence please let us know on what basis we need to allocate the i2c_rpbus nodes and whether is it mandatory to allocate i2c_rpbus nodes if we wish to use M4 along with A35?. Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, We think the issue is sorted out once we change as per your suggestion in the mek.h file. Thanks for your support. Will check with you if any other issue arises. Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  From the error log, it seems relate to vring and vdev address, but i just calculate the vdev and vring address, there are in range of 2GB. Maybe this issue is caused by incorrect DRAM definition in Uboot. The Linux still use 3GB DRAM size to map address , this could be the reason about address NULL issue. You can try to modify  include/configs/imx8qxp_mek.h in Uboot like this. Best Regards Zhiming  Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, We are using 2GiB of DRAM in our design. Can you please let me know if any guide is available for changing the address? Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  Here are vdevbuffer and vring definitions in mek dtsi, are you using same DRAM size? If not, you need adjust these address. reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; vdev0vring0: vdev0vring0@90000000 { reg = <0 0x90000000 0 0x8000>; no-map; }; vdev0vring1: vdev0vring1@90008000 { reg = <0 0x90008000 0 0x8000>; no-map; }; vdev1vring0: vdev1vring0@90010000 { reg = <0 0x90010000 0 0x8000>; no-map; }; vdev1vring1: vdev1vring1@90018000 { reg = <0 0x90018000 0 0x8000>; no-map; }; rsc_table: rsc_table@900ff000 { reg = <0 0x900ff000 0 0x1000>; no-map; }; vdevbuffer: vdevbuffer { compatible = "shared-dma-pool"; reg = <0 0x90400000 0 0x100000>; no-map; }; }; Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, We haven't modified the U-boot source code other than the dts, defconfig and board file changes. We have used "flash_linux_m4" flag for booting with M4 and "flash" flag for booting without M4 in the imx-mkimage compilation. Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  Have you load the m4_0.bin in uboot? Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, Please find the dtsi files in the attachment (dtsi.zip). Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  Can you share your device tree file? Thanks Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, We have received our target board and when I boot the board with M4 having only one i2c bus (mapped to i2c1 in the mek.dtsi file) in the rpmsg.dtsi file, we're facing kernel panic from imx-rproc driver and when I boot the board without M4 there is no issue in booting. Attaching the logs of the kernel panic below. Please look into it and let me know what is the RCA of this issue. Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, Thanks for the support. Regards, Ranjith Kumar Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  Yes, of course Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, Thanks for the detailed clarification. My query is like in our target device we won't be having any of the slaves mentioned in the rpmsg.dtsi file, so in this case can we disable all the i2c_rpbus nodes? Regards, Ranjith Kumar Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  It depends on which i2c_rpbus node, for example, if you need use typec port ,you can't disable or comment i2c_rpbus_1. For pca9557_a and pca9557_b in i2c_rpbus_15 node, they could be used for gpio control in other devices, so please handle these devices with care. But for other sensor devices, you can disable them. Best Regards Zhiming Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, Thanks for the information. By disabling the slaves present in the i2c_rpbus_5 we're able to boot the board. One additional query, is it mandatory to have i2c_rpbus nodes or else can we disable all the i2c_rpbus nodes along with it's associated slaves? Regards, Ranjith Kumar. Re: iMX8QXP I2C RPBUS configuration Hi @ranjithkumar_kv  If you have disabled the i2c_rpbus_5 node, please also disabled it's slave devices or comment the whole i2c_rpbus_5 node in rpmsg.dtsi Re: iMX8QXP I2C RPBUS configuration Hi Zhiming, Please find the kernel boot logs in the attachment (kernel_error_logs.txt). Regards, Ranjith Kumar Re: iMX8QXP I2C RPBUS configuration Hello @ranjithkumar_kv  Can you provide kernel boot log? Best Regards Zhiming

T1024 ehernetインターフェースが起動しない ねえ皆さん！ t1024ベースのボードのイメージをまとめようとしました。建物には、Buildrootツールと新しいカーネル6.1.44を使用しました。しかし、イーサネットインターフェースは立ち上がりませんが ip a インターフェイスのリストを表示する 1: lo: mtu 65536 qdisc noqueue qlen 1000 link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 inet 127.0.0.1/8 scope host lo valid_lft forever preferred_lft forever inet6 ::1/128 scope host valid_lft forever preferred_lft forever 2: eth0: mtu 1500 qdisc noop qlen 1000 link/ether 00:00:00:00:01:00 brd ff:ff:ff:ff:ff:ff 3: eth1: mtu 1500 qdisc noop qlen 1000 link/ether 00:00:00:00:01:01 brd ff:ff:ff:ff:ff:ff 4: eth2: mtu 1500 qdisc noop qlen 1000 link/ether 00:00:00:00:01:02 brd ff:ff:ff:ff:ff:ff 5: eth3: mtu 1500 qdisc noop qlen 1000 link/ether 00:00:00:00:01:03 brd ff:ff:ff:ff:ff:ff 6: tunl0@NONE: mtu 1480 qdisc noop qlen 1000 link/ipip 0.0.0.0 brd 0.0.0.0 7: sit0@NONE: mtu 1480 qdisc noop qlen 1000 link/sit 0.0.0.0 brd 0.0.0.0 切ない ip link set dev eth0 up エラーを与える fsl_dpaa_mac ffe4e0000.ethernet eth0: init_phy() failed ブートログ中に、私はこれを見ることができます: mdio_bus 0x0000000ffe4fc000: MDIO device at address 2 is missing. mdio_bus 0x0000000ffe4fc000: MDIO device at address 6 is missing. mdio_bus 0x0000000ffe4fd000: MDIO device at address 1 is missing. mdio_bus 0x0000000ffe4fd000: MDIO device at address 2 is missing. platform ffe488000.port: Adding to iommu group 15 platform ffe489000.port: Adding to iommu group 16 platform ffe48a000.port: Adding to iommu group 17 platform ffe48b000.port: Adding to iommu group 18 fsl_dpaa_mac ffe4e0000.ethernet: FMan MEMAC fsl_dpaa_mac ffe4e0000.ethernet: FMan MAC address: 00:00:00:00:01:00 fsl_dpaa_mac ffe4e2000.ethernet: FMan MEMAC fsl_dpaa_mac ffe4e2000.ethernet: FMan MAC address: 00:00:00:00:01:01 fsl_dpaa_mac ffe4e4000.ethernet: FMan MEMAC fsl_dpaa_mac ffe4e4000.ethernet: FMan MAC address: 00:00:00:00:01:02 fsl_dpaa_mac ffe4e6000.ethernet: FMan MEMAC fsl_dpaa_mac ffe4e6000.ethernet: FMan MAC address: 00:00:00:00:01:03 fsl_dpaa_mac ffe4e0000.ethernet eth0: Probed interface eth0 fsl_dpaa_mac ffe4e2000.ethernet eth1: Probed interface eth1 fsl_dpaa_mac ffe4e4000.ethernet eth2: Probed interface eth2 fsl_dpaa_mac ffe4e6000.ethernet eth3: Probed interface eth3 MDIOが正しく構成されていないというのは本当ですか?私はカーネルソースからのデバイスツリーを使用していますが、Ubootは以前のイメージ(カーネルバージョン3.12.27)から保持されています。新しいrootfs、dtb、uImageをRAMにロードし、そこから実行しました。 ethtool 次を見せてください: ethtool eth0 Settings for eth0: Supported ports: [ ] Supported link modes: Not reported Supported pause frame use: No Supports auto-negotiation: No Supported FEC modes: Not reported Advertised link modes: Not reported Advertised pause frame use: No Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: Unknown! Duplex: Half Port: Twisted Pair PHYAD: 0 Transceiver: internal Auto-negotiation: off MDI-X: Unknown Current message level: 0x00002037 (8247) drv probe link ifdown ifup hw Link detected: no T1024でイーサネットを使用するための秘訣はありますか? QorIQ SDK 2.0から新しい画像をコンパイルしようとしましたが、非常に古いツールがあり、多くのエラーで停止しました。 QorIQ T1デバイス 日時:T1024 ehernetインターフェースが起動しない どうもありがとうございます。私は問題を解決しました。

Integrating lpddr4_timing.c for custom board using i.MX 8M plus Hello, I am bringing up a custom board using an i.MX 8M plus, and I am having trouble with u-boot SPL failing to boot with what I believe is a calibrated lpddr4_timing.c file. I followed the instructions to use the MSCALE DDR Tool v3.31 to successfully perform a DDR stress test. I then generated a calibrated lpddr4_timing.c. Following section 4.5.2 of MSCALE_DDR_Tool_User_Guide.pdf, I copied the generated lpddr4_timing.c file into the board/freescale/imx8mp_evk/ directory in the u-boot-imx project of my Yocto build environment.  I then forced a compilation of u-boot-imx using the command bitbake u-boot-linux -f -c compile I then built imx-image-core using the usual command bitbake imx-image-core Finally, I wrote the generated .wic.zst image to an SD card as I have done previously when adding packages and modifying the Linux device tree. However, when I boot, I see the following debug message over UART. U-Boot SPL 2024.04+g674440bc73e+p0 (Oct 24 2024 - 14:35:20 +0000) DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS Training FAILED Is there a step I am missing when integrating the lpddr4_timing.c into a build of imx-core-image? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Integrating lpddr4_timing.c for custom board using i.MX 8M plus I believe my build of u-boot was not correctly building in the lpddr4_timing.c file using just the bitbake u-boot-linux -f -c compile command. What worked for me was deleting lpddr4_timing.o from the build artifacts. I then forced another u-boot compile using bitbake u-boot-linux -f -c compile and verified that lpddr4_timing.o was regenerated. I then built imx-image-core using the usual command bitbake imx-image-core Finally, I wrote the generated .wic.zst image to an SD card as I have done previously when adding packages and modifying the Linux device tree. When I booted the device, it worked. I'll need to review how I include my board specific lpddr4_timing.c into my device layer, and how to force a full rebuild, but not a checkout of from source repositories, using bitbake commands. Re: Integrating lpddr4_timing.c for custom board using i.MX 8M plus Hello, You are following the correct steps to generate and implement the DDR scripts using Yocto, there is no additional steps to implement it. How are you flashing the image? UUU? Best regards.