PCA9617波形 この回路はPCA9600で問題なく動作しますが、コストを下げるために、PCA9617を使用するようにボードを変更し、波形を確認しました。 クロック波形を見ると、特に歪みはありませんが、 なので問題なさそうですが、データ波形がLowを出力しているポイントでは、 クロックの立ち下がりエッジでHighに引っ張られた波形を観察しました。 これはクロックとデータ間のクロストークによるものなのでしょうか(PCA9600DPZを装着していれば問題ありません)、 それとも基板のパターン修正(パターンカット/ケーブルはんだ付け)の影響ですか? ご意見を頂戴いたします。

IW612 PCM/I2S support I am developing an embedded audio application that is using the IW612 for Bluetooth communication. The IW612 has a PCM/I2S interface - is this interface only intended for use with SCO audio, or can it be used in other cases, such as for audio streaming with A2DP? Re: IW612 PCM/I2S support Dear @skordal , >> is this interface only intended for use with SCO audio? Yes, PCM/I2S is only used for SCO or eSCO. >>About A2DP UART interface is used for A2DP. Thanks! Regards, weidong

i.MX8MM ECSPI slave mode restriction I am currently using the i.MX8MM ECSPI Slave in PIO mode. The issue is that in Slave mode, the burst length appears to be limited to 512 bytes. While it's not clear whether using DMA mode instead of PIO mode would remove the transmission data size limitation, I have applied a kernel patch to try using DMA mode. Can I get sample code or materials related to SPI data transmission and reception in Slave mode(using DMA)? I am referring to the AN13633 document, but I would appreciate any comments if there are other helpful resources available. Let me know if you would like me to help you find specific resources or documentation about implementing DMA mode for ECSPI on i.MX8MM. Re: i.MX8MM ECSPI slave mode restriction Thank you for your quick response. Have a nice day. Re: i.MX8MM ECSPI slave mode restriction double checked again, this limitation is HW limitation, the AN is released and based on the old bsp, the new bsp add 512 bytes limitation because of HW limitation, so you couldn't remove this,  it seems imx8mm ecspi couldn't support this(no 512 bytes limitation) if you want to use slave mode Re: i.MX8MM ECSPI slave mode restriction Thank you for your reply. But, I didn't understand exactly what you said. Does annotating the 512 byte limit in kernel code mean I can transfer more than 512 bytes in SPI Slave mode? if ((is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) && transfer->len > MX53_MAX_TRANSFER_BYTES && spi_imx->target_mode) {     dev_err(spi_imx->dev, "Transaction too big, max size is %d bytes\n",     MX53_MAX_TRANSFER_BYTES);     return -EMSGSIZE; } Re: i.MX8MM ECSPI slave mode restriction I checked the driver again, the limitation is https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/spi/spi-imx.c#L1492 if you want to test this, you can comment the 512 limitation to test based on your detailed user case Re: i.MX8MM ECSPI slave mode restriction confirmed that DMA/PIO mode has 512 limitation, and DMA has 4 bytes align limitation, you can refer to the patch I sent to you before Re: i.MX8MM ECSPI slave mode restriction I apologize for contacting you. I have a question I'd like to ask for clarification. Could you please help me understand the meaning of the note on page 5 of the linked document? (Link) https://www.nxp.com/docs/en/application-note/AN13633.pdf " Note: From testing, it seems no such transfer length restriction must be added in DMA mode. So only PIO mode has this restriction." Re: i.MX8MM ECSPI slave mode restriction Thank you for your quick reply. Re: i.MX8MM ECSPI slave mode restriction yes, DMA has this limtitaion too Re: i.MX8MM ECSPI slave mode restriction Thank you for your response. I was trying to enable DMA mode thinking there were no transfer size restrictions in DMA mode. Based on the linked document, does it mean that both PIO and DMA modes have a 512-byte limit for transfer data size? Re: i.MX8MM ECSPI slave mode restriction AN13633 is very detailed application note for your request, for dma support, you also can refer to the patch as below, and you also can focus on the ERR003775 from errata LF-6680 spi: imx: add dma support for target mode · nxp-imx/linux-imx@1aef8ed · GitHub

change bluetooth address via vendor specific commands I am working with a module based on the 88W8997 chipset. We have a need to change the device's public BD address. Is there a vendor-specific command for doing so? What specific internal documents do I need to request access to? Product: WiFi 88W8997 Protocol: Bluetooth Re: change bluetooth address via vendor specific commands Dear @mike16 , See below, please! Thanks! Regards, weidong

i.MX93: ESDHC erratum ERR052357 U-Boot code from current BSP (lf-6.6.52_2.2.0) contains a fix for an undocumented erratum. Please give more in detail information about the issue. Is there a fix available for Linux? Re: i.MX93: ESDHC erratum ERR052357 Hi @Niebel-TQ  Is this always guaranteed even for a kernel compiled with PREEMPT_RT and / or at higher tick rates? -->The Linux OS here is NONE-RT kernel, for NONE-RT kernel, we have tested and didn't observe issue. For PREEMPT_RT Linux, there is no test data on this, but according to previous information, for Real Time OS, this delay needs to be added.  Is this issues limited to i.MX93 or is it present in other CPU / MCU -->The affected chips are i.MX91, i.MX93 and i.MX95 A1. Best Regards, Zhiming Re: i.MX93: ESDHC erratum ERR052357 Add  @florian_arndt and @danny_john Re: i.MX93: ESDHC erratum ERR052357 Thank you for explaining. Two additiponal questions:  1) `In Linux OS, since software latency is enough`: Is this always guaranteed even for a kernel compiled with PREEMPT_RT and / or at higher tick rates? 2) Is this issues limited to i.MX93 or is it present in other CPU / MCU (we us a lot of different NXP products in our company) Re: i.MX93: ESDHC erratum ERR052357 Hello, In Linux OS, since software latency is enough, this issue will not be observed, no need extra workaround. In real time OS like QNX, extra delay time should be added to avoid this issue. So in u-boot, 10μs delay is added for uSDHC read transfer since Linux 6.6.36_2.1.0. This errata will not affect application layer. Best Regards, Zhiming Re: i.MX93: ESDHC erratum ERR052357 Yes, this is the commit. 10us is a lot of time. Re: i.MX93: ESDHC erratum ERR052357 Hello, Is this commit? Best Regards, Zhiming

i.MX8MM ECSPIスレーブモードの制限 現在、i.MX8MM ECSPI SlaveをPIOモードで使用しています。 問題は、スレーブ モードでは、バースト長が 512 バイトに制限されているように見えることです。 PIOモードの代わりにDMAモードを使用すると送信データサイズの制限がなくなるかどうかは明らかではありませんが、カーネルパッチを適用してDMAモードを使用してみました。 スレーブモード(DMA使用)でSPIデータの送受信に関するサンプルコードや資料は入手できますか? 私はAN13633のドキュメントを参照していますが、他の役立つリソースがあればコメントをいただければ幸いです。 i.MX8MMでのECSPIのDMAモードの実装に関する特定のリソースやドキュメントを見つけるのを手伝ってほしい場合は、お知らせください。 Re:i.MX8MM ECSPIスレーブモードの制限 迅速な対応ありがとうございました。 よい一日を。 Re:i.MX8MM ECSPIスレーブモードの制限 もう一度確認し直して、この制限はHWの制限であり、ANがリリースされ、古いbspに基づいて、新しいbspはHWの制限のために512バイトの制限を追加するため、これを削除することはできませんでした、スレーブモードを使用したい場合は、imx8mm ecspiがこれをサポートできなかったようです（512バイトの制限はありません Re:i.MX8MM ECSPIスレーブモードの制限 ご返信ありがとうございます。 でも、君が何を言っているのかよくわからなかった。 カーネル コードで 512 バイトの制限に注釈を付けると、SPI スレーブ モードで 512 バイト以上を転送できるということですか。 if ((is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) && transfer->len > MX53_MAX_TRANSFER_BYTES & spi_imx->target_mode) { dev_err(spi_imx->dev, "トランザクションが大きすぎます。最大サイズは %d バイトです\n", MX53_MAX_TRANSFER_BYTES); -EMSGSIZEを返します。 } Re:i.MX8MM ECSPIスレーブモードの制限 ドライバーを再度確認しましたが、制限は https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/spi/spi-imx.c#L1492 これをテストしたい場合は、詳細なユーザーケースに基づいてテストする512制限をコメントできます Re:i.MX8MM ECSPIスレーブモードの制限 DMA / PIOモードには512の制限があり、DMAには4バイトのアライメント制限があることを確認しましたので、以前に送信したパッチを参照できます Re:i.MX8MM ECSPIスレーブモードの制限 ご連絡を頂きまして申し訳ございません。 明確にしたい質問があります。 リンクされたドキュメントの5ページにある注の意味を理解するのを手伝っていただけますか? (リンク) https://www.nxp.com/docs/en/application-note/AN13633.pdf 注:テストの結果、DMAモードではそのような転送長の制限を追加する必要はないようです。したがって、PIOモードにのみこの制限があります。」 Re:i.MX8MM ECSPIスレーブモードの制限 迅速な返信ありがとうございます。 Re:i.MX8MM ECSPIスレーブモードの制限 ええ、DMAにもこの制限があります Re:i.MX8MM ECSPIスレーブモードの制限 返信ありがとうございます。 DMAモードには転送サイズの制限がないと思って、DMAモードを有効にしようとしていました。 リンクされたドキュメントに基づいて、PIO モードと DMA モードの両方に転送データ サイズに 512 バイトの制限があるということですか? Re:i.MX8MM ECSPIスレーブモードの制限 AN13633、DMAサポートについては、ご要望に応じた非常に詳細なアプリケーションノートであり、以下のようにパッチを参照することもでき、また、 エラッタからのERR003775 LF-6680 spi: imx: ターゲットモードのdmaサポートを追加 ·nxp-imx/linux-imx@1aef8ed ·GitHubの

i.MX8MM ECSPI 从属模式限制 我目前正在 PIO 模式下使用 i.MX8MM ECSPI 从属设备。 问题是，在从属模式下，突发长度似乎被限制为 512 字节。 虽然不清楚使用 DMA 模式而不是 PIO 模式是否会消除传输数据大小限制，但我已经应用了内核补丁来尝试使用 DMA 模式。 我可以获得与从属模式（使用 DMA）下的 SPI 数据传输和接收相关的示例代码或资料吗？ 我指的是 AN13633 文档，但如果有其他有用的资源，我将非常感激您的评论。 如果您希望我帮助您找到有关在 i.MX8MM 上为 ECSPI 实现 DMA 模式的特定资源或文档，请告诉我。 回复：i.MX8MM ECSPI 从属模式限制 感谢您的快速回复。 祝你今天过得愉快。 回复：i.MX8MM ECSPI 从属模式限制 再次检查，这个限制是硬件限制，AN 是基于旧 bsp 发布的，由于硬件限制，新 bsp 增加了 512 字节限制，所以你不能删除这个，如果你想使用从属模式，似乎 imx8mm ecspi 无法支持这个（没有 512 字节限制） 回复：i.MX8MM ECSPI 从属模式限制 感谢你的回复。 但是，我不太明白你的意思。 在内核代码中注释 512 字节限制是否意味着我可以在 SPI 从属模式下传输超过 512 字节？ 如果（（is_imx51_ecspi（spi_imx）|| is_imx53_ecspi（spi_imx））&& 传输->长度 > MX53_MAX_TRANSFER_BYTES && spi_imx->目标模式) { dev_err（spi_imx->dev，“事务太大，最大大小为%d字节\n”， MX53_最大传输字节数）； 返回-EMSGSIZE； } 回复：i.MX8MM ECSPI 从属模式限制 我再次检查了驱动程序，限制是 https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/spi/spi-imx.c#L1492 如果你想测试这一点，你可以根据你详细的用户案例，评论 512 限制进行测试 回复：i.MX8MM ECSPI 从属模式限制 确认DMA/PIO模式有512个限制，DMA有4个字节对齐限制，你可以参考我之前发给你的补丁 回复：i.MX8MM ECSPI 从属模式限制 很抱歉联系您。 我有一个问题想请求澄清。 您能帮我理解链接文档第 5 页注释的含义吗？ （关联） https://www.nxp.com/docs/en/application-note/AN13633.pdf “注意：从测试来看，在 DMA 模式下似乎不需要添加这样的传输长度限制。所以只有PIO模式才有这个限制。” 回复：i.MX8MM ECSPI 从属模式限制 感谢您的快速回复。 回复：i.MX8MM ECSPI 从属模式限制 是的，DMA 也有这个限制 回复：i.MX8MM ECSPI 从属模式限制 谢谢您的回复。 我试图启用 DMA 模式，认为 DMA 模式下没有传输大小限制。 根据链接的文档，这是否意味着 PIO 和 DMA 模式对传输数据大小都有 512 字节的限制？ 回复：i.MX8MM ECSPI 从属模式限制 AN13633 是一份非常详细的应用说明，适用于您的请求，对于 DMA 支持，您还可以参考下面的补丁，还可以关注勘误表中的 ERR003775 LF-6680 spi: imx: 添加目标模式的 dma 支持 · nxp-imx/linux-imx@1aef8ed · GitHub

IMX8ulp flexCAN Hi all，     I am debugging the CAN communication function, but I cannot find the flexCAN device node in the dtb file. If I want to get it working, what's the solution? Best regards! i.MX8ULP Re: IMX8ulp flexCAN Yes, I see.Thanks a lot! Re: IMX8ulp flexCAN I just got the confirmation from the SE team. FlexCAN is in realtime domain so it is not supported in Linux. It can only be accessed by M core. You can find driver and related examples in SDK. Re: IMX8ulp flexCAN yeah, I know I can refer to other dts, but how do I reference the clock and interrupts? These are strongly related to hardware. Re: IMX8ulp flexCAN Please refer to the following definition in arch/arm64/boot/dts/freescale/imx8mp.dtsi in Linux Kernel. flexcan1: can@308c0000 { compatible = "fsl,imx8mp-flexcan"; reg = <0x308c0000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_IPG_ROOT>, <&clk IMX8MP_CLK_CAN1_ROOT>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX8MP_CLK_CAN1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; flexcan2: can@308d0000 { compatible = "fsl,imx8mp-flexcan"; reg = <0x308d0000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_IPG_ROOT>, <&clk IMX8MP_CLK_CAN2_ROOT>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX8MP_CLK_CAN2>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; fsl,stop-mode = <&gpr 0x10 5>; status = "disabled"; }; }; And the following definition in arch/arm64/boot/dts/freescale/imx8mp-evk.dts. &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <&reg_can1_stby>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <&reg_can2_stby>; pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; status = "disabled";/* can2 pin conflict with pdm */ };

拡張機能の更新が失敗しました 「Getting Started with MR-CANHUBK344 Evaluation Board」というドキュメントによると、「S32K3 RTD AUTOSAR® 4.4 Version 2.0.0」と「S32K3xx development package Version 3.4.3」についてインストールしてみました。しかし、アップロードのスクリーンショットのように失敗しました。  また、拡張リストに「FreeRTOS for S32K3 2.0.0」が見つかりません。正しくインストールするにはどうすればよいですか? Re:拡張機能の更新が失敗しました https://community.nxp.com/t5/S32K/S32K3-Unified-Bootloader-Build-Issue/td-p/1653130 に記載されているオフラインインストールとオンラインインストールの方法を参照してください S32K3 リファレンスソフトウェア -> Automotive SW - S32K3 - FreeRTOS -> SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 Re:拡張機能の更新が失敗しました 理由の詳細: 操作の詳細あなたの元の要求は変更されました。「ARM PEMicro Interface Debugging Support」は既にインストール済みですので、代わりにアップデートを行います。インストールされているソフトウェア:com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337フィルタープロパティの要件がありません ~= $0: com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337 requires 'org.eclipse.equinox.p2.iu;com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.jar [1.0.0.202109281337,1.0.0.202109281337]' が見つかりませんでした Re:拡張機能の更新が失敗しました また、拡張リストに「FreeRTOS for S32K3 2.0.0」が見つかりません。どうすれば正しくインストールできますか?」が解決されます。 Re: Extension update failled バージョン2.0.0はもう存在しません。2.0.1しか見つからないのですが、これは動作しません。 SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 を指し示していただけますか？

Extension update failled  According to the document which named "Getting Started with MR-CANHUBK344 Evaluation Board", I tried to install about "S32K3 RTD AUTOSAR® 4.4 Version 2.0.0" and "S32K3xx development package Version 3.4.3". But it failed like an upload screenshot.  Also I can't find "FreeRTOS for S32K3 2.0.0" at the extension list. How can install correctly? Re: Extension update failled Please refer to the offline installation and online installation methods mentioned in https://community.nxp.com/t5/S32K/S32K3-Unified-Bootloader-Build-Issue/td-p/1653130 S32K3 Reference Software -> Automotive SW - S32K3 - FreeRTOS -> SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 Re: Extension update failled Reason Details: Operation detailsYour original request has been modified."GNU ARM PEMicro Interface Debugging Support" is already installed, so an update will be performed instead.Software being installed: com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337 Missing requirement for filter properties ~= $0: com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337 requires 'org.eclipse.equinox.p2.iu; com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.jar [1.0.0.202109281337,1.0.0.202109281337]' but it could not be found Re: Extension update failled " Also I can't find "FreeRTOS for S32K3 2.0.0" at the extension list. How can install correctly?" is solved. Re: Extension update failled 2.0.0 is no longer there. I only find 2.0.1 which doesn't work. Can you point to SW32K3_FreeRTOS_10.4.6_2.0.0_D2204?

IW612 PCM/I2S 支持 我正在开发一个嵌入式音频应用程序，使用IW612进行蓝牙通信。IW612 有一个 PCM/I2S 接口 - 该接口仅适用于 SCO 音频，还是可以用于其他情况，例如用于 A2DP 音频流？

通过供应商特定命令更改蓝牙地址 我正在使用基于 88W8997 芯片组的模块。我们需要更改设备的公共 BD 地址。是否有针对供应商的特定命令可以执行此操作？我需要请求访问哪些具体的内部文件？ 产品：WiFi 88W8997 协议：蓝牙

RT1024 second bootloader double bank Hi, Our final goal: - Be able to write an image from the RAM into a bank of the flash (with a dual bank system) - After restarting the uP, check the integrity of the image and then boot on this new bank After reading different documentation we found the document MCUOTASBLSFWUG and reconfigured the RT1020 example to be compatible with the RT1024. When we load the bootloader generated, in flash, using the software 'LINKFLASH', we can connect via ISP using the software 'MCU-BOOT-Utility'. First problem if we restart the uP we can no longer connect. The configuration of the boot pins is '10' internal boot, for the others BOOT_CFGX they are all zero. Second problem, we try to load our image at the configured address (0x60200000) and the image does not boot. We set this Defined symbols : XIP_BOOT_HEADER_ENABLE to 0 Our questions are: - Is the SBL project the most relevant to use to develop our second bootloader? - After programming our bootloader, is the pin configuration correct? - Is there a special configuration at the project level on MCUExpresso to make the image bootable with the second bootloader? Re: RT1024 second bootloader double bank Finally I tested with a hello world image and it works, so we have a problem, but it does not come from the bootloader, nor from the image configuration, but from the code itself. Thank you very much for your help! Re: RT1024 second bootloader double bank Thank you for your answer. Following your advice we switched to MCUBoot. As we also have an RT1064 uP in our application, we took the example from the SDK for this uP. The bootloader compiles well, we can load it in flash, but our application does not work, we have a hardfault. We have tried different configurations, which all lead to the same result. We do not want, for the moment, to go through the imgtool tool to create a header, this is not very practical, because we are in the development phase, so first, we added a partition MCUBoot_header to the address 0x70040000 of our flash and added the necessary structure. We put our application at the address 0x70040400. We removed the key verification. And we have enabled the SINGLE_IMAGE parameter After loading our program in flash, we restart the bootloader in debug mode. The bootloader does the header check and it is valid. When arriving at the jump there is the following code : vt = (struct arm_vector_table *)(flash_base + rsp->br_image_off + rsp->br_hdr->ih_hdr_size); cleanup(); __set_CONTROL(0); __set_MSP(vt->msp); __ISB(); ((void (*)(void))vt->reset)(); at this time vt = 0x0x7004000, which seems correct. And vt.msp = 0x20020000 and vt.reset = 0x7004071D. The address of the ResetISR does not match that of the .map which is = 0x7004071C. We tried to hardcode the address, but the result is the same. Do you have any advice? Re: RT1024 second bootloader double bank Hi @Gaetan  Thank you for contacting us and for your interest!  I just want to understand this phrase better: When we load the bootloader generated, in flash, using the software 'LINKFLASH', we can connect via ISP using the software 'MCU-BOOT-Utility'. First problem if we restart the uP we can no longer connect. After programming the ported SBL, do you see this bootloader executing ? After testing by loading a blinky with the LINKFLASH on RT1024, I had to make a reset to see the blinky running. The SBL prints to UART, when it is running. Have you ever seen any bootloader messages?  Regarding - Is the SBL project the most relevant to use to develop our second bootloader? The SBL is not under active development since 2021, still is is a good reference thanks to the security features and OTA capabilities that it provides. If we check the readme, on the github, you will find that development team recommends the MCU boot opensource project. However, the this project is also not ported for the  RT1024, but it is for the RT1020, as I mentioned on this thread I am not recommending you to jump directly to the MCU boot open source, feel free to pick the option that works better for you. Instead I mention this, in case you want  to consider other option, simply because the MCU boot open source is on active development. Regarding - After programming our bootloader, is the pin configuration correct? The SBL needs to boot on internal bootloader mode, so I think  the boot mode settings are correct. Regarding - Is there a special configuration at the project level on MCUExpresso to make the image bootable with the second bootloader? I can not tell, because I do not know all the steps you followed from the SBL user guide. If you follow all the steps, I do not see a missing step to boot the target SFW image.  Please correct me, if I am wrong, but I have not seen the SBL for the MCUXpresso IDE tool chain. Which IDE are you using? is ARM GCC instead? I hope I could help you Diego

IW612 PCM/I2S 対応 Bluetooth通信に IW612 を使用する組み込みオーディオアプリケーションを開発しています。IW612 には PCM/I2S インターフェースがありますが、このインターフェースは SCO オーディオでの使用のみを目的としていますか、それとも A2DP によるオーディオストリーミングなど、他の場合にも使用できますか?

扩展程序更新失败 根据名为“MR-CANHUBK344评估板入门”的文档，我尝试安装“S32K3 RTD AUTOSAR ® 4.4 版本 2.0.0”和“S32K3xx开发包版本 3.4.3”。但是像上传截图一样失败了。 另外，我在扩展列表中找不到“FreeRTOS for S32K3 2.0.0”。怎样才能正确安装？ 回复：扩展更新失败 请参考https://community.nxp.com/t5/S32K/S32K3-Unified-Bootloader-Build-Issue/td-p/1653130中提到的离线安装和在线安装方法 S32K3参考软件->汽车软件-S32K3-FreeRTOS->SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 回复：扩展更新失败 原因详情：操作详情您的原始请求已被修改。“GNUARM PEMicro 接口调试支持”已安装，因此将执行更新。正在安装的软件：com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337缺少过滤器属性的要求 ~= $0: com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.group 1.0.0.202109281337 需要‘org.eclipse.equinox.p2.iu; com.nxp.s32ds.brc.arm.tools.gcc102.feature.feature.jar [1.0.0.202109281337,1.0.0.202109281337]’但找不到 回复：扩展更新失败 “另外，我在扩展列表中找不到“FreeRTOS for S32K3 2.0.0”。如何正确安装？”已解决。 Re: Extension update failled 2.0.0 已不复存在。我只找到了 2.0.1 版，但无法使用。 您能指出 SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 吗？

LPCXpresso54628 Development Board SDRAM addressing I am using the documentation for the LPCXpress54628 development board as a guide to replicate the interface with the SDRAM IC IS42S16800F-6BLI in my own design.  I noticed on the diagram that there is a P1_24-EMC_A12 identified connected to pin G1.  However, the datasheet for that device shows pin G1 as NC.  I will assume it really isn't a functioning connection.  The 12 address lines A0-A11 do provide the 4K of addressing for the memory.  Was there a part change?  The other part number (W9812G6JB) also shows NC on G1. Thanks Sam LPC546xx Re: LPCXpresso54628 Development Board SDRAM addressing Hi @samv  Yes, The W9812G6JB and IS42S16800F-6BLI both have only 12 bit address lines. They are 128Mb SDRAM. You can also check the LPC54628 RM. BR Harry

ベンダー固有のコマンドによるBluetoothアドレスの変更 88W8997チップセットに基づくモジュールで作業しています。デバイスの公開BDアドレスを変更する必要があります。そのためのベンダー固有のコマンドはありますか?どのような内部ドキュメントへのアクセスをリクエストする必要がありますか? 製品: Wi-Fi 88W8997 プロトコル：Bluetooth

i.MX8 booting from QSPIFlash Hi we've a imx8mn based board with different DDR chip and different NOR flash connected to QSPI interface. (different from imx8mn-evk board) As well we have two boot options: eMMC and QSPI. The board boots and works while booting from eMMC, the QSPI flash is available in u-boot and Linux. But, when we're trying to switch to QSPI boot option - boot fails - no output on the console. On the other hand, we can see the clocks on SPI bus and - it means the CPU indeed tries to boot from QSPI. We're building our QSPI flash image with a help of imx-mkimage utility, there is a guide of how to create it: https://community.nxp.com/t5/i-MX-Processors/IMX8Mnano-EVK-How-to-make-QSPI-booting-image/td-p/1704730 In addition, here is the out of: make SOC=iMX8MN DEV=flexspi flash_evk BL32=tee.bin DEK_BLOB_LOAD_ADDR=0x40400000 TEE_LOAD_ADDR=0x56000000 ATF_LOAD_ADDR=0x00960000 ../iMX8M/mkimage_fit_atf.sh evk.dtb  > u-boot.its bl31.bin size:  41456 u-boot-nodtb.bin size:  736416 evk.dtb size:  28304 ./mkimage_uboot -E -p 0x5000 -f u-boot.its u-boot.itb FIT description: Configuration to load ATF before U-Boot Created:         Tue Oct  8 17:44:52 2024  Image 0 (uboot-1)   Description:  U-Boot (64-bit)   Created:      Tue Oct  8 17:44:52 2024   Type:         Standalone Program   Compression:  uncompressed   Data Size:    736416 Bytes = 719.16 KiB = 0.70 MiB   Architecture: AArch64   Load Address: 0x40200000   Entry Point:  unavailable  Image 1 (fdt-1)   Description:  evk   Created:      Tue Oct  8 17:44:52 2024   Type:         Flat Device Tree   Compression:  uncompressed   Data Size:    28304 Bytes = 27.64 KiB = 0.03 MiB   Architecture: Unknown Architecture  Image 2 (atf-1)   Description:  ARM Trusted Firmware   Created:      Tue Oct  8 17:44:52 2024   Type:         Firmware   Compression:  uncompressed   Data Size:    41456 Bytes = 40.48 KiB = 0.04 MiB   Architecture: AArch64   OS:           Unknown OS   Load Address: 0x00960000  Default Configuration: 'config-1'  Configuration 0 (config-1)   Description:  evk   Kernel:       unavailable   Firmware:     uboot-1   FDT:          fdt-1   Loadables:    atf-1 41420+1 records in 41421+0 records out 165684 bytes (166 kB, 162 KiB) copied, 0.0578868 s, 2.9 MB/s ./mkimage_imx8 -version v2 -fit -loader u-boot-spl-ddr.bin 0x912000 -second_loader u-boot.itb 0x40200000 0x60000 -out flash.bin Platform: i.MX8M (mScale) ROM VERSION: v2 Using FIT image LOADER IMAGE: u-boot-spl-ddr.bin start addr: 0x00912000 SECOND LOADER IMAGE: u-boot.itb start addr: 0x40200000 offset: 0x00060000 Output: flash.bin fit_size: 886 1+0 records in 1+0 records out 886 bytes copied, 5.7108e-05 s, 15.5 MB/s FIT hash: 9dc0d453c9a49e3d880292c4c330e685ea495c6856ab82ab61354b134f9b ========= IVT HEADER [HDMI FW] ========= header.tag: 0x0 header.length: 0x0 header.version: 0x0 entry: 0x0 reserved1: 0x0 dcd_ptr: 0x0 boot_data_ptr: 0x0 self: 0x0 csf: 0x0 reserved2: 0x0 boot_data.start: 0x0 boot_data.size: 0x0 boot_data.plugin: 0x0 ========= IVT HEADER [PLUGIN] ========= header.tag: 0x0 header.length: 0x0 header.version: 0x0 entry: 0x0 reserved1: 0x0 dcd_ptr: 0x0 boot_data_ptr: 0x0 self: 0x0 csf: 0x0 reserved2: 0x0 boot_data.start: 0x0 boot_data.size: 0x0 boot_data.plugin: 0x0 ========= IVT HEADER [LOADER IMAGE] ========= header.tag: 0xd1 header.length: 0x2000 header.version: 0x41 entry: 0x912000 reserved1: 0x0 dcd_ptr: 0x0 boot_data_ptr: 0x911fe0 self: 0x911fc0 csf: 0x9527c0 reserved2: 0x0 boot_data.start: 0x911fc0 boot_data.size: 0x42860 boot_data.plugin: 0x0 ========= OFFSET dump ========= Loader IMAGE:  header_image_off 0x0  dcd_off 0x0  image_off 0x40  csf_off 0x40800  spl hab block: 0x911fc0 0x0 0x40800   Second Loader IMAGE:  sld_header_off 0x58000  sld_csf_off 0x59020  sld hab block: 0x401fadc0 0x58000 0x1020  fit-fdt csf_off 0x5b020  fit-fdt hab block: 0x401fadc0 0x58000 0x3020 SPL CSF block: Blocks = 0x911fc0 0x0 0x40800 "flash.bin" SLD CSF block: Blocks = 0x401fadc0 0x58000 0x1020 "flash.bin",\ SLD FIT-FDT CSF block: Blocks = 0x401fadc0 0x58000 0x3020 "flash.bin"     bootmode selected: FlexSPI - 3B Read '0110' We can see on power up clock signal of the QSPI bus. But we can't see the processor running. Nothing over the console.  What is probably incorrect in our FLASH image preparation? To which offset on QSPI FLASH the image should be burn? Do we need to config something on u-boot? SPL? if so, what to config? The flash P/N we are using is: S25FL256SAGBHVB00 Thank you so much for your help, i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: i.MX8 booting from QSPIFlash Hi @efio  Glad to here that. You are welcome. And for the further question, Could you please create another ticket talk about it? B.R Re: i.MX8 booting from QSPIFlash Hi, I am pleased to inform you that the issue has been fully resolved. The root cause was identified as an incorrect mkimage file configuration. Thank you for your valuable assistance throughout this process. Best regards, Re: i.MX8 booting from QSPIFlash Thank you for your previous assistance. I would like to provide a status update regarding the flash issue. I've made progress by modifying the mkimage command to: make SOC=iMX8MN DEV=flexspi flash_evk_flexspi This resolved the initial problem as this command properly includes the QSPI header with the 0xFCFB word at address 0x400. However, I'm now encountering a new issue when attempting to access the flash from U-Boot. Specifically, the "sf probe" command fails with the following error: u-boot=> sf probe Invalid bus 0 (err=-19) Failed to initialize SPI flash at 0:0 (error -19) Notably, when booting from eMMC and stopping at U-Boot, the "sf probe" command works correctly. This suggests that the controller might be holding the bus, preventing access to the flash. Could you please provide guidance on how to properly configure or release the bus controller in this scenario? Thank you for your continued support.   Best regards Re: i.MX8 booting from QSPIFlash HI @efio  Please use the following command compile your flash.bin file. make SOC=iMX8MN flash_evk_flexspi B.R Re: i.MX8 booting from QSPIFlash Hi, Unfortunately, the link doesn't help - I want to boot the imx8mn from the QSPI flash - meaning u-boot should come-up from the QSPI flash. Any other suggestions?  Thank you very much, Re: i.MX8 booting from QSPIFlash HI @efio  I found the same issue with you, You can refer it follow the below link. hope it can help you. https://community.nxp.com/t5/i-MX-Processors/i-MX8MM-QSPI-booting-and-partition/m-p/1661476 B.R Re: i.MX8 booting from QSPIFlash Same, doesn't work Re: i.MX8 booting from QSPIFlash hi @efio  What is your result when you use the UUU command flash your .bin file? B.R Re: i.MX8 booting from QSPIFlash Hi, It's only one flash, the symbol package is divided to two for convenience. I flashed the data using external J-Link and using dd command of linux. both gave some results. Hexdump gives the correct data. I don't think the data is the issue, something is wrong what the IVT header the QSPI controller reads. ========= IVT HEADER [LOADER IMAGE] ========= header.tag:             0xd1 header.length:          0x2000 header.version:         0x41 Thank you, Re: i.MX8 booting from QSPIFlash hi @efio  I have some confuse about your schematic, you connect on flash, why your schematic have two flash chips?  My understand is you only connect S25FL256SAGBHVB00 , right? And what is your command to flash your .bin file to your flash? B.R Re: i.MX8 booting from QSPIFlash Flash data sheet: S25FL256SAGBHVB00  Re: i.MX8 booting from QSPIFlash Hi, Yes of course, you can see below the schematics for both QSPI Flash and imx8mn. Please note that I can see the signals over scope and I can communicate with the flash in uboot & linux (read, write and more). The issue occurs only when trying to boot from the QSPI flash. The mux in the schematics meant for external flash burning - which also works. As I wrote before about observations of the QSPI controller: Using an oscilloscope, I monitored the SPI wave and noticed the QSPI controller reading address 0x400 with command 0x3. The read register value is 0xd1002041, which I believe should be correct. The controller attempts this read twice. A third read attempt is made using command 0x13 (4-byte address read), resulting in the same value: 0xd1002041. After these three cycles, the operation halts. Any suggestions? Thank you, QSPI Flash sideQSPI Flash side imx8mn sideimx8mn side Re: i.MX8 booting from QSPIFlash HI @efio  Could you please share your board schematic file and your nor flash datasheet file? B.R Re: i.MX8 booting from QSPIFlash Hi, Customized board, Re: i.MX8 booting from QSPIFlash Hi,   Observations of QSPI controller: Using an oscilloscope, I monitored the SPI wave and noticed the QSPI controller reading address 0x400 with command 0x3. The read register value is 0xd1002041, which I believe should be correct. The controller attempts this read twice. A third read attempt is made using command 0x13 (4-byte address read), resulting in the same value: 0xd1002041. After these three cycles, the operation halts. Questions: Is this behavior normal for a QSPI controller? Could the read value (0xd1002041) be incorrect despite appearing valid? Why might the controller stop after three read attempts? Is there a potential issue with the controller or the connected device? Any insights or suggestions for further troubleshooting would be greatly appreciated. Thank you, Re: i.MX8 booting from QSPIFlash hi @efio  you are use our NXP i.MX8MN evk board or customer's board? Re: i.MX8 booting from QSPIFlash Does the entry: 0x912000 correct for imx8mn? Re: i.MX8 booting from QSPIFlash Hi, Using uuu didn't work. I see that the flash is burned using sf read. Is there any offset I should burn the bin file or it supposed to be in address 0x0? Thank you Re: i.MX8 booting from QSPIFlash hi @efio  I have test this on  my i.mx8mn evk board. And no issue found. Please share your uuu command result. "uuu -b qspi <.bin file>" B.R Re: i.MX8 booting from QSPIFlash Hi, Yes I did, Re: i.MX8 booting from QSPIFlash HI @efio  Did you choose the right boot selection? Please refer the following Boot selection for i.mx8MN. B.R Re: i.MX8 booting from QSPIFlash Anyone?

NHS3100 具有能量收集功能吗？ 您好，先生， 如标题，NHS3100支持能量收集吗？ 我们想用它来测量温度。 NHS3100 回复：NHS3100 具有能量收集功能吗？ 你好@KevenChen 希望你一切都好。 NHS3100支持通过 NFC 场进行被动供电；该设备可以接受来自内置 NFC/RFID 整流器的电力。欲了解更多信息，请参阅NHS31xx 用户手册，第 5.4 节系统电源架构。 问候， 爱德华多。

emios trigger Hi I am trying to test the system so that the BCTU is triggered via PWM  at every flag generation. I would like to plot the flag that triggers the BCTU on an oscilloscope. How do I do that? I am trying to get the generating emios_pwm flag outputted on an oscilloscope, by using the EMIOS_PWM_IP_INTERRUPT_REQUEST callback function, but i am not sure the interrupt for EMIOS is working. I have attached the project below RTD 4.00 S32K344 T172 Re: emios trigger Hi@Ayaz This is a demo i made before and the RTD version is 2.0.3, maybe you can refer to it.