Multi Source Translation Content

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Multi Source Translation Content

Discussions

Sort by:
关于 AFM907N PA 如果有的话,能否分享一下针对 915MHz 频率范围的调谐布局? Re: Regarding AFM907N PA 你好 lavanyaemsec 再会! 很遗憾地通知您,我们没有 915 MHz 的参考布局图;最接近的应该是…… AFM907N 760-870 MHz 参考电路设计文件 可以在AFM907N官方页面的设计资源部分找到。 对于可能由此导致的不便,我们深感抱歉。 祝你今天过得愉快,一切顺利。
View full article
S32DS v3.5 许可证已过期,授权仍然有效,没有“延长”按钮,且不允许退货。 Hello NXP support, My NXP account holds valid entitlement for S32DS v3.5, but the generated license expired. Fulfillment ID: 113445398 IDE: S32 Design Studio for S32 Platform v3.5 License Expiry: Aug 8, 2026 Entitlement Expiry: Sep 16, 2030 Machine ID: A5883F5CCBF60C6BECC55C5A0CC9D1C68DA192AD Current situation: 1. The license management page has no EXTEND button. 2. Return license is disabled, cannot release this fulfillment. 3. The entitlement is still valid until Sep 16, 2030. Could you help refresh this fulfillment license to entitlement expiry date Sep 16,2030? I have attached the screenshot of license list for your reference. Thanks. LicenseNotAllow.png Re: S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed 非常感谢您的帮助。我已经成功重新激活了S32DS。 Re: S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed 你好, 我已经退回了旧的许可证,您应该可以使用之前的激活码再次激活S32DS。
View full article
Request for TED-Kit 2 (OM6716) GUI Software Download Instructions Dear NXP Support Team, i am jwHyun, Could you please provide instructions on how to download the GUI software package, so that we can pass this along to our customer? We would appreciate your guidance on the registration/download process at your earliest convenience. Thank you in advance for your support. Re: Request for TED-Kit 2 (OM6716) GUI Software Download Instructions Replied you in another case. Thanks.
View full article
MCXN947 HPDAC backport I am backporting the Zephyr nxp_hpdac driver to Zephyr 4.3 for an MCXN947-based board. The upstream driver does not use a device init callback. However, on Zephyr 4.3 the HPDAC does not work correctly unless I explicitly initialize the DAC2 clock, SPC analog modules and reset before using the peripheral. I added an nxp_hpdac_init() function which performs the following steps: CLOCK_SetClkDiv(kCLOCK_DivDac2Clk, 1U) CLOCK_AttachClk(kFRO_HF_to_DAC2) CLOCK_EnableClock(kCLOCK_Dac2) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac2) SPC_EnableLowPowerModeAnalogModules(SPC0, kSPC_controlDac2) RESET_PeripheralReset(kDAC2_RST_SHIFT_RSTn) DAC14_DoSoftwareReset() DAC14_DoFIFOReset() SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref) These initialization steps were based on the MCXN947 reference manual and implemented using the corresponding MCUX SDK APIs. The init function is registered as the device init callback through DEVICE_DT_INST_DEFINE(). With these changes, the HPDAC works correctly. I also checked the Zephyr MCUX SYSCON clock-control driver and the mcux_lpc_syscon_clock.h bindings, but I could not find an HPDAC/DAC2 clock identifier or clock-control implementation for this peripheral, so I am currently using the MCUX SDK clock, SPC and reset APIs directly. My questions are: 1. Is this the correct approach when backporting the MCXN947 HPDAC driver? 2. In newer Zephyr versions, are these resources initialized somewhere else, or does the upstream nxp_hpdac driver assume that they have already been configured? 3. Is the HPDAC device init callback the correct place for this MCXN947-specific initialization, or should these steps be handled elsewhere in Zephyr? I have attached the complete backported driver for reference. Analog(ADC|CMP|DAC|OpAmps) Clock|Timers MCXN 回复: MCXN947 HPDAC backport Hi  @wesOS  1. Is this the correct approach when backporting the MCXN947 HPDAC driver? Yes, this is a reasonable and practical approach for the backport. If the required DAC2 clock, SPC analog modules, VREF, and reset resources are not initialized elsewhere in the Zephyr 4.3 environment, performing the initialization in the driver is necessary to ensure correct HPDAC operation. 2. In newer Zephyr versions, are these resources initialized somewhere else, or does the upstream nxp_hpdac driver assume that they have already been configured? HPDAC support has already been added upstream: https://github.com/zephyrproject-rtos/zephyr/pull/104642 However, I performed a quick verification using the current upstream implementation and observed that the DAC2 clock does not appear to be configured. For example, CLOCK_GetDacClkFreq(2) reports 0 Hz in my test environment, while the equivalent MCUX SDK example reports 48 MHz after the DAC clock is configured. Based on this observation, it appears that the current driver may be assuming that certain device resources have already been configured. Could you please double-check the clock configuration path on your side as well? I will also report this to our Zephyr team for further investigation and work with them to address the issue if a missing clock initialization bug is confirmed. 3. Is the HPDAC device init callback the correct place for this MCXN947-specific initialization, or should these steps be handled elsewhere in Zephyr? For a backport, placing this logic in the HPDAC device initialization callback is a practical and acceptable solution. That said, the MCXN947-specific DAC2 clock, SPC, VREF, and reset configuration should ideally be clearly isolated as SoC-specific functionality rather than embedded as generic HPDAC behavior. In the longer term, these resources would preferably be managed through Zephyr infrastructure such as clock, reset, or power-management frameworks where applicable. BR Harry 回复: MCXN947 HPDAC backport Thanks, I double-checked the DAC2 clock path on my MCXN947 setup. Before the HPDAC driver configures the clock: dac_nxp_hpdac: DAC2 clock before config: 0 Hz After: CLOCK_SetClkDiv(kCLOCK_DivDac2Clk, 1U); CLOCK_AttachClk(kFRO_HF_to_DAC2); CLOCK_EnableClock(kCLOCK_Dac2); I get: dac_nxp_hpdac: DAC2 clock after config: 48000000 Hz So I am seeing the same behavior on my side: the DAC2 clock is not configured before the HPDAC driver initialization. Your explanation about keeping the MCXN947-specific resource handling isolated also makes sense. What I am mainly trying to understand now is how you expect that initialization to be divided in the eventual upstream solution. For example, do you expect the DAC2 clock configuration, SPC/VREF setup and reset handling to each move into their corresponding Zephyr/SoC infrastructure, with `dac_nxp_hpdac.c` only keeping the generic HPDAC initialization? I am mainly asking so I can understand the intended ownership of each initialization step and keep the backport reasonably aligned with that direction. Thank you. BR  Ouassim 回复: MCXN947 HPDAC backport Hi @wesOS  Thanks for confirming your results. The fact that both of us observe DAC2 clock before config: 0 Hz and 48000000 Hz after the clock configuration strongly suggests that the DAC2 clock is not initialized before the HPDAC driver runs. I have already reported the bug fix to our internal Zephyr team. After looking further into the FRDM-MCXN947 implementation, I found that the existing DAC clock initialization is currently handled at the board level rather than in the DAC drivers themselves. zephyr/boards/nxp/frdm_mcxn947/board.c the function: void board_early_init_hook(void) performs the clock and SPC initialization for both DAC0 and DAC1: #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0)) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0); CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u); CLOCK_AttachClk(kFRO_HF_to_DAC0); CLOCK_EnableClock(kCLOCK_Dac0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac1)) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac1); CLOCK_SetClkDiv(kCLOCK_DivDac1Clk, 1u); CLOCK_AttachClk(kFRO_HF_to_DAC1); CLOCK_EnableClock(kCLOCK_Dac1); #endif Based on the current implementation, my expectation would be to keep the solution consistent with the existing board design. In other words, the DAC2 clock initialization could be added to board_early_init_hook() alongside the existing DAC0/DAC1 initialization rather than placing board-specific clock setup into the generic HPDAC driver. BR Harry
View full article
KW47B42ZB7 熔丝写入问题 Lu888_0-1788925610415.pngLu888_0-1788925610415.pngLu888_0-1788925610415.png 如图所示,我无法写入熔丝 0xa,但已成功写入熔丝 0x1f。我不知道为什么 Re: KW47B42ZB7 Fuse write issue 嗨@Christine_Li , 这是否意味着不能使用 blhost 的 熔丝-program 命令来对 kw47 的生命周期进行编程? Re: KW47B42ZB7 Fuse write issue 你好, @Lu888 感谢您向我们提交案件。 根据你提供的信息,我认为你可以执行 fuse-read 命令,这意味着你不在“OEM 打开后”状态下。 但根据: KW47SRM.pdf 原因如下: 下表中的 RO 表示用户不能使用 MGMT_FUSE_PROGRAM 来写入生命周期熔丝,而是可以使用 MGMT_ADVANCE_LIFECYCLE 或 MGMT_SET_RETURN_FA_MODE。 Christine_Li_0-1788944686191.pngChristine_Li_0-1788944686191.pngChristine_Li_0-1788944686191.png 如果要更改生命周期,可以使用以下命令: SB3 文件中的 MGMT_ADVANCE_LIFECYCLE。 Christine_Li_1-1788944712390.pngChristine_Li_1-1788944712390.pngChristine_Li_1-1788944712390.png 顺祝商祺! Christine。 Re: KW47B42ZB7 Fuse write issue 你好, @Lu888 请问您能否帮忙查看一下您主板目前的生命周期? 您可以在已经执行过先前命令的板上使用以下命令: Christine_Li_0-1789109774271.pngChristine_Li_0-1789109774271.png blhost -p com4 熔丝-read 0xa 4 我想知道你的主板是否已经更换为 OEM-Closed 版本。 因为我发现根据这篇AN: KW47 生命周期管理 你使用的命令是正确的,可以用来改变生命周期。这与我之前的评论相矛盾。 顺祝商祺! Christine。 Re: KW47B42ZB7 Fuse write issue 你好, @Lu888 你有没有机会看我之前的评论? 关于这个案子,我还能为您做些什么吗? 如果您在这个帖子里还有任何我可以帮忙的地方,请随时告诉我。 顺祝商祺! Christine。
View full article
KW47B42ZB7 Fuse write issue Lu888_0-1788925610415.pngLu888_0-1788925610415.pngLu888_0-1788925610415.png As shown, I cannot write to fuse 0xa, but I have successfully written to fuse 0x1f. I don't know why Re: KW47B42ZB7 Fuse write issue Hi @Christine_Li , Does it mean that the fuse-program command of blhost cannot be used to program the lifecycle in kw47? Re: KW47B42ZB7 Fuse write issue Hi, @Lu888  Thanks for creating case to us. From your provided info, I think you can execute fuse-read command means you are not in "After OEM Open" state. But according to: KW47SRM.pdf The reason is: The RO in the following table indicates that user cannot use MGMT_FUSE_PROGRAM to write the lifecycle fuses, instead, he can use MGMT_ADVANCE_LIFECYCLE or MGMT_SET_RETURN_FA_MODE. Christine_Li_0-1788944686191.pngChristine_Li_0-1788944686191.pngChristine_Li_0-1788944686191.png If you want to change lifecycle, you can use this command: MGMT_ADVANCE_LIFECYCLE in SB3 file. Christine_Li_1-1788944712390.pngChristine_Li_1-1788944712390.pngChristine_Li_1-1788944712390.png Best regards, Christine. Re: KW47B42ZB7 Fuse write issue Hi, @Lu888  Can you please help to check what is your board's lifecycle currently? You can use below command on your board which already been executed previous commands: Christine_Li_0-1789109774271.pngChristine_Li_0-1789109774271.png blhost -p com4 fuse-read 0xa 4 I want to know whether your board already been changed into OEM-Closed. Because I found  that according to this AN: KW47 Managing Lifecycles you are using correct commands to change lifecycle. Which is conflict with my previous comment. Best regards, Christine. Re: KW47B42ZB7 Fuse write issue Hi, @Lu888  Did you get any chance to read my previous comment? Anything else I can do for you on this case? Please do not hesitate to let me know if still have any thing I can do for you on this thread. Best regards, Christine.
View full article
refence configuration path In Simulink, when configuring the hardware, I am trying to change the directory for the reference configuration to a relative path. Simulink -> HW-Settings -> Hardware Implementation -> Target hardware resources -> Referenced Configuration Reference Configuration Path = '.\generated\referenced_config' Unfortunately, it is not possible to enter a relative path here. Nor have I so far been able to set the path via a MATLAB script. Although the script appears to set the path in CoderTargetData, it is not actually applied. Either the old path remains active, or an empty path is applied. Is there a way to set a relative path for the reference configuration? Re: refence configuration path Hi, @AlexG124, Thanks for the details. Could you please help us and let us know what are the MBDT toolbox version, as well as the MATLAB version that you are currently using? In case you are using S32K3 toolbox, there is a model example showcasing the referenced configuration workflow, under model_ref/s32k3xx_refconfig_s32ct folder. Here you will find a MATLAB script called s32k3xx_refconfig_update_paths_callback.m that could help in achieving your goal. It will be also helpful if you could let us know more details on your referenced configuration way of working, usage and application flow. Best regards, Dragos
View full article
S32DS 许可证到期 您好, 当我打开 S32DS 时,得到以下信息:   适用于 ARM 的 S32 设计工作室 ActivationId:8AEC-51FD-AB5B-6A4D 评估天数:9 功能版本:2.2 功能状态:评估(9 天) 延长许可证有效期需要哪些手续? 顺祝商祺! 桑德拉 Re: S32DS license expiring 你好 我已通知管理员延长您的许可证有效期。 顺祝商祺! Peter Re: S32DS license expiring 你好 您的许可证有效期延长至 2030 年。 顺祝商祺! Peter Re: S32DS license expiring 你好 我无法激活 S32DS,原因是图像问题,你们能帮我解决这个问题吗? HelenLi_0-1778831877838.pngHelenLi_0-1778831877838.pngHelenLi_0-1778831877838.png Re: S32DS license expiring 帮助! 我的S32DS IDE许可证即将到期。请问您能否帮我延长一下它的使用期限?谢谢 ! 许可证:1A99 90A8 2F06 339B Re: S32DS license expiring 你好: ActivationId:04E9-8F5A-8B1F-F9C8 需要延长许可证有效期 Re: S32DS license expiring 你好! 我的S32DS IDE许可证即将到期。请问您能否帮我延长一下它的使用期限?谢谢 ! 许可证号:EA09-8465-A8E8-F07B Re: S32DS license expiring 嗨,彼得, 我的S32DS v3.5许可证已过期。您能否帮忙将期限延长至 2030 年 9 月 16 日? 订单号:113445398 机器 ID:A5883F5CCBF60C6BECC55C5A0CC9D1C68DA192AD 激活码:A060-A074-B014-D67C 许可证页面显示“不允许退还此许可证”,没有“延期”按钮。 已附截图。 谢谢你!
View full article
Seeking guidance: se05x_Minimal fails in OP-TEE environment Hello NXP Community, I am attempting to run se05x_Minimal on our target board running Linux with OP-TEE. Following the solution recommended in this community post (How to integrate Plug and Trust MW into OP-TEE), we built the environment accordingly. In particular, for Step 2, we configured the setup without enabling "keep CAAM enabled". As a result of this configuration, the I2C bus connected to SE05x is managed by OP-TEE (Secure World), and the standard Linux I2C device node /dev/i2c-1 is not visible/available in the Normal World (Linux). When executing `./se05x_Minimal` directly from the Linux user-space console, we encounter the following error: App :INFO :Running ./se05x_Minimal App :INFO :If you want to over-ride the selection, use ENV=EX_SSS_BOOT_SSS_PORT or pass in command line arguments. App :INFO :PlugAndTrust_v04.07.01_20250519 App :INFO :Using default PlatfSCP03 keys. You can use keys from file using ENV=EX_SSS_BOOT_SCP03_PATH smCom :ERROR:opening failed... Failed to open the i2c bus: No such file or directory smCom :INFO :Pass i2c device address in the format : . smCom :INFO :Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1 smCom :ERROR:phPalEse_i2c_open_and_configure Failed retry smCom :ERROR:I2C init Failed: retval d smCom :ERROR:phPalEse_Init Failed smCom :ERROR: Failed to create physical connection with ESE sss :ERROR:SM_I2CConnect Failed. Status 7012 App :ERROR:sss_session_open failed App :ERROR:ex_sss_session_open Failed App :ERROR:!ERROR! ret != 0. Environment & Hardware Setup: Evaluation Board: MCIMX8M-WEVK (i.MX 8M Dual/Quad) Secure Element Board: OM-SE051ARD Secure Element: SE05x (Plug & Trust MW v04.07.01) OS: Linux (Normal World) + OP-TEE (Secure World) Middleware Options (CMake): -DPTMW_Host=iMXLinux, -DPTMW_SMCOM=T1oI2C Note: se05x_Minimal works fine if Linux kernel-space direct I2C (/dev/i2c-1) is enabled. It appears smCom is still attempting to open the physical Linux I2C device (/dev/i2c-X), which no longer exists in our Normal World environment. Could you please provide instructions on what we need to do or modify so that se05x_Minimal can run successfully in this setup? SE050 Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment @Kan_Li  Thank you very much for your detailed explanation and the C code samples. Following your guidance, we implemented a C application using the standard PKCS#11 API (libckteec.so.0) under Option 1 (OP-TEE exclusive I2C setup). All operations -- including key generation, AES encrypt/decrypt, RSA sign/verify, and RSA encrypt/decrypt -- are now working completely as expected. We appreciate your support in resolving this issue. Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment Hi @Uc_S , This is an excellent and important question. The short answer is: In Option 1 (OP-TEE exclusive I2C), the Plug & Trust MW SSS APIs cannot be used from Linux userspace directly. You must use the standard PKCS#11 C API via libckteec.so . Below is a detailed explanation and complete C code samples for all the operations you need. Why SSS APIs Cannot Be Used in This Setup The Plug & Trust MW SSS APIs ( sss_session_open , sss_key_store_set_key , sss_asymmetric_sign_digest , etc.) rely on a transport layer to communicate with the SE051. All supported transports ( T1oI2C , JRCP_V1_AM , etc.) ultimately require either Linux I2C access or a proxy server — neither of which is available when OP-TEE exclusively owns the I2C bus. The correct path in the OP-TEE exclusive setup is: Your C App → PKCS#11 C API (cryptoki.h) → libckteec.so → OP-TEE PKCS#11 TA → SE051 libckteec is provided by optee-client and implements the Cryptoki interface with the OP-TEE PKCS#11 TA as its backend. The TA in turn routes crypto operations to SE051 via OP-TEE's native I2C driver. Required Headers and Linking #include /* Standard Cryptoki header — from optee-client or OpenSC */ Compile and link: gcc -o my_app my_app.c -ldl # Or link directly: gcc -o my_app my_app.c /usr/lib/libckteec.so.0 At runtime, set the module path if using dynamic loading: #define PKCS11_MODULE "/usr/lib/libckteec.so.0" Initialization and Token Setup (call once at startup) #include #include #include #define CHECK_RV(rv, msg) \ if ((rv) != CKR_OK) { fprintf(stderr, "%s failed: 0x%lX\n", (msg), (rv)); goto cleanup; } /* User PIN — must match what was set with pkcs11-tool --init-pin */ static CK_UTF8CHAR user_pin[] = "1234"; static CK_ULONG user_pin_len = 4; CK_FUNCTION_LIST *p11 = NULL; /* Global function list pointer */ CK_SESSION_HANDLE session = CK_INVALID_HANDLE; int pkcs11_init(void) { CK_RV rv; CK_ULONG slot_count = 0; CK_SLOT_ID slot_id; CK_SLOT_ID slot_list[8]; /* Load function list — if using dynamic linking, use C_GetFunctionList() */ rv = C_Initialize(NULL_PTR); CHECK_RV(rv, "C_Initialize"); /* Get available slots */ rv = C_GetSlotList(CK_TRUE, NULL_PTR, &slot_count); CHECK_RV(rv, "C_GetSlotList (count)"); rv = C_GetSlotList(CK_TRUE, slot_list, &slot_count); CHECK_RV(rv, "C_GetSlotList"); slot_id = slot_list[0]; /* Use first slot — OP-TEE PKCS#11 TA */ /* Open a read-write session */ rv = C_OpenSession(slot_id, CKF_SERIAL_SESSION | CKF_RW_SESSION, NULL_PTR, NULL_PTR, &session); CHECK_RV(rv, "C_OpenSession"); /* Login as normal user */ rv = C_Login(session, CKU_USER, user_pin, user_pin_len); CHECK_RV(rv, "C_Login"); return 0; cleanup: return -1; } void pkcs11_cleanup(void) { C_Logout(session); C_CloseSession(session); C_Finalize(NULL_PTR); } Operation 1: Generate an RSA Key Pair and Store in SE051 int generate_rsa_keypair(CK_OBJECT_HANDLE *pub_key, CK_OBJECT_HANDLE *priv_key) { CK_RV rv; CK_MECHANISM mech = { CKM_RSA_PKCS_KEY_PAIR_GEN, NULL_PTR, 0 }; CK_ULONG key_bits = 2048; CK_BYTE pub_exponent[] = { 0x01, 0x00, 0x01 }; /* 65537 */ CK_BBOOL ck_true = CK_TRUE; CK_BBOOL ck_false = CK_FALSE; /* Key ID stored in SE051 NVM — choose a unique 4-byte ID */ CK_BYTE key_id[] = { 0x10, 0x10, 0x10, 0x10 }; CK_ATTRIBUTE pub_tmpl[] = { { CKA_MODULUS_BITS, &key_bits, sizeof(key_bits) }, { CKA_PUBLIC_EXPONENT, pub_exponent, sizeof(pub_exponent) }, { CKA_VERIFY, &ck_true, sizeof(ck_true) }, { CKA_ENCRYPT, &ck_true, sizeof(ck_true) }, { CKA_TOKEN, &ck_true, sizeof(ck_true) }, { CKA_ID, key_id, sizeof(key_id) }, }; CK_ATTRIBUTE priv_tmpl[] = { { CKA_SIGN, &ck_true, sizeof(ck_true) }, { CKA_DECRYPT, &ck_true, sizeof(ck_true) }, { CKA_TOKEN, &ck_true, sizeof(ck_true) }, { CKA_SENSITIVE, &ck_true, sizeof(ck_true) }, { CKA_EXTRACTABLE, &ck_false, sizeof(ck_false) }, { CKA_ID, key_id, sizeof(key_id) }, }; rv = C_GenerateKeyPair(session, &mech, pub_tmpl, sizeof(pub_tmpl) / sizeof(pub_tmpl[0]), priv_tmpl, sizeof(priv_tmpl) / sizeof(priv_tmpl[0]), pub_key, priv_key); CHECK_RV(rv, "C_GenerateKeyPair"); printf("RSA-2048 key pair generated. Private key stays in SE051 NVM.\n"); return 0; cleanup: return -1; } Operation 2: Generate an AES Key and Store in SE051 int generate_aes_key(CK_OBJECT_HANDLE *aes_key) { CK_RV rv; CK_MECHANISM mech = { CKM_AES_KEY_GEN, NULL_PTR, 0 }; CK_ULONG key_len = 32; /* 256-bit AES */ CK_BBOOL ck_true = CK_TRUE; CK_BBOOL ck_false = CK_FALSE; CK_BYTE key_id[] = { 0x20, 0x00, 0x00, 0x01 }; CK_ATTRIBUTE aes_tmpl[] = { { CKA_VALUE_LEN, &key_len, sizeof(key_len) }, { CKA_ENCRYPT, &ck_true, sizeof(ck_true) }, { CKA_DECRYPT, &ck_true, sizeof(ck_true) }, { CKA_TOKEN, &ck_true, sizeof(ck_true) }, { CKA_SENSITIVE, &ck_true, sizeof(ck_true) }, { CKA_EXTRACTABLE, &ck_false, sizeof(ck_false) }, { CKA_ID, key_id, sizeof(key_id) }, }; rv = C_GenerateKey(session, &mech, aes_tmpl, sizeof(aes_tmpl) / sizeof(aes_tmpl[0]), aes_key); CHECK_RV(rv, "C_GenerateKey (AES)"); printf("AES-256 key generated and stored in SE051.\n"); return 0; cleanup: return -1; } Operations 3 & 4: AES-CBC Encrypt / Decrypt int aes_encrypt(CK_OBJECT_HANDLE aes_key, const CK_BYTE *plaintext, CK_ULONG plaintext_len, CK_BYTE *ciphertext, CK_ULONG *ciphertext_len) { CK_RV rv; CK_BYTE iv[16] = { 0 }; /* All-zero IV for example; use a random IV in production */ CK_MECHANISM mech = { CKM_AES_CBC_PAD, iv, sizeof(iv) }; rv = C_EncryptInit(session, &mech, aes_key); CHECK_RV(rv, "C_EncryptInit"); rv = C_Encrypt(session, (CK_BYTE *)plaintext, plaintext_len, ciphertext, ciphertext_len); CHECK_RV(rv, "C_Encrypt"); return 0; cleanup: return -1; } int aes_decrypt(CK_OBJECT_HANDLE aes_key, const CK_BYTE *ciphertext, CK_ULONG ciphertext_len, CK_BYTE *plaintext, CK_ULONG *plaintext_len) { CK_RV rv; CK_BYTE iv[16] = { 0 }; /* Must match the IV used for encryption */ CK_MECHANISM mech = { CKM_AES_CBC_PAD, iv, sizeof(iv) }; rv = C_DecryptInit(session, &mech, aes_key); CHECK_RV(rv, "C_DecryptInit"); rv = C_Decrypt(session, (CK_BYTE *)ciphertext, ciphertext_len, plaintext, plaintext_len); CHECK_RV(rv, "C_Decrypt"); return 0; cleanup: return -1; } Operations 5 & 6: RSA Sign (private key stays in SE051) and Verify int rsa_sign(CK_OBJECT_HANDLE priv_key, const CK_BYTE *data, CK_ULONG data_len, CK_BYTE *signature, CK_ULONG *sig_len) { CK_RV rv; /* SHA256-PKCS1v1.5 — SE051 computes SHA-256 digest internally then signs */ CK_MECHANISM mech = { CKM_SHA256_RSA_PKCS, NULL_PTR, 0 }; rv = C_SignInit(session, &mech, priv_key); CHECK_RV(rv, "C_SignInit"); rv = C_Sign(session, (CK_BYTE *)data, data_len, signature, sig_len); CHECK_RV(rv, "C_Sign"); printf("RSA signature generated (%lu bytes). Private key never left SE051.\n", *sig_len); return 0; cleanup: return -1; } int rsa_verify(CK_OBJECT_HANDLE pub_key, const CK_BYTE *data, CK_ULONG data_len, const CK_BYTE *signature, CK_ULONG sig_len) { CK_RV rv; CK_MECHANISM mech = { CKM_SHA256_RSA_PKCS, NULL_PTR, 0 }; rv = C_VerifyInit(session, &mech, pub_key); CHECK_RV(rv, "C_VerifyInit"); rv = C_Verify(session, (CK_BYTE *)data, data_len, (CK_BYTE *)signature, sig_len); if (rv == CKR_OK) { printf("Signature verification: SUCCESS\n"); return 0; } else if (rv == CKR_SIGNATURE_INVALID) { printf("Signature verification: INVALID\n"); return 1; } CHECK_RV(rv, "C_Verify"); cleanup: return -1; } Operations 7 & 8: RSA Encrypt / Decrypt int rsa_encrypt(CK_OBJECT_HANDLE pub_key, const CK_BYTE *plaintext, CK_ULONG plaintext_len, CK_BYTE *ciphertext, CK_ULONG *ciphertext_len) { CK_RV rv; /* RSA-OAEP with SHA-256 — recommended over PKCS1 v1.5 for new designs */ CK_RSA_PKCS_OAEP_PARAMS oaep_params = { .hashAlg = CKM_SHA256, .mgf = CKG_MGF1_SHA256, .source = CKZ_DATA_SPECIFIED, .pSourceData = NULL, .ulSourceDataLen = 0 }; CK_MECHANISM mech = { CKM_RSA_PKCS_OAEP, &oaep_params, sizeof(oaep_params) }; rv = C_EncryptInit(session, &mech, pub_key); CHECK_RV(rv, "C_EncryptInit (RSA-OAEP)"); rv = C_Encrypt(session, (CK_BYTE *)plaintext, plaintext_len, ciphertext, ciphertext_len); CHECK_RV(rv, "C_Encrypt (RSA-OAEP)"); return 0; cleanup: return -1; } int rsa_decrypt(CK_OBJECT_HANDLE priv_key, const CK_BYTE *ciphertext, CK_ULONG ciphertext_len, CK_BYTE *plaintext, CK_ULONG *plaintext_len) { CK_RV rv; CK_RSA_PKCS_OAEP_PARAMS oaep_params = { .hashAlg = CKM_SHA256, .mgf = CKG_MGF1_SHA256, .source = CKZ_DATA_SPECIFIED, .pSourceData = NULL, .ulSourceDataLen = 0 }; CK_MECHANISM mech = { CKM_RSA_PKCS_OAEP, &oaep_params, sizeof(oaep_params) }; rv = C_DecryptInit(session, &mech, priv_key); CHECK_RV(rv, "C_DecryptInit (RSA-OAEP)"); rv = C_Decrypt(session, (CK_BYTE *)ciphertext, ciphertext_len, plaintext, plaintext_len); CHECK_RV(rv, "C_Decrypt (RSA-OAEP)"); printf("RSA decryption completed. Private key never left SE051.\n"); return 0; cleanup: return -1; } Accessing Existing Keys (without regenerating) If a key was previously generated and stored in SE051, retrieve it by CKA_ID without calling C_GenerateKey again: int find_key_by_id(CK_BYTE *key_id, CK_ULONG key_id_len, CK_OBJECT_CLASS obj_class, CK_OBJECT_HANDLE *handle) { CK_RV rv; CK_ULONG obj_count = 0; CK_ATTRIBUTE search_tmpl[] = { { CKA_CLASS, &obj_class, sizeof(obj_class) }, { CKA_ID, key_id, key_id_len }, }; rv = C_FindObjectsInit(session, search_tmpl, sizeof(search_tmpl) / sizeof(search_tmpl[0])); CHECK_RV(rv, "C_FindObjectsInit"); rv = C_FindObjects(session, handle, 1, &obj_count); CHECK_RV(rv, "C_FindObjects"); C_FindObjectsFinal(session); if (obj_count == 0) { fprintf(stderr, "Key not found in SE051\n"); return -1; } return 0; cleanup: C_FindObjectsFinal(session); return -1; } Usage example: CK_OBJECT_HANDLE priv_key; CK_BYTE key_id[] = { 0x10, 0x10, 0x10, 0x10 }; CK_OBJECT_CLASS priv_class = CKO_PRIVATE_KEY; find_key_by_id(key_id, sizeof(key_id), priv_class, &priv_key); Supported Mechanisms (verified on OP-TEE PKCS#11 TA + SE051) Operation Mechanism Constant Notes RSA key generation CKM_RSA_PKCS_KEY_PAIR_GEN 256–4096 bits AES key generation CKM_AES_KEY_GEN 16 or 32 bytes RSA sign/verify CKM_SHA256_RSA_PKCS PKCS#1 v1.5 RSA sign/verify (PSS) CKM_SHA256_RSA_PKCS_PSS PSS padding RSA encrypt/decrypt CKM_RSA_PKCS_OAEP OAEP recommended RSA encrypt/decrypt CKM_RSA_PKCS PKCS#1 v1.5 AES encrypt/decrypt CKM_AES_CBC_PAD CBC with PKCS#7 AES encrypt/decrypt CKM_AES_CBC CBC without padding AES encrypt/decrypt CKM_AES_CTR CTR mode ECC sign/verify CKM_ECDSA_SHA256 160–521 bits ECDH key agreement CKM_ECDH1_DERIVE   Can the SSS APIs Still Be Used at All? Yes — but only in the co-existence setup (Option 2) where Linux still has access to the I2C bus (i.e., the lf-6.12.y-i2c-disabled-se050 DTS patch has NOT been applied). In that case, you can use the SSS APIs as described in AN13030 Section 3.3 directly from Linux. If you choose Option 1 (OP-TEE exclusive), the Cryptoki/PKCS#11 C API shown above is the correct and only supported path from Linux userspace. Reference AN13030 Rev. 2.4, Section 3.3 — Full SSS API reference (for co-existence / non-OP-TEE builds) OP-TEE PKCS#11 TA test suite (pkcs11_1000.c): optee-test/host/xtest/pkcs11_1000.c — comprehensive C examples for all Cryptoki operations NXP GitHub: se05x-pkcs11 — NXP's PKCS#11 standalone library (alternative to libckteec.so for non-OP-TEE builds)   Hope that helps,   Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment @Kan_Li  Thank you very much for the clear and detailed explanation. We are currently considering using Option 1 or Option 2 depending on the stage of our future development (e.g., using Option 2 for initial testing/evaluation and Option 1 for production). Regarding Option 1 (OP-TEE PKCS#11 TA), we have a question about application development in C. If we would like to implement cryptographic operations such as key storage, signing / signature generation, signature verification, and encryption/decryption in a C program under Option 1, which approach should we take? Should we write a C program that directly calls standard PKCS#11 APIs (e.g., C_Initialize, C_CreateObject, C_SignInit, C_Sign, C_VerifyInit, C_Verify, etc.) via the OP-TEE PKCS#11 library (libckteec.so)? Or is it still possible/recommended to use the Plug & Trust MW SSS APIs (such as sss_key_store_set_key, sss_asymmetric_sign_digest, sss_asymmetric_verify_digest, sss_cipher_update, etc.) in this setup? If PKCS#11 APIs are required, could you please provide a simple sample code or reference guide for calling libckteec.so in C? Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment Hi @Uc_S , Thank you for the detailed report. The root cause is clear, and I can explain exactly why this happens and what your options are. Root Cause se05x_Minimal was built with -DPTMW_SMCOM=T1oI2C . This tells the smCom layer to open a physical Linux I2C device node ( /dev/i2c-X ) at session open time. Since you applied the lf-6.12.y-i2c-disabled-se050 DTS patch (Step 1 of the integration guide), that I2C controller is disabled in Linux Normal World — the device node simply does not exist. OP-TEE exclusively owns the I2C bus via CFG_IMX_I2C=y , and Linux cannot see or open it. This is by design — the DTS patch is what gives OP-TEE exclusive, uncontended access to SE051. The se05x_Minimal binary built with T1oI2C is fundamentally incompatible with this configuration. Your Two Options ✅ Option 1 — Use OP-TEE PKCS#11 TA (Recommended for Production) This is the intended Linux userspace path in the OP-TEE exclusive setup. Instead of running se05x_Minimal , use pkcs11-tool or OpenSSL with libckteec.so (the OP-TEE PKCS#11 TA library). The TA internally uses SE051 as its crypto backend via OP-TEE's native I2C driver. Quick verification that SE051 is reachable via PKCS#11: # List available PKCS#11 slots — SE051 should appear pkcs11-tool --module /usr/lib/libckteec.so.0 --list-slots # Get a random number from SE051 via OP-TEE pkcs11-tool --module /usr/lib/libckteec.so.0 --generate-random 16 | xxd If you see a slot and random bytes, SE051 is fully accessible through OP-TEE. There is no need to run se05x_Minimal — it duplicates what the PKCS#11 TA already provides. ✅ Option 2 — Co-existence Setup (Recommended for Development/Testing) If you specifically need to run se05x_Minimal and other Plug & Trust MW demos from Linux userspace, use the co-existence setup where Linux DTS still has I2C enabled (i.e., do not apply the I2C-disabled DTS patch). Steps: Step 1 — Revert the Linux DTS to keep I2C enabled in Normal World Build your imx8mq-evk.dtb (or equivalent) from the unmodified Linux DTS (without the lf-6.12.y-i2c-disabled-se050 patch). The I2C controller node for SE051 must remain enabled in Linux. Step 2 — Keep your existing cmake flags unchanged Your current cmake configuration is correct for co-existence: cmake -S . -B ./build/ -DPTMW_Applet=SE05X_C -DPTMW_SE05X_Ver=07_02 -DPTMW_Host=iMXLinux -DPTMW_SMCOM=T1oI2C -DPTMW_HostCrypto=OPENSSL -DPTMW_RTOS=Default -DPTMW_mbedTLS_ALT=None -DPTMW_SCP=SCP03_SSS -DPTMW_SE05X_Auth=PlatfSCP03 -DPTMW_Log=Silent -DCMAKE_BUILD_TYPE=Release -DPTMW_OpenSSL=3_0 -DPTMW_SE_RESET_LOGIC=1 Step 3 — Set the I2C port before running export EX_SSS_BOOT_SSS_PORT=/dev/i2c-1 ./se05x_Minimal Trade-off: In this mode, both OP-TEE and Linux share the I2C bus to SE051. OP-TEE uses it for RSA/ECC offload; Linux uses it for MW demos. Concurrent access is not arbitrated, which can cause APDU collisions under load. Acceptable for development, but not recommended for production. Summary Option I2C DTS se05x_Minimal OP-TEE exclusive Recommended For PKCS#11 TA ( libckteec.so ) Disabled ❌ Not needed ✅ Yes Production Co-existence (T1oI2C) Enabled ✅ Works ⚠️ Shared I2C Development/Testing Clarification on the Integration Guide The community post you referenced (Step 2 — without CAAM) configures OP-TEE to exclusively own I2C. The Linux-side MW compilation shown in that guide (with T1oI2C ) was intended for the initial verification step before switching to OP-TEE mode — not for use alongside the OP-TEE exclusive I2C setup. Once OP-TEE owns I2C exclusively, the correct Linux userspace interface is the OP-TEE PKCS#11 TA, not the Plug & Trust MW SSS API demos directly. Please let us know which option fits your use case and we can provide further guidance. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
View full article
MCXN947 HPDAC 反向移植 我正在将 Zephyr nxp_hpdac 驱动程序移植到 Zephyr 4.3,用于基于 MCXN947 的板。 上游驱动程序未使用设备初始化回调。然而,在 Zephyr 4.3 上,除非我在使用该外设之前显式初始化 DAC2 时钟、SPC 模拟模块并进行RESET,否则 HPDAC 无法正常工作。 我添加了一个 nxp_hpdac_init() 函数,该函数执行以下步骤: CLOCK_SetClkDiv(kCLOCK_DivDac2Clk, 1U) CLOCK_AttachClk(kFRO_HF_to_DAC2) CLOCK_EnableClock(kCLOCK_Dac2) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac2) SPC_EnableLowPowerModeAnalogModules(SPC0, kSPC_controlDac2) RESET_PeripheralReset(kDAC2_RST_SHIFT_RSTn) DAC14_DoSoftwareReset() DAC14_DoFIFOReset() SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref) 这些初始化步骤基于 MCXN947 参考手册,并使用相应的 MCUX SDK API 实现。 init 函数通过 DEVICE_DT_INST_DEFINE() 注册为设备初始化回调函数。经过这些更改,HPDAC 可以正常工作了。 我还检查了 Zephyr MCUX SYSCON 时钟控制驱动程序和 mcux_lpc_syscon_clock.h 文件。虽然有绑定,但我找不到 HPDAC/DAC2 时钟标识符或该外设的时钟控制实现,因此我目前直接使用 MCUX SDK 时钟、SPC 和复位 API。 我的问题是: 1. 在向后移植 MCXN947 HPDAC 驱动程序时,这种方法是否正确? 2. 在较新的 Zephyr 版本中,这些资源是在其他地方初始化的,还是上游 nxp_hpdac 驱动程序假定它们已经配置好了? 3. HPDAC 设备初始化回调是否是进行此 MCXN947 特定初始化的正确位置,还是应该在 Zephyr 的其他地方处理这些步骤? 我已附上完整的移植驱动程序供您参考。 模拟(ADC|CMP|DAC|运算放大器) 时钟|计时器 MCX N 回复: MCXN947 HPDAC backport 嗨@wesOS 1. 在向后移植 MCXN947 HPDAC 驱动程序时,这种方法是否正确? 是的,这对于向后移植来说是一个合理且实用的方法。如果 Zephyr 4.3 环境中的其他位置没有初始化所需的 DAC2 时钟、SPC 模拟模块、VREF 和 RESET 资源,则必须在驱动程序中执行初始化,以确保 HPDAC 正确运行。 2. 在较新的 Zephyr 版本中,这些资源是在其他地方初始化的,还是上游 nxp_hpdac 驱动程序假定它们已经配置好了? HPDAC 支持已在上游添加: https://github.com/zephyrproject-rtos/zephyr/pull/104642 然而,我使用当前的上游实现进行了快速验证,发现 DAC2 时钟似乎没有配置。例如,在我的测试环境中,CLOCK_GetDacClkFreq(2) 报告为 0 Hz,而配置 DAC 时钟后,相应的 MCUX SDK 示例报告为 48 MHz。 根据这一观察结果,当前驱动程序似乎假定某些设备资源已经配置完毕。请您也检查一下您那边的时钟配置路径好吗? 我也会将此情况报告给我们的 Zephyr 团队,以便他们进一步调查,如果确认存在时钟初始化错误,我将与他们合作解决这个问题。 3. HPDAC 设备初始化回调是否是进行此 MCXN947 特定初始化的正确位置,还是应该在 Zephyr 的其他地方处理这些步骤? 对于向后移植来说,将此逻辑放在 HPDAC 设备初始化回调中是一个实用且可接受的解决方案。 也就是说,MCXN947 特有的 DAC2 时钟、SPC、VREF 和 RESET 配置最好明确地隔离为 SoC 特有的功能,而不是作为通用 HPDAC 行为嵌入。从长远来看,这些资源最好通过 Zephyr 基础设施进行管理,例如时钟、RESET 或电源管理单元框架(如适用)。 BR 哈里 回复: MCXN947 HPDAC backport 谢谢,我已经仔细检查了我的 MCXN947 设置中的 DAC2 时钟路径。 在 HPDAC 驱动程序配置时钟之前: dac_nxp_hpdac: 配置前的 DAC2 时钟:0 Hz 后: CLOCK_SetClkDiv(kCLOCK_DivDac2Clk, 1U); CLOCK_AttachClk(kFRO_HF_to_DAC2); CLOCK_EnableClock(kCLOCK_Dac2); 我得到: dac_nxp_hpdac:配置后的 DAC2 时钟:48000000 Hz 我这边也出现了同样的情况:在 HPDAC 驱动程序初始化之前,DAC2 时钟没有进行配置。 你关于将 MCXN947 特有的资源处理隔离的解释也很有道理。 我现在主要想了解的是,你希望最终的上游解决方案如何划分初始化过程。 例如,您是否希望 DAC2 时钟配置、SPC/VREF 设置和 RESET 处理分别移至其对应的 Zephyr/SoC 基础架构中,并使用 `dac_nxp_hpdac.c` 文件?只保留通用的HPDAC初始化? 我主要想了解每个初始化步骤的预期所有权,并保持向后移植与该方向合理一致。 谢谢。 BR 瓦西姆 回复: MCXN947 HPDAC backport 嗨@wesOS 感谢您确认结果。我们两人都观察到,在配置时钟之前 DAC2 时钟频率为 0 Hz,配置时钟之后为 48000000 Hz,这强烈表明 DAC2 时钟在 HPDAC 驱动程序运行之前没有初始化。 我已经将此漏洞修复报告给了我们内部的 Zephyr 团队。 在进一步研究 FRDM-MCXN947 的实现之后,我发现现有的 DAC 时钟初始化目前是在板级处理的,而不是在 DAC 驱动程序本身中处理的。 zephyr/boards/nxp/frdm_mcxn947/board.c 函数: void board_early_init_hook(void) 对 DAC0 和 DAC1 执行时钟和 SPC 初始化: #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0)) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0); CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u); CLOCK_AttachClk(kFRO_HF_to_DAC0); CLOCK_EnableClock(kCLOCK_Dac0); #endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac1)) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac1); CLOCK_SetClkDiv(kCLOCK_DivDac1Clk, 1u); CLOCK_AttachClk(kFRO_HF_to_DAC1); CLOCK_EnableClock(kCLOCK_Dac1); #endif 根据目前的实现方式,我希望解决方案能够与现有的板设计保持一致。换句话说,可以将 DAC2 时钟初始化添加到 board_early_init_hook() 中,与现有的 DAC0/DAC1 初始化一起,而不是将特定于板的时钟设置放入通用的 HPDAC 驱动程序中。 BR 哈里
View full article
I2C read and write using s32k144 MBD toolbox Hello, I am using s32k144 to read and write data from an external EEPROM. I will attach the model below. I am able to write the data but the read returns 255+NACK as output. Am i missing something here Sriram_0-1737789999186.png Sriram_1-1737790013461.png Is there a way to specify the register address of the EEPROM in the I2Cmaster block Sriram_2-1737790096449.png Can you guys help me out with this issue. Thanks Re: I2C read and write using s32k144 MBD toolbox Hi, I am also facing the same issue with I2C communication using the S32K144 as the master and the ST M24C04 EEPROM as the slave. Since you are using the same microcontroller and EEPROM, I wanted to check whether you were able to find a solution. If you have resolved this issue, could you please share the solution or let me know what fixed it? Thank you in advance for your help. Re: I2C read and write using s32k144 MBD toolbox I m using M24C02-DRE EEPROM
View full article
S32 Design Studio Installation Issue I am facing issues in S32 Design Studio (V3.6.4) Installation. The installation's progress bar finishes immediately once I start the installation, but I could not see any installed application. Please guide me on resolving this issue. The system specs are Windows 11, 16GB RAM, 1TB SSD. Note this system is under our Company's IT policies. Re: S32 Design Studio Installation Issue Please find below the requested log files. We tried to do the installation twice, but it was not successful. Re: S32 Design Studio Installation Issue Hi @ashutoshsahu  Could you please share the installation log file (.log)? It should be located under: C:\NXP\S32DS.3.6.4\_S32 Design Studio for S32 Platform 3.6.4_installation\Logs BR, VaneB Re: S32 Design Studio Installation Issue Hi @ashutoshsahu  I have reviewed the installation logs and identified an important error that occurred when the installer attempted to run powershell -ExecutionPolicy Bypass -File parallel.ps1: "This program is blocked by group policy. For more information, contact your system administrator." Based on this error, it may be worth checking with your IT team to verify that there are no security policies, Group Policy restrictions, firewall rules, or proxy settings that could be preventing the PowerShell script from running correctly. 
View full article
「スマートエネルギー」太陽光発電に関する意見 今日はスマートエナジーという会社の訪問販売員が何人か来て、太陽光パネルについて話したがっていました。太陽光発電に興味はあるのですが、初期投資をする資金がありません。そこで、初期費用ゼロで利用できる政府資金による制度があると聞きました。 もちろん、私は非常に懐疑的です。彼らと取引したことのある方からのご意見をぜひお聞かせください。 Re: Opinions on "Smart Energy" solar こんにちは、 時には「前払い0ドル」という提案は、実際には第三者の会社が屋根にパネルを無料で設置してくれることもありますが、その会社がシステムの所有者です。クリーンエネルギーの株式を取得することはできず、その代わりに、発電された電力を購入する長期契約(多くの場合20年から25年)に縛られることになる。これらは後で家を売るのを複雑にすることがあります。 よろしくお願いします
View full article
Secondary failed allocate mbuff from DPDK Pool hi All, Using : LX2160  LSDK 2108 main  MC firmware version: 10.32.0 DPDK Version : dpdk_19_11_tags_LSDK20.04-isc-09 Primary ( DPDK ) Process : Create a mbuff Pool using [ rte_pktmbuf_pool_create("dlmempool", ] Secondary ( DPDK ) Process : fails to allocate mbuff using API [ rte_pktmbuf_alloc(mempool) ] In Secondary i can see mempool is correct. I can see mbuff available is full. The failure happens for 1st mbuff allocation using  rte_pktmbuf_alloc. Any solution for this. Thanks. Re: Secondary failed allocate mbuff from DPDK Pool thanks i will try these options and update you by tomorrow Re: Secondary failed allocate mbuff from DPDK Pool Hello, The secondary process must map hugepages at the same virtual address as the primary. If ASLR is active, the secondary will resolve the mempool pointer to a different virtual address, causing the first allocation to fail. echo 0 > /proc/sys/kernel/randomize_va_space   Run this before launching either the primary or secondary process. 2. Provision Sufficient DPMCP Objects Create as many DPMCP objects as the total number of processes (primary + secondary). For 1 primary + 1 secondary, you need at least 2 DMPCPs: export DPMCP_COUNT=3 # for 1 Primary + 2 Secondary (always provision +1 as buffer) ./dynamic_dpl.sh dpmac.X 3. Provision Sufficient DPIO Objects Each process needs its own DPIO portals. The formula is: (Total Processes) × (cores per process + 1 extra per process) For example, 1 primary (2 cores) + 1 secondary (2 cores) = at minimum 9 DPIOs. export DPIO_COUNT=20 # set generously 4. Correctly Blacklist/Whitelist Devices in the Secondary The secondary process must NOT re-initialize I/O devices (dpni, dpbp, dpcon, dpseci). Only dpio and dpmcp should be initialized by the secondary. Pass the correct blacklist flags: # Secondary process example — blacklist all dpni/dpbp/dpcon, allow only dpio + dpmcp ./your_secondary_app --proc-type=secondary \ -b fslmc:dpni.X \ -b fslmc:dpbp.X \ -b fslmc:dpcon.X \ -- [app args]   Or alternatively, explicitly whitelist only the dpio and dpmcp objects assigned to the secondary: ./your_secondary_app --proc-type=secondary \ -w fslmc:dpio.Y \ -w fslmc:dpmcp.Z \ -- [app args] 5. Use --proc-type=secondary EAL Argument Ensure the secondary is launched with the correct EAL flag: ./your_secondary_app -c -n 1 --proc-type=secondary ...   Or use --proc-type=auto to let DPDK auto-detect. 6. Verify the Mempool Lookup in Secondary In the secondary, do not call rte_pktmbuf_pool_create again. Instead, look up the existing pool created by the primary: // In secondary process: struct rte_mempool *mempool = rte_mempool_lookup("dlmempool"); if (mempool == NULL) { // Error: pool not found — ASLR or hugepage mapping issue } struct rte_mbuf *m = rte_pktmbuf_alloc(mempool);     If rte_mempool_lookup returns a valid non-NULL pointer but rte_pktmbuf_alloc still returns NULL, the issue is almost certainly the DPIO portal not being initialized for the secondary's thread/core.   Regards Re: Secondary failed allocate mbuff from DPDK Pool thanks @Bio_TICFSL for the quick solution
View full article
关于“智能能源”太阳能的观点 今天有几个来自 Smart Energy 的推销员上门推销太阳能电池板。我对太阳能很感兴趣,但没有足够的资金进行前期投资,他们提到有一个政府资助的计划,无需预付任何费用。 我自然非常怀疑。很想听听和他们打过交道的人的意见。 Re: Opinions on "Smart Energy" solar 你好, 有时,“0 美元预付款”的推销实际上意味着第三方公司免费将太阳能电池板安装在你的屋顶上,但系统的所有权归他们所有。你无法获得清洁能源权益,反而会被锁定在一份长期合同(通常是 20 到 25 年)中,购买他们生产的电力。这些都可能使日后卖房变得复杂。 此致
View full article
NXP S32k118 I2C 仿真 你好, 我正在评估一种方法,即在不使用 I2C 多路复用器的情况下,从 S32K118 (Q48) 主设备同时驱动 10 个地址相同的 I2C 从设备。 我的计划是使用硬件定时器生成时钟来模拟 10 个并行的 I2C 总线,并结合 DMA 传输来同时更新同一端口上的 10 个 GPIO 引脚。 能否帮忙确认一下 S32K118 的 DMA 和定时器外设是否支持以这种方式触发端口范围的 GPIO 更新?这种架构是否存在我需要注意的硬件限制或特殊情况? 顺祝商祺! Re: NXP S32k118 I2C emulation 嗨@Luke_John , 是的,这种架构从根本上来说是支持的。 请参阅 S32K1xx 系列参考手册,修订版 14: 第 13.3.1 节 GPIO 寄存器描述。 如您所见,所有 GPIO 端口均可通过 32 位寄存器访问。 第 17.4.1 节 “使用 GPIO 端口驱动或采样波形 通过配置 DMA 将数据传输到一个或多个 GPIO 端口,可以使用存储在片上存储器中的表格数据创建复杂的波形。反之,利用DMA定期从一个或多个GPIO端口传输数据,可以对复杂的波形进行采样,并将结果以表格形式存储在片上存储器中。 DMA 传输可以通过定时器经由 DMAMUX、TRGMUX 触发。 必须将交叉开关编程为轮询仲裁(将 MCM_CPCR[CBRR] 配置为“1”),才能实现无缝 DMA 传输。 此致, 丹尼尔
View full article
从 DPDK 池分配 mbuff 失败 大家好, 使用:LX2160 LSDK 2108 主程序 MC固件版本:10.32.0 DPDK 版本:dpdk_19_11_tags_LSDK20.04-isc-09 主进程 (DPDK):使用 [ rte_pktmbuf_pool_create("dlmempool", ] 创建 mbuff 池 辅助(DPDK)进程:使用 API [ rte_pktmbuf_alloc(mempool) ] 分配 mbuff 失败 在辅助内存池中,我可以看到内存池是正确的。我看到mbuff可用空间已满。第一次使用 rte_pktmbuf_alloc 进行 mbuff 分配时发生失败。 有什么解决办法吗?谢谢。 Re: Secondary failed allocate mbuff from DPDK Pool 谢谢,我会尝试这些方法,明天再向您汇报。 Re: Secondary failed allocate mbuff from DPDK Pool 你好, 辅助进程必须将大页映射到与主进程相同的虚拟地址。如果 ASLR 处于活动状态,则辅助内存池指针将解析到不同的虚拟地址,导致第一次内存分配失败。 echo 0 > /proc/sys/kernel/randomize_va_space   在启动主进程或辅助进程之前运行此程序。 2. 配置充足的DPMCP对象 创建与进程总数(主进程 + 辅助进程)相同的 DPMCP 对象数量。对于 1 个主要处方药 + 1 个次要处方药,您至少需要 2 个 DMPCP: export DPMCP_COUNT=3 # for 1 Primary + 2 Secondary (always provision +1 as buffer) ./dynamic_dpl.sh dpmac.X 3. 配置足够的DPIO对象 每个流程都需要自己的 DPIO 门户。公式为: (总进程数)×(每个进程的核心数 + 每个进程额外 1 个核心) 例如,1 个主处理器(2 个核心)+ 1 个辅助处理器(2 个核心)= 至少 9 个 DPIO。 export DPIO_COUNT=20 # set generously 4. 在辅助设备中正确设置黑名单/白名单设备 辅助进程不得重新初始化 I/O 设备(dpni、dpbp、dpcon、dpseci)。只有 dpio 和 dpmcp 应该由辅助节点初始化。传递正确的黑名单标志: # Secondary process example — blacklist all dpni/dpbp/dpcon, allow only dpio + dpmcp ./your_secondary_app --proc-type=secondary \ -b fslmc:dpni.X \ -b fslmc:dpbp.X \ -b fslmc:dpcon.X \ -- [app args]   或者,也可以明确地将分配给辅助节点的 dpio 和 dpmcp 对象列入白名单: ./your_secondary_app --proc-type=secondary \ -w fslmc:dpio.Y \ -w fslmc:dpmcp.Z \ -- [app args] 5. 使用 --proc-type=secondary EAL 参数 确保备用服务器使用正确的 EAL 标志启动: ./your_secondary_app -c -n 1 --proc-type=secondary ...   或者使用 --proc-type=auto 让 DPDK 自动检测。 6. 验证辅助内存池查找 在辅助节点中,不要再次调用 rte_pktmbuf_pool_create 。相反,查找主节点创建的现有池: // In secondary process: struct rte_mempool *mempool = rte_mempool_lookup("dlmempool"); if (mempool == NULL) { // Error: pool not found — ASLR or hugepage mapping issue } struct rte_mbuf *m = rte_pktmbuf_alloc(mempool);     如果 rte_mempool_lookup 返回一个有效的非 NULL 指针,但 rte_pktmbuf_alloc 仍然返回 NULL,则问题几乎肯定是辅助线程/核心的 DPIO 门户没有被初始化。   此致 Re: Secondary failed allocate mbuff from DPDK Pool 感谢@Bio_TICFSL的快速解决方案
View full article
S32K31XEVB-Q100FlexCAN0 — Loopback works fine, but no reception with external CANoe Tool Board: S32K311-EVB Module: FlexCAN0 Tool: Vector CANoe connected via J8 connector Debug probe:  J-Link  I am implementing the CAN protocol on the S32K311-EVB using FlexCAN0. Loopback mode test (working): I first implemented and tested FlexCAN0 in internal loopback mode. This worked successfully — messages transmitted were correctly received back through my "void CanIf_RxIndication(const Can_HwType* Mailbox, const PduInfoType* PduInfoPtr )"  handling function, confirming that my basic FlexCAN0 configuration (clock setup, bit timing, message buffer initialization) is functioning correctly. External communication test (not working): I then moved to testing external CAN communication: Configure PTA6 and PTA7 pin in pin configuration. Connected Vector CANoe to the board via the J8 connector. In CANoe configuration, I unchecked "CAN Loopback Mode." Attach 12 V Adapter  Started CANoe transmission — CANoe shows it is sending CAN frames. However, on the S32K311 side, nothing is received — CanIf_RxIndication(the same function that worked correctly in loopback mode) is never called/triggered. For debugging i use segger RTT viewer using JTAG Configuration Sami2098_0-1789478804307.pngSami2098_0-1789478804307.pngSami2098_0-1789478804307.png Sami2098_1-1789478831337.pngSami2098_1-1789478831337.pngSami2098_1-1789478831337.png Sami2098_2-1789478911944.pngSami2098_2-1789478911944.pngSami2098_2-1789478911944.png Sami2098_3-1789478932611.pngSami2098_3-1789478932611.pngSami2098_3-1789478932611.png  Best regards.   Re: S32K31XEVB-Q100FlexCAN0 — Loopback works fine, but no reception with external CANoe Tool Hello @Sami2098, Could you share RTD version you are currently using? There are some examples in our community you can use as reference:  Re: CAN Example for S32K311 - NXP Community Example S32K312 CAN Transmit & Receive Using Polling mode DS3.5 RTD300 [RTD600 MCAL & IP] S32K3X4EVB-T172 FlexCAN Example Interrupt/Polling FlexCAN configuration overall looks OK. Can you confirm PTA6/7 are configured as input and output, respectively, and you are indeed calling Siul2_Port_Ip_Init() API to initialize Port? Julin_AragnM_2-1789514266922.pngJulin_AragnM_2-1789514266922.pngJulin_AragnM_2-1789514266922.png Since you are using S32K1XEVB, transceiver used is FS23, and when the FS23 is in Debug mode, the CAN transceiver is set to Active mode by default, thus there is no need to set CAN_MODE = 0b1x. I would also suggest checking that the bitrate and sampling point configured is the same between S32K311<->CANoe. Lastly, if you have a logic analyzer or an oscilloscope, could you share the CANTXD, CANRXD, CANH and CANL signals? Best regards, Julián Re: S32K31XEVB-Q100FlexCAN0 — Loopback works fine, but no reception with external CANoe Tool Hi Julián_AragónM Thanks for looking into this. I found the root cause — it was actually a CANoe channel bus configuration issue on my end, not a problem with the S32K311 CAN driver configuration. After correcting the CANoe Vector configuration, reception is working fine now. Follow-up question: I'm currently running at 500 kbps, and I understand that if I switch to a different baud rate (e.g., 125 kbps), several dependent parameters need to be recalculated — such as the Prescaler, Propagation Segment, Phase Segment 1, Phase Segment 2, and Resync Jump Width — to maintain correct bit timing and sample point relative to the CAN peripheral clock. Could someone point me to a reference/guide document that explains: How these bit timing parameters (Prescaler, Prop Seg, PS1, PS2, SJW) relate to and are derived for different target baud rates. Recommended sample point ranges for different baud rates in an automotive/industrial context. Any official NXP application note or reference specific to the S32K3xx FlexCAN MCAL (AUTOSAR) configuration tool for bit timing calculation. I'm using the MCAL layer in AUTOSAR mode (S32 Configuration Tool for Can driver configuration), so a guide aligned with this configuration flow (rather than register-level FlexCAN programming alone) would be especially helpful. Thanks in advance for your guidance. Re: S32K31XEVB-Q100FlexCAN0 — Loopback works fine, but no reception with external CANoe Tool Hello @Sami2098, 1. The chapter 73.3.10.8 (Protocol timing) from S32K3XX Reference Manual Rev. 12 explains bit timing configuration, and its various parameters. 2. This really depends on your application and configuration; however, nominal bitrates include 125 kbps, 250 kbps, and 500 kbps. 3. You can refer to our FlexCAN bit timing calculation sheet. You can also refer to the S32K3XX FlexCAN with RTD Training sildes. Best regards, Julián
View full article
S32DS for ARM 2018.R1 デバッグ問題 ARM 2018.R1用のS32DSでチップのデバッグ時に問題が発生しS32K146、以下の通りです: 送信後にGDBバージョンを特定できませんでした:D:\S32DS\eclipse\./Cross_Tools/gcc-arm-none-eabi-4_9/bin/arm-none-eabi-gdb --version、応答: しかし、Jlinkはチップの編集や消去、プログラムが可能です。私はARM 2018.R1のS32DSでデバッグしていません。助けてください。ありがとうございます! Re: S32DS for ARM 2018.R1 debug Problem Hi@lyz あなたの質問の意味がよく分かりませんでした。エラーのスクリーンショットを投稿してもらえますか?
View full article
S32DS for ARM 2018.R1 调试问题 使用 S32DS for ARM 2018.R1 调试 S32K146 芯片时出现问题,具体如下: 发送以下命令后无法确定 GDB 版本:D:\S32DS\eclipse\../Cross_Tools/gcc-arm-none-eabi-4_9/bin/arm-none-eabi-gdb --version,响应如下: 但是,Jlink 可以连接、擦除和编程芯片。我现在无法使用 S32DS for ARM 2018.R1 进行调试,请帮帮我,谢谢! Re: S32DS for ARM 2018.R1 debug Problem 嗨@lyz 我不太明白你的问题。能否提供一下错误截图?
View full article